October 2014 - coreboot-gerrit

New patch to review for coreboot: 9d73504 superio/fintek/f81216h: Implement device support
by Edward O'Callaghan Oct. 31, 2014

Oct. 31, 2014

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7309 -gerrit commit 9d735045c0fa2c4541f522ff70a8a11756b757e6 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Nov 1 10:19:58 2014 +1100 superio/fintek/f81216h: Implement device support Change-Id: I20a34b569f109dd12af29e9e0cee8f7f6b8ebb80 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/superio/fintek/Kconfig | 4 ++ src/superio/fintek/Makefile.inc | 1 + src/superio/fintek/f81216h/Makefile.inc | 22 ++++++++++ src/superio/fintek/f81216h/chip.h | 40 +++++++++++++++++ src/superio/fintek/f81216h/early_serial.c | 68 +++++++++++++++++++++++++++++ src/superio/fintek/f81216h/f81216h.h | 46 ++++++++++++++++++++ src/superio/fintek/f81216h/superio.c | 71 +++++++++++++++++++++++++++++++ 7 files changed, 252 insertions(+) diff --git a/src/superio/fintek/Kconfig b/src/superio/fintek/Kconfig index f577898..e9cbe74 100644 --- a/src/superio/fintek/Kconfig +++ b/src/superio/fintek/Kconfig @@ -47,6 +47,10 @@ config SUPERIO_FINTEK_F71889 bool select SUPERIO_FINTEK_COMMON_ROMSTAGE +config SUPERIO_FINTEK_F81216H + bool +# N.B. 'special romstage' + config SUPERIO_FINTEK_F81865F bool select SUPERIO_FINTEK_COMMON_ROMSTAGE diff --git a/src/superio/fintek/Makefile.inc b/src/superio/fintek/Makefile.inc index 1b11336..5756393 100644 --- a/src/superio/fintek/Makefile.inc +++ b/src/superio/fintek/Makefile.inc @@ -26,4 +26,5 @@ subdirs-y += f71863fg subdirs-y += f71869ad subdirs-y += f71872 subdirs-y += f71889 +subdirs-y += f81216h subdirs-y += f81865f diff --git a/src/superio/fintek/f81216h/Makefile.inc b/src/superio/fintek/f81216h/Makefile.inc new file mode 100644 index 0000000..f473ef2 --- /dev/null +++ b/src/superio/fintek/f81216h/Makefile.inc @@ -0,0 +1,22 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +romstage-$(CONFIG_SUPERIO_FINTEK_F81216H) += early_serial.c +ramstage-$(CONFIG_SUPERIO_FINTEK_F81216H) += superio.c diff --git a/src/superio/fintek/f81216h/chip.h b/src/superio/fintek/f81216h/chip.h new file mode 100644 index 0000000..459b5df --- /dev/null +++ b/src/superio/fintek/f81216h/chip.h @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SUPERIO_FINTEK_F81216H_CHIP_H +#define SUPERIO_FINTEK_F81216H_CHIP_H + +#include <stdint.h> + +/* Member variables are defined in devicetree.cb. */ +struct superio_fintek_f81216h_config { + /** + * KEY1 KEY0 Enter key + * 0 0 0x77 (default) + * 0 1 0xA0 + * 1 0 0x87 + * 1 1 0x67 + * + * See page 17 of data sheet. + */ +// uint8_t ldn_conf_key_mode; +}; + +#endif /* SUPERIO_FINTEK_F81216H_CHIP_H */ diff --git a/src/superio/fintek/f81216h/early_serial.c b/src/superio/fintek/f81216h/early_serial.c new file mode 100644 index 0000000..6b667df --- /dev/null +++ b/src/superio/fintek/f81216h/early_serial.c @@ -0,0 +1,68 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <device/pnp.h> +#include <stdint.h> +#include "fintek.h" + +static u8 f81216h_entry_key; +#define FINTEK_EXIT_KEY 0xAA + +static void pnp_enter_conf_state(pnp_devfn_t dev) +{ + u16 port = dev >> 8; + outb(f81216h_entry_key, port); + outb(f81216h_entry_key, port); +} + +static void pnp_exit_conf_state(pnp_devfn_t dev) +{ + u16 port = dev >> 8; + outb(FINTEK_EXIT_KEY, port); +} + +/* Bring up early serial debugging output before the RAM is initialized. */ +void f81216h_enable_serial(pnp_devfn_t dev, u16 iobase, enum mode_key k) +{ + switch(k) { + MODE_6767: + f81216h_entry_key = 0x67; + break; + MODE_7777: + f81216h_entry_key = 0x77; + break; + MODE_8787: + f81216h_entry_key = 0x87; + break; + MODE_A0A0: + f81216h_entry_key = 0xa0; + break; + default: + f81216h_entry_key = 0x77; /* (safe to be hw default) */ + } + + pnp_enter_conf_state(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, iobase); + pnp_set_enable(dev, 1); + pnp_exit_conf_state(dev); +} diff --git a/src/superio/fintek/f81216h/f81216h.h b/src/superio/fintek/f81216h/f81216h.h new file mode 100644 index 0000000..37e7753 --- /dev/null +++ b/src/superio/fintek/f81216h/f81216h.h @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SUPERIO_FINTEK_F81216H_H +#define SUPERIO_FINTEK_F81216H_H + +/* Logical Device Numbers (LDN). */ +#define F81216H_SP1 0x00 /* UART1 (+CIR mode) */ +#define F81216H_SP2 0x01 /* UART2 */ +#define F81216H_SP3 0x02 /* UART3 */ +#define F81216H_SP4 0x03 /* UART4 */ +#define F81216H_WDT 0x08 /* WDT */ + +/** + * The PNP config entry key is parameterised + * by two bits on this Super I/O with 0x77 as + * the default key. + * See page 17 of data sheet for details. + */ +enum { + MODE_6767, + MODE_7777, + MODE_8787, + MODE_A0A0, +} mode_key; + +void f81216h_enable_serial(pnp_devfn_t dev, u16 iobase, enum mode_key k); + +#endif /* SUPERIO_FINTEK_F81216H_H */ diff --git a/src/superio/fintek/f81216h/superio.c b/src/superio/fintek/f81216h/superio.c new file mode 100644 index 0000000..a56c60c --- /dev/null +++ b/src/superio/fintek/f81216h/superio.c @@ -0,0 +1,71 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <device/device.h> +#include <device/pnp.h> +#include <superio/conf_mode.h> +#include <console/console.h> +#include <stdlib.h> + +#include "chip.h" +#include "f81216h.h" + +static void f81216h_init(struct device *dev) +{ + if (!dev->enabled) + return; + + switch(dev->path.pnp.device) { + case F81216H_SP1: + case F81216H_SP2: + case F81216H_SP3: + case F81216H_SP4: + case F81216H_WDT: + break; + } +} + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_alt_enable, + .init = f81216h_init, + .ops_pnp_mode = &pnp_conf_mode_7777_aa, /* TODO: make configurable */ +}; + +static struct pnp_info pnp_dev_info[] = { + { &ops, F81216H_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, + { &ops, F81216H_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, + { &ops, F81216H_SP3, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, + { &ops, F81216H_SP4, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, + { &ops, F81216H_WDT, }, +}; + +static void enable_dev(struct device *dev) +{ + pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +struct chip_operations superio_fintek_f81216h_ops = { + CHIP_NAME("Fintek F81216H/D/DG/F/FG Super I/O") + .enable_dev = enable_dev +};

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New patch to review for coreboot: 0832b3d superio/common/conf_mode.c: Introduce 'new' enter/exit keys for SIO's
by Edward O'Callaghan Oct. 31, 2014

Oct. 31, 2014

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7308 -gerrit commit 0832b3d51d415c901fb8b1438b8fd19eca2b84d1 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Nov 1 09:14:58 2014 +1100 superio/common/conf_mode.c: Introduce 'new' enter/exit keys for SIO's Super I/O manufactures have found new and innovative ways to enter and exit out of LDN config in PNP config space. Change-Id: Id3f5882664f1b2b18b49f32373430cf4b037ad22 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/superio/common/conf_mode.c | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/src/superio/common/conf_mode.c b/src/superio/common/conf_mode.c index 271d4ef..92bd7a3 100644 --- a/src/superio/common/conf_mode.c +++ b/src/superio/common/conf_mode.c @@ -28,12 +28,30 @@ void pnp_enter_conf_mode_55(struct device *dev) outb(0x55, dev->path.pnp.port); } +void pnp_enter_conf_mode_6767(struct device *dev) +{ + outb(0x67, dev->path.pnp.port); + outb(0x67, dev->path.pnp.port); +} + +void pnp_enter_conf_mode_7777(struct device *dev) +{ + outb(0x77, dev->path.pnp.port); + outb(0x77, dev->path.pnp.port); +} + void pnp_enter_conf_mode_8787(struct device *dev) { outb(0x87, dev->path.pnp.port); outb(0x87, dev->path.pnp.port); } +void pnp_enter_conf_mode_a0a0(struct device *dev) +{ + outb(0xa0, dev->path.pnp.port); + outb(0xa0, dev->path.pnp.port); +} + void pnp_exit_conf_mode_aa(struct device *dev) { outb(0xaa, dev->path.pnp.port); @@ -63,11 +81,26 @@ const struct pnp_mode_ops pnp_conf_mode_55_aa = { .exit_conf_mode = pnp_exit_conf_mode_aa, }; +const struct pnp_mode_ops pnp_conf_mode_6767_aa = { + .enter_conf_mode = pnp_enter_conf_mode_6767, + .exit_conf_mode = pnp_exit_conf_mode_aa, +}; + +const struct pnp_mode_ops pnp_conf_mode_7777_aa = { + .enter_conf_mode = pnp_enter_conf_mode_7777, + .exit_conf_mode = pnp_exit_conf_mode_aa, +}; + const struct pnp_mode_ops pnp_conf_mode_8787_aa = { .enter_conf_mode = pnp_enter_conf_mode_8787, .exit_conf_mode = pnp_exit_conf_mode_aa, }; +const struct pnp_mode_ops pnp_conf_mode_a0a0_aa = { + .enter_conf_mode = pnp_enter_conf_mode_a0a0, + .exit_conf_mode = pnp_exit_conf_mode_aa, +}; + const struct pnp_mode_ops pnp_conf_mode_870155_aa = { .enter_conf_mode = pnp_enter_conf_mode_870155aa, .exit_conf_mode = pnp_exit_conf_mode_0202,

1 0

New patch to review for coreboot: 90c6f69 x86 romstage.ld: handle the AGESA special case in the linker script
by Patrick Georgi Oct. 31, 2014

Oct. 31, 2014

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7307 -gerrit commit 90c6f69ae987d51cabacdfcbadbde80168103b93 Author: Patrick Georgi <pgeorgi(a)google.com> Date: Sat Nov 1 00:02:50 2014 +0100 x86 romstage.ld: handle the AGESA special case in the linker script Move the .illegal_globals definition lower in the romstage linker script to make some versions of ld happy. Also add a special case for AGESA files (which host a bunch of globals that could be const, but aren't) here, so they're ignored from the start instead of failing the test, then have the Makefile ignore the test result. Change-Id: Ib533b7516135d2d3cab2bfda50d69c132c68e261 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- src/arch/x86/Makefile.inc | 2 +- src/arch/x86/init/romstage.ld | 28 +++++++++++++++------------- 2 files changed, 16 insertions(+), 14 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 7ca3ca4..55266f6 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -217,7 +217,7 @@ endif $(OBJCOPY_romstage) --only-section .illegal_globals $(@) $(objcbfs)/romstage_null.offenders && \ $(NM_romstage) $(objcbfs)/romstage_null.offenders | grep -q ""; if [ $$? -eq 0 ]; then \ echo "Forbidden global variables in romstage:"; \ - $(NM_romstage) $(objcbfs)/romstage_null.offenders; test "$(CONFIG_CPU_AMD_AGESA)" = y; \ + $(NM_romstage) $(objcbfs)/romstage_null.offenders; false; \ else true; fi $(objcbfs)/romstage_xip.debug: $$(romstage-objs) $(objgenerated)/romstage_xip.ld $$(romstage-libs) diff --git a/src/arch/x86/init/romstage.ld b/src/arch/x86/init/romstage.ld index f4a4dde..56b096e 100644 --- a/src/arch/x86/init/romstage.ld +++ b/src/arch/x86/init/romstage.ld @@ -43,19 +43,6 @@ SECTIONS _erom = .; } - /* Global variables are not allowed in romstage - * This section is checked during stage creation to ensure - * that there are no global variables present - */ - .illegal_globals . : { - *(.data) - *(.data.*) - *(.bss) - *(.bss.*) - *(.sbss) - *(.sbss.*) - } - /DISCARD/ : { *(.comment) *(.note) @@ -78,5 +65,20 @@ SECTIONS preram_cbmem_console = .; } + /* Global variables are not allowed in romstage + * This section is checked during stage creation to ensure + * that there are no global variables present + */ + + . = 0xffffff00; + .illegal_globals . : { + *(EXCLUDE_FILE (*/libagesa.*.a: */buildOpts.romstage.o */agesawrapper.romstage.o) .data) + *(.data.*) + *(.bss) + *(.bss.*) + *(.sbss) + *(.sbss.*) + } + _bogus = ASSERT((SIZEOF(.car.data) + CONFIG_CONSOLE_PRERAM_BUFFER_SIZE <= CONFIG_DCACHE_RAM_SIZE), "Cache as RAM area is too full"); }

1 0

Patch set updated for coreboot: 83a07e8 bd82x6x, ibexpeak: consolidate expresscard hotplug
by Vladimir Serbinenko Oct. 31, 2014

Oct. 31, 2014

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7296 -gerrit commit 83a07e8e18a636abe6b09edab25c9fb973117ae6 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Tue Oct 28 23:43:20 2014 +0100 bd82x6x,ibexpeak: consolidate expresscard hotplug Change-Id: I585dec12e17e22d829baa3f2dc7aecc174f9d3b5 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/lenovo/t520/devicetree.cb | 2 ++ src/mainboard/lenovo/t520/dsdt.asl | 1 - src/mainboard/lenovo/t520/mainboard.c | 8 ------- src/mainboard/lenovo/t530/devicetree.cb | 2 ++ src/mainboard/lenovo/t530/dsdt.asl | 1 - src/mainboard/lenovo/t530/mainboard.c | 8 ------- src/mainboard/lenovo/x201/devicetree.cb | 2 ++ src/mainboard/lenovo/x201/dsdt.asl | 1 - src/mainboard/lenovo/x201/mainboard.c | 8 ------- src/mainboard/lenovo/x220/devicetree.cb | 2 ++ src/mainboard/lenovo/x220/dsdt.asl | 1 - src/mainboard/lenovo/x220/mainboard.c | 8 ------- src/mainboard/lenovo/x230/devicetree.cb | 2 ++ src/mainboard/lenovo/x230/dsdt.asl | 1 - src/mainboard/lenovo/x230/mainboard.c | 8 ------- src/southbridge/intel/bd82x6x/acpi/pcie.asl | 21 ------------------ src/southbridge/intel/bd82x6x/chip.h | 2 ++ src/southbridge/intel/bd82x6x/lpc.c | 34 +++++++++++++++++++++++++++++ src/southbridge/intel/bd82x6x/pcie.c | 9 ++++++++ src/southbridge/intel/ibexpeak/lpc.c | 34 +++++++++++++++++++++++++++++ 20 files changed, 89 insertions(+), 66 deletions(-) diff --git a/src/mainboard/lenovo/t520/devicetree.cb b/src/mainboard/lenovo/t520/devicetree.cb index 486e8d2..d2a4d6b 100644 --- a/src/mainboard/lenovo/t520/devicetree.cb +++ b/src/mainboard/lenovo/t520/devicetree.cb @@ -67,6 +67,8 @@ chip northbridge/intel/sandybridge register "c2_latency" = "101" # c2 not supported register "p_cnt_throttling_supported" = "1" + register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }" + device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end device pci 16.2 off end diff --git a/src/mainboard/lenovo/t520/dsdt.asl b/src/mainboard/lenovo/t520/dsdt.asl index b6b4b33..0c84bfb 100644 --- a/src/mainboard/lenovo/t520/dsdt.asl +++ b/src/mainboard/lenovo/t520/dsdt.asl @@ -23,7 +23,6 @@ #define BRIGHTNESS_UP \_SB.PCI0.GFX0.LCD0.INCB #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.LCD0.DECB #define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 -#define RP04_IS_EXPRESSCARD 1 #define EC_LENOVO_H8_ME_WORKAROUND 1 #define HAVE_LCD_SCREEN 1 diff --git a/src/mainboard/lenovo/t520/mainboard.c b/src/mainboard/lenovo/t520/mainboard.c index 387bbe0..582ef81 100644 --- a/src/mainboard/lenovo/t520/mainboard.c +++ b/src/mainboard/lenovo/t520/mainboard.c @@ -53,14 +53,6 @@ static void mainboard_init(device_t dev) RCBA32(0x38c0) = 0x00000007; pc_keyboard_init(); - - /* Enable expresscard hotplug events. */ - pci_write_config32(dev_find_slot(0, PCI_DEVFN(0x1c, 3)), - 0xd8, - pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x1c, 3)), 0xd8) - | (1 << 30)); - pci_write_config16(dev_find_slot(0, PCI_DEVFN(0x1c, 3)), - 0x42, 0x142); } /* mainboard_enable is executed as first thing after diff --git a/src/mainboard/lenovo/t530/devicetree.cb b/src/mainboard/lenovo/t530/devicetree.cb index c1cbca2..c44f927 100644 --- a/src/mainboard/lenovo/t530/devicetree.cb +++ b/src/mainboard/lenovo/t530/devicetree.cb @@ -66,6 +66,8 @@ chip northbridge/intel/sandybridge register "c2_latency" = "101" # c2 not supported register "p_cnt_throttling_supported" = "1" + register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }" + device pci 14.0 on end # USB 3.0 Controller device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 diff --git a/src/mainboard/lenovo/t530/dsdt.asl b/src/mainboard/lenovo/t530/dsdt.asl index c73f795..0c84bfb 100644 --- a/src/mainboard/lenovo/t530/dsdt.asl +++ b/src/mainboard/lenovo/t530/dsdt.asl @@ -23,7 +23,6 @@ #define BRIGHTNESS_UP \_SB.PCI0.GFX0.LCD0.INCB #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.LCD0.DECB #define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 -#define RP03_IS_EXPRESSCARD 1 #define EC_LENOVO_H8_ME_WORKAROUND 1 #define HAVE_LCD_SCREEN 1 diff --git a/src/mainboard/lenovo/t530/mainboard.c b/src/mainboard/lenovo/t530/mainboard.c index f8c9dae..14e1960 100644 --- a/src/mainboard/lenovo/t530/mainboard.c +++ b/src/mainboard/lenovo/t530/mainboard.c @@ -56,14 +56,6 @@ static void mainboard_init(device_t dev) connected to anything and hence we don't init it. */ pc_keyboard_init(); - - /* Enable expresscard hotplug events. */ - pci_write_config32(dev_find_slot(0, PCI_DEVFN(0x1c, 2)), - 0xd8, - pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x1c, 2)), 0xd8) - | (1 << 30)); - pci_write_config16(dev_find_slot(0, PCI_DEVFN(0x1c, 2)), - 0x42, 0x142); } // mainboard_enable is executed as first thing after diff --git a/src/mainboard/lenovo/x201/devicetree.cb b/src/mainboard/lenovo/x201/devicetree.cb index d467e92..117c25c 100644 --- a/src/mainboard/lenovo/x201/devicetree.cb +++ b/src/mainboard/lenovo/x201/devicetree.cb @@ -113,6 +113,8 @@ chip northbridge/intel/nehalem register "c2_latency" = "1" register "docking_supported" = "1" + register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }" + device pci 16.2 on # IDE/SATA subsystemid 0x17aa 0x2161 end diff --git a/src/mainboard/lenovo/x201/dsdt.asl b/src/mainboard/lenovo/x201/dsdt.asl index 62616a8..5265a91 100644 --- a/src/mainboard/lenovo/x201/dsdt.asl +++ b/src/mainboard/lenovo/x201/dsdt.asl @@ -23,7 +23,6 @@ #define BRIGHTNESS_UP \_SB.PCI0.GFX0.LCD0.INCB #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.LCD0.DECB #define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 -#define RP04_IS_EXPRESSCARD 1 #define EC_LENOVO_H8_ME_WORKAROUND 1 #define HAVE_LCD_SCREEN 1 diff --git a/src/mainboard/lenovo/x201/mainboard.c b/src/mainboard/lenovo/x201/mainboard.c index 5b76be2..a58d415 100644 --- a/src/mainboard/lenovo/x201/mainboard.c +++ b/src/mainboard/lenovo/x201/mainboard.c @@ -102,14 +102,6 @@ static void mainboard_init(device_t dev) connected to anything and hence we don't init it. */ pc_keyboard_init(); - - /* Enable expresscard hotplug events. */ - pci_write_config32(dev_find_slot(0, PCI_DEVFN(0x1c, 3)), - 0xd8, - pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x1c, 3)), 0xd8) - | (1 << 30)); - pci_write_config16(dev_find_slot(0, PCI_DEVFN(0x1c, 3)), - 0x42, 0x142); } static void fill_ssdt(void) diff --git a/src/mainboard/lenovo/x220/devicetree.cb b/src/mainboard/lenovo/x220/devicetree.cb index c3b8ad9..982e30b 100644 --- a/src/mainboard/lenovo/x220/devicetree.cb +++ b/src/mainboard/lenovo/x220/devicetree.cb @@ -65,6 +65,8 @@ chip northbridge/intel/sandybridge register "gen2_dec" = "0x0c15e1" register "gen4_dec" = "0x0c06a1" + register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }" + # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "1" diff --git a/src/mainboard/lenovo/x220/dsdt.asl b/src/mainboard/lenovo/x220/dsdt.asl index b6b4b33..0c84bfb 100644 --- a/src/mainboard/lenovo/x220/dsdt.asl +++ b/src/mainboard/lenovo/x220/dsdt.asl @@ -23,7 +23,6 @@ #define BRIGHTNESS_UP \_SB.PCI0.GFX0.LCD0.INCB #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.LCD0.DECB #define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 -#define RP04_IS_EXPRESSCARD 1 #define EC_LENOVO_H8_ME_WORKAROUND 1 #define HAVE_LCD_SCREEN 1 diff --git a/src/mainboard/lenovo/x220/mainboard.c b/src/mainboard/lenovo/x220/mainboard.c index 00e7991..2fdc204 100644 --- a/src/mainboard/lenovo/x220/mainboard.c +++ b/src/mainboard/lenovo/x220/mainboard.c @@ -59,14 +59,6 @@ static void mainboard_init(device_t dev) connected to anything and hence we don't init it. */ pc_keyboard_init(); - - /* Enable expresscard hotplug events. */ - pci_write_config32(dev_find_slot(0, PCI_DEVFN(0x1c, 3)), - 0xd8, - pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x1c, 3)), 0xd8) - | (1 << 30)); - pci_write_config16(dev_find_slot(0, PCI_DEVFN(0x1c, 3)), - 0x42, 0x142); } // mainboard_enable is executed as first thing after diff --git a/src/mainboard/lenovo/x230/devicetree.cb b/src/mainboard/lenovo/x230/devicetree.cb index f2fed1f..5130410 100644 --- a/src/mainboard/lenovo/x230/devicetree.cb +++ b/src/mainboard/lenovo/x230/devicetree.cb @@ -65,6 +65,8 @@ chip northbridge/intel/sandybridge register "gen2_dec" = "0x0c15e1" register "gen4_dec" = "0x0c06a1" + register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }" + # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "1" register "c2_latency" = "101" # c2 not supported diff --git a/src/mainboard/lenovo/x230/dsdt.asl b/src/mainboard/lenovo/x230/dsdt.asl index c73f795..0c84bfb 100644 --- a/src/mainboard/lenovo/x230/dsdt.asl +++ b/src/mainboard/lenovo/x230/dsdt.asl @@ -23,7 +23,6 @@ #define BRIGHTNESS_UP \_SB.PCI0.GFX0.LCD0.INCB #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.LCD0.DECB #define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 -#define RP03_IS_EXPRESSCARD 1 #define EC_LENOVO_H8_ME_WORKAROUND 1 #define HAVE_LCD_SCREEN 1 diff --git a/src/mainboard/lenovo/x230/mainboard.c b/src/mainboard/lenovo/x230/mainboard.c index a060015..da0aa65 100644 --- a/src/mainboard/lenovo/x230/mainboard.c +++ b/src/mainboard/lenovo/x230/mainboard.c @@ -60,14 +60,6 @@ static void mainboard_init(device_t dev) connected to anything and hence we don't init it. */ pc_keyboard_init(); - - /* Enable expresscard hotplug events. */ - pci_write_config32(dev_find_slot(0, PCI_DEVFN(0x1c, 2)), - 0xd8, - pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x1c, 2)), 0xd8) - | (1 << 30)); - pci_write_config16(dev_find_slot(0, PCI_DEVFN(0x1c, 2)), - 0x42, 0x142); } // mainboard_enable is executed as first thing after diff --git a/src/southbridge/intel/bd82x6x/acpi/pcie.asl b/src/southbridge/intel/bd82x6x/acpi/pcie.asl index 14ae449..934cf78 100644 --- a/src/southbridge/intel/bd82x6x/acpi/pcie.asl +++ b/src/southbridge/intel/bd82x6x/acpi/pcie.asl @@ -155,16 +155,6 @@ Device (RP03) { Return (IRQM (RPPN)) } -#ifdef RP03_IS_EXPRESSCARD - Device (SLOT) - { - Name (_ADR, 0x00) - Method (_RMV, 0, NotSerialized) - { - Return (0x01) - } - } -#endif } Device (RP04) @@ -177,17 +167,6 @@ Device (RP04) { Return (IRQM (RPPN)) } - -#ifdef RP04_IS_EXPRESSCARD - Device (SLOT) - { - Name (_ADR, 0x00) - Method (_RMV, 0, NotSerialized) - { - Return (0x01) - } - } -#endif } Device (RP05) diff --git a/src/southbridge/intel/bd82x6x/chip.h b/src/southbridge/intel/bd82x6x/chip.h index 1256129..290bb05 100644 --- a/src/southbridge/intel/bd82x6x/chip.h +++ b/src/southbridge/intel/bd82x6x/chip.h @@ -87,6 +87,8 @@ struct southbridge_intel_bd82x6x_config { int p_cnt_throttling_supported; int c2_latency; int docking_supported; + + uint8_t pcie_hotplug_map[8]; }; #endif /* SOUTHBRIDGE_INTEL_BD82X6X_CHIP_H */ diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 20f20ae..62b7096 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -839,6 +839,39 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->x_gpe1_blk.addrh = 0x0; } +static void southbridge_fill_ssdt(void) +{ + device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0)); + config_t *chip = dev->chip_info; + char scope_name[] = "\\_SB.PCI0.RP0x"; + int port; + + for (port = 0; port < 8; port++) { + if (chip->pcie_hotplug_map[port]) { + int scopelen; + scope_name[sizeof("\\_SB.PCI0.RP0x") - 2] = '1' + port; + scopelen = acpigen_write_scope(scope_name); + + /* + Device (SLOT) + { + Name (_ADR, 0x00) + Method (_RMV, 0, NotSerialized) + { + Return (0x01) + } + } + */ + static char stream[] = { + 0x5b, 0x82, 0x14, 0x53, 0x4c, 0x4f, 0x54, 0x08, 0x5f, 0x41, 0x44, + 0x52, 0x00, 0x14, 0x08, 0x5f, 0x52, 0x4d, 0x56, 0x00, 0xa4, 0x01 + }; + scopelen += acpigen_emit_stream(stream, ARRAY_SIZE(stream)); + acpigen_patch_len(scopelen - 1); + } + } +} + static struct pci_operations pci_ops = { .set_subsystem = set_subsystem, }; @@ -849,6 +882,7 @@ static struct device_operations device_ops = { .enable_resources = pch_lpc_enable_resources, .write_acpi_tables = acpi_write_hpet, .acpi_inject_dsdt_generator = southbridge_inject_dsdt, + .acpi_fill_ssdt_generator = southbridge_fill_ssdt, .init = lpc_init, .enable = pch_lpc_enable, .scan_bus = scan_static_bus, diff --git a/src/southbridge/intel/bd82x6x/pcie.c b/src/southbridge/intel/bd82x6x/pcie.c index fadb43f..c698b12 100644 --- a/src/southbridge/intel/bd82x6x/pcie.c +++ b/src/southbridge/intel/bd82x6x/pcie.c @@ -218,6 +218,7 @@ static void pci_init(struct device *dev) { u16 reg16; u32 reg32; + struct southbridge_intel_bd82x6x_config *config = dev->chip_info; printk(BIOS_DEBUG, "Initializing PCH PCIe bridge.\n"); @@ -255,6 +256,14 @@ static void pci_init(struct device *dev) reg16 = pci_read_config16(dev, 0x1e); //reg16 |= 0xf900; pci_write_config16(dev, 0x1e, reg16); + + /* Enable expresscard hotplug events. */ + if (config->pcie_hotplug_map[PCI_FUNC(dev->path.pci.devfn)]) { + pci_write_config32(dev, 0xd8, + pci_read_config32(dev, 0xd8) + | (1 << 30)); + pci_write_config16(dev, 0x42, 0x142); + } } static void pch_pcie_enable(device_t dev) diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index da609da..c7a2427 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -822,6 +822,39 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->x_gpe1_blk.addrh = 0x0; } +static void southbridge_fill_ssdt(void) +{ + device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0)); + config_t *chip = dev->chip_info; + char scope_name[] = "\\_SB.PCI0.RP0x"; + int port; + + for (port = 0; port < 8; port++) { + if (chip->pcie_hotplug_map[port]) { + int scopelen; + scope_name[sizeof("\\_SB.PCI0.RP0x") - 2] = '1' + port; + scopelen = acpigen_write_scope(scope_name); + + /* + Device (SLOT) + { + Name (_ADR, 0x00) + Method (_RMV, 0, NotSerialized) + { + Return (0x01) + } + } + */ + static char stream[] = { + 0x5b, 0x82, 0x14, 0x53, 0x4c, 0x4f, 0x54, 0x08, 0x5f, 0x41, 0x44, + 0x52, 0x00, 0x14, 0x08, 0x5f, 0x52, 0x4d, 0x56, 0x00, 0xa4, 0x01 + }; + scopelen += acpigen_emit_stream(stream, ARRAY_SIZE(stream)); + acpigen_patch_len(scopelen - 1); + } + } +} + static struct pci_operations pci_ops = { .set_subsystem = set_subsystem, }; @@ -831,6 +864,7 @@ static struct device_operations device_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pch_lpc_enable_resources, .acpi_inject_dsdt_generator = southbridge_inject_dsdt, + .acpi_fill_ssdt_generator = southbridge_fill_ssdt, .write_acpi_tables = acpi_write_hpet, .init = lpc_init, .enable = pch_lpc_enable,

1 0

New patch to review for coreboot: 33ae80d x86: Update the check for Forbidden global variables
by Furquan Shaikh Oct. 31, 2014

Oct. 31, 2014

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7306 -gerrit commit 33ae80d7ec76f1f4dfda5297ea00804baebffea1 Author: Furquan Shaikh <furquan(a)google.com> Date: Thu Oct 30 11:53:38 2014 -0700 x86: Update the check for Forbidden global variables Add a section .illegal_globals to romstage and check that the section does not contain any variables while creating romstage. Change-Id: I866681f51a44bc21770d32995c281b556a90c153 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- src/arch/x86/Makefile.inc | 5 +++-- src/arch/x86/init/romstage.ld | 13 +++++++++++++ 2 files changed, 16 insertions(+), 2 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index f99ea15..7ca3ca4 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -214,9 +214,10 @@ ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) else $(CC_romstage) $(CFLAGS_romstage) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(objgenerated)/romstage_null.ld -Wl,--wrap,__divdi3 -Wl,--wrap,__udivdi3 -Wl,--wrap,__moddi3 -Wl,--wrap,__umoddi3 -Wl,--start-group $(romstage-objs) $(romstage-libs) $(LIBGCC_FILE_NAME_romstage) -Wl,--end-group endif - $(NM_romstage) $@ | grep -q " [DdBb] "; if [ $$? -eq 0 ]; then \ + $(OBJCOPY_romstage) --only-section .illegal_globals $(@) $(objcbfs)/romstage_null.offenders && \ + $(NM_romstage) $(objcbfs)/romstage_null.offenders | grep -q ""; if [ $$? -eq 0 ]; then \ echo "Forbidden global variables in romstage:"; \ - $(NM_romstage) $@ | grep " [DdBb] "; test "$(CONFIG_CPU_AMD_AGESA)" = y; \ + $(NM_romstage) $(objcbfs)/romstage_null.offenders; test "$(CONFIG_CPU_AMD_AGESA)" = y; \ else true; fi $(objcbfs)/romstage_xip.debug: $$(romstage-objs) $(objgenerated)/romstage_xip.ld $$(romstage-libs) diff --git a/src/arch/x86/init/romstage.ld b/src/arch/x86/init/romstage.ld index d6eb511..f4a4dde 100644 --- a/src/arch/x86/init/romstage.ld +++ b/src/arch/x86/init/romstage.ld @@ -43,6 +43,19 @@ SECTIONS _erom = .; } + /* Global variables are not allowed in romstage + * This section is checked during stage creation to ensure + * that there are no global variables present + */ + .illegal_globals . : { + *(.data) + *(.data.*) + *(.bss) + *(.bss.*) + *(.sbss) + *(.sbss.*) + } + /DISCARD/ : { *(.comment) *(.note)

1 0

New patch to review for coreboot: 4943e76 romstage: Pass .car.data as ignored section while adding romstage
by Furquan Shaikh Oct. 31, 2014

Oct. 31, 2014

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7305 -gerrit commit 4943e7626437d06f01006fbf697ab08e0ff452a7 Author: Furquan Shaikh <furquan(a)google.com> Date: Thu Oct 30 11:47:20 2014 -0700 romstage: Pass .car.data as ignored section while adding romstage We don't want segment for .car.data section to be considered while elf_to_stage transformation is being done. Thus, use -S option for add-stage. Change-Id: I04868c892e3aa94113189b012d284d52bacea5f0 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- src/arch/x86/Makefile.inc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 50f5ada..f99ea15 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -53,7 +53,8 @@ mbi.bin-type := mbi ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32),y) CBFSTOOL_PRE1_OPTS = -m x86 -o $$(( $(CONFIG_ROM_SIZE) - $(CONFIG_CBFS_SIZE) )) -CBFSTOOL_PRE_OPTS = -b $(shell cat $(objcbfs)/base_xip.txt) +# Make sure that segment for .car.data is ignored while adding romstage. +CBFSTOOL_PRE_OPTS = -b $(shell cat $(objcbfs)/base_xip.txt) -S ".car.data" endif ################################################################################

1 0

New patch to review for coreboot: 05635ca cbfstool: Add option to ignore section in add-stage
by Furquan Shaikh Oct. 31, 2014

Oct. 31, 2014

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7304 -gerrit commit 05635ca4b0cc47375a925aec98fe244ef02d7719 Author: Furquan Shaikh <furquan(a)google.com> Date: Thu Oct 30 11:44:20 2014 -0700 cbfstool: Add option to ignore section in add-stage Allow add-stage to have an optional parameter for ignoring any section. This is required to ensure proper operation of elf_to_stage in case of loadable segments with zero filesize. Change-Id: I49ad62c2a4260ab9cec173c80c0f16923fc66c79 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- util/cbfstool/cbfs-mkstage.c | 77 +++++++++++++++++++++++++++++++++++++++++++- util/cbfstool/cbfstool.c | 12 +++++-- util/cbfstool/common.h | 3 +- 3 files changed, 87 insertions(+), 5 deletions(-) diff --git a/util/cbfstool/cbfs-mkstage.c b/util/cbfstool/cbfs-mkstage.c index 3da0836..8459334 100644 --- a/util/cbfstool/cbfs-mkstage.c +++ b/util/cbfstool/cbfs-mkstage.c @@ -28,16 +28,79 @@ #include "common.h" #include "cbfs.h" +/* Checks if program segment contains the ignored section */ +static int is_phdr_ignored(Elf64_Phdr *phdr, Elf64_Shdr *shdr) +{ + /* If no ignored section, return false. */ + if (shdr == NULL) + return 0; + + Elf64_Addr sh_start = shdr->sh_addr; + Elf64_Addr sh_end = shdr->sh_addr + shdr->sh_size; + Elf64_Addr ph_start = phdr->p_vaddr; + Elf64_Addr ph_end = phdr->p_vaddr + phdr->p_memsz; + + /* Return true only if section occupies whole of segment. */ + if ((sh_start == ph_start) && (sh_end == ph_end)) { + DEBUG("Ignoring program segment at %p\n", (void *)ph_start); + return 1; + } + + /* If shdr intersects phdr at all, its a conflict */ + if (((sh_start >= ph_start) && (sh_start <= ph_end)) || + ((sh_end >= ph_start) && (sh_end <= ph_end))) { + ERROR("Conflicting sections in segment\n"); + exit(1); + } + + /* Program header doesn't need to be ignored. */ + return 0; +} + +/* Find section header based on ignored section name */ +static Elf64_Shdr *find_ignored_section_header(struct parsed_elf *pelf, + const char *ignore_section) +{ + int i; + const char *shstrtab; + + /* No section needs to be ignored */ + if (ignore_section == NULL) + return NULL; + + DEBUG("Section to be ignored: %s\n", ignore_section); + + /* Get pointer to string table */ + shstrtab = buffer_get(pelf->strtabs[pelf->ehdr.e_shstrndx]); + + for (i = 0; i < pelf->ehdr.e_shnum; i++) { + Elf64_Shdr *shdr; + const char *section_name; + + shdr = &pelf->shdr[i]; + section_name = &shstrtab[shdr->sh_name]; + + /* If section name matches ignored string, return shdr */ + if (strcmp(section_name, ignore_section) == 0) + return shdr; + } + + /* No section matches ignore string */ + return NULL; +} + /* returns size of result, or -1 if error. * Note that, with the new code, this function * works for all elf files, not just the restricted set. */ int parse_elf_to_stage(const struct buffer *input, struct buffer *output, - uint32_t arch, comp_algo algo, uint32_t *location) + uint32_t arch, comp_algo algo, uint32_t *location, + const char *ignore_section) { struct parsed_elf pelf; Elf64_Phdr *phdr; Elf64_Ehdr *ehdr; + Elf64_Shdr *shdr_ignored; char *buffer; struct buffer outheader; int ret = -1; @@ -62,8 +125,20 @@ int parse_elf_to_stage(const struct buffer *input, struct buffer *output, ehdr = &pelf.ehdr; phdr = &pelf.phdr[0]; + /* Find the section header corresponding to ignored-section */ + shdr_ignored = find_ignored_section_header(&pelf, ignore_section); + + if (ignore_section && (shdr_ignored == NULL)) + WARN("Ignore section not found\n"); + headers = ehdr->e_phnum; + /* Ignore the program header containing ignored section */ + for (i = 0; i < headers; i++) { + if (is_phdr_ignored(&phdr[i], shdr_ignored)) + phdr[i].p_type = PT_NULL; + } + data_start = ~0; data_end = 0; mem_end = 0; diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c index ca02ca6..66c425b 100644 --- a/util/cbfstool/cbfstool.c +++ b/util/cbfstool/cbfstool.c @@ -41,6 +41,7 @@ static struct param { char *name; char *filename; char *bootblock; + char *ignore_section; uint64_t u64val; uint32_t type; uint32_t baseaddress; @@ -184,7 +185,7 @@ static int cbfstool_convert_mkstage(struct buffer *buffer, uint32_t *offset) struct buffer output; int ret; ret = parse_elf_to_stage(buffer, &output, param.arch, param.algo, - offset); + offset, param.ignore_section); if (ret != 0) return -1; buffer_delete(buffer); @@ -516,7 +517,7 @@ static int cbfs_update_fit(void) static const struct command commands[] = { {"add", "f:n:t:b:vh?", cbfs_add}, {"add-payload", "f:n:t:c:b:vh?C:I:", cbfs_add_payload}, - {"add-stage", "f:n:t:c:b:vh?", cbfs_add_stage}, + {"add-stage", "f:n:t:c:b:S:vh?", cbfs_add_stage}, {"add-flat-binary", "f:n:l:e:c:b:vh?", cbfs_add_flat_binary}, {"add-int", "i:n:b:vh?", cbfs_add_integer}, {"remove", "n:vh?", cbfs_remove}, @@ -546,6 +547,7 @@ static struct option long_options[] = { {"empty-fits", required_argument, 0, 'x' }, {"initrd", required_argument, 0, 'I' }, {"cmdline", required_argument, 0, 'C' }, + {"ignore-sec", required_argument, 0, 'S' }, {"verbose", no_argument, 0, 'v' }, {"help", no_argument, 0, 'h' }, {NULL, 0, 0, 0 } @@ -566,7 +568,8 @@ static void usage(char *name) " add-payload -f FILE -n NAME [-c compression] [-b base] " "Add a payload to the ROM\n" " (linux specific: [-C cmdline] [-I initrd])\n" - " add-stage -f FILE -n NAME [-c compression] [-b base] " + " add-stage -f FILE -n NAME [-c compression] [-b base] \\\n" + " [-S section-to-ignore] " "Add a stage to the ROM\n" " add-flat-binary -f FILE -n NAME -l load-address \\\n" " -e entry-point [-c compression] [-b base] " @@ -714,6 +717,9 @@ int main(int argc, char **argv) case 'C': param.cmdline = optarg; break; + case 'S': + param.ignore_section = optarg; + break; case 'h': case '?': usage(argv[0]); diff --git a/util/cbfstool/common.h b/util/cbfstool/common.h index 02a088b..41659a2 100644 --- a/util/cbfstool/common.h +++ b/util/cbfstool/common.h @@ -139,7 +139,8 @@ int parse_flat_binary_to_payload(const struct buffer *input, comp_algo algo); /* cbfs-mkstage.c */ int parse_elf_to_stage(const struct buffer *input, struct buffer *output, - uint32_t arch, comp_algo algo, uint32_t *location); + uint32_t arch, comp_algo algo, uint32_t *location, + const char *ignore_section); void print_supported_filetypes(void);

1 0

New patch to review for coreboot: df2b6ae cbfstool: Convert cbfs-mkstage.c into pelf
by Furquan Shaikh Oct. 31, 2014

Oct. 31, 2014

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7303 -gerrit commit df2b6ae446bce1c46b66aef3ea94b9c2b3027178 Author: Furquan Shaikh <furquan(a)google.com> Date: Thu Oct 30 11:28:27 2014 -0700 cbfstool: Convert cbfs-mkstage.c into pelf Change cbfs-mkstage to use parsed elf instead of calling elf_headers. That allows us to have access to the complete elf including the string table. Change-Id: Ie767d28bdf41af38d1df0bce54bc0ada45123136 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- util/cbfstool/cbfs-mkstage.c | 29 +++++++++++++++++++++-------- 1 file changed, 21 insertions(+), 8 deletions(-) diff --git a/util/cbfstool/cbfs-mkstage.c b/util/cbfstool/cbfs-mkstage.c index 4a2f4d8..3da0836 100644 --- a/util/cbfstool/cbfs-mkstage.c +++ b/util/cbfstool/cbfs-mkstage.c @@ -35,10 +35,12 @@ int parse_elf_to_stage(const struct buffer *input, struct buffer *output, uint32_t arch, comp_algo algo, uint32_t *location) { + struct parsed_elf pelf; Elf64_Phdr *phdr; - Elf64_Ehdr ehdr; + Elf64_Ehdr *ehdr; char *buffer; struct buffer outheader; + int ret = -1; int headers; int i, outlen; @@ -50,10 +52,17 @@ int parse_elf_to_stage(const struct buffer *input, struct buffer *output, DEBUG("start: parse_elf_to_stage(location=0x%x)\n", *location); - if (elf_headers(input, arch, &ehdr, &phdr, NULL) < 0) + int flags = ELF_PARSE_PHDR | ELF_PARSE_SHDR | ELF_PARSE_STRTAB; + + if (parse_elf(input, &pelf, flags)) { + ERROR("Couldn't parse ELF\n"); return -1; + } + + ehdr = &pelf.ehdr; + phdr = &pelf.phdr[0]; - headers = ehdr.e_phnum; + headers = ehdr->e_phnum; data_start = ~0; data_end = 0; @@ -102,7 +111,7 @@ int parse_elf_to_stage(const struct buffer *input, struct buffer *output, if (buffer == NULL) { ERROR("Unable to allocate memory: %m\n"); - return -1; + goto err; } /* Copy the file data into the buffer */ @@ -135,7 +144,7 @@ int parse_elf_to_stage(const struct buffer *input, struct buffer *output, "File has %zu bytes left, segment end is %zu\n", input->size, (size_t)(phdr[i].p_offset + phdr[i].p_filesz)); free(buffer); - return -1; + goto err; } memcpy(buffer + (l_start - data_start), &input->data[phdr[i].p_offset + l_offset], @@ -147,7 +156,7 @@ int parse_elf_to_stage(const struct buffer *input, struct buffer *output, input->name) != 0) { ERROR("Unable to allocate memory: %m\n"); free(buffer); - return -1; + goto err; } memset(output->data, 0, output->size); @@ -177,7 +186,7 @@ int parse_elf_to_stage(const struct buffer *input, struct buffer *output, * Maybe we should just change the spec. */ xdr_le.put32(&outheader, algo); - xdr_le.put64(&outheader, ehdr.e_entry); + xdr_le.put64(&outheader, ehdr->e_entry); xdr_le.put64(&outheader, data_start); xdr_le.put32(&outheader, outlen); xdr_le.put32(&outheader, mem_end - data_start); @@ -185,5 +194,9 @@ int parse_elf_to_stage(const struct buffer *input, struct buffer *output, if (*location) *location -= sizeof(struct cbfs_stage); output->size = sizeof(struct cbfs_stage) + outlen; - return 0; + ret = 0; + +err: + parsed_elf_destroy(&pelf); + return ret; }

1 0

Patch set updated for coreboot: 410f054 Redundant addr '&' operator on func ptr's in struct initiator
by Edward O'Callaghan Oct. 31, 2014

Oct. 31, 2014

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7290 -gerrit commit 410f054ad2c295a34becafc21f00acb0b52fa9d3 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Fri Oct 31 08:54:41 2014 +1100 Redundant addr '&' operator on func ptr's in struct initiator Bring code inline to be consistent with the rest of coreboot. See standard - c99std (n1256) 6.3.2.1p4 - to paraphrase, 'expressions that refer to functions get converted to pointers to those functions' Change-Id: I63a7bed5efade37dd7076dbfc9c85d420cf6c92b Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/northbridge/via/cx700/lpc.c | 4 ++-- src/soc/intel/broadwell/systemagent.c | 12 ++++++------ 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/src/northbridge/via/cx700/lpc.c b/src/northbridge/via/cx700/lpc.c index da3e2ce..1e6d2ce 100644 --- a/src/northbridge/via/cx700/lpc.c +++ b/src/northbridge/via/cx700/lpc.c @@ -296,12 +296,12 @@ static struct device_operations cx700_lpc_ops = { .read_resources = cx700_read_resources, .set_resources = cx700_set_resources, .enable_resources = cx700_enable_resources, - .init = &cx700_lpc_init, + .init = cx700_lpc_init, .scan_bus = scan_static_bus, }; static const struct pci_driver lpc_driver __pci_driver = { - .ops = &cx700_lpc_ops, + .ops = &cx700_lpc_ops, .vendor = PCI_VENDOR_ID_VIA, .device = 0x8324, }; diff --git a/src/soc/intel/broadwell/systemagent.c b/src/soc/intel/broadwell/systemagent.c index 787a62b..2b3ce41 100644 --- a/src/soc/intel/broadwell/systemagent.c +++ b/src/soc/intel/broadwell/systemagent.c @@ -433,12 +433,12 @@ static void systemagent_enable(device_t dev) } static struct device_operations systemagent_ops = { - .read_resources = &systemagent_read_resources, - .set_resources = &pci_dev_set_resources, - .enable_resources = &pci_dev_enable_resources, - .init = &systemagent_init, - .enable = &systemagent_enable, - .ops_pci = &broadwell_pci_ops, + .read_resources = systemagent_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = systemagent_init, + .enable = systemagent_enable, + .ops_pci = broadwell_pci_ops, }; static const unsigned short systemagent_ids[] = {

1 0

New patch to review for coreboot: 4abe982 amd/agesa/f16kb: Invalid inline asm in gcc-intrin.h
by Edward O'Callaghan Oct. 31, 2014

Oct. 31, 2014

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7302 -gerrit commit 4abe982f7139570b54f021f4a7bd97267ffe0b1e Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Nov 1 05:36:34 2014 +1100 amd/agesa/f16kb: Invalid inline asm in gcc-intrin.h Forward port commit: db0e0e2 amd/agesa/*/gcc-intrin.h: Invaild inline asm Change-Id: Ia857f76d3782aea07e09df1352eeb286e40b2689 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- .../amd/agesa/f16kb/Include/gcc-intrin.h | 197 ++++++++++++--------- 1 file changed, 112 insertions(+), 85 deletions(-) diff --git a/src/vendorcode/amd/agesa/f16kb/Include/gcc-intrin.h b/src/vendorcode/amd/agesa/f16kb/Include/gcc-intrin.h index ea80746..7d90f8b 100644 --- a/src/vendorcode/amd/agesa/f16kb/Include/gcc-intrin.h +++ b/src/vendorcode/amd/agesa/f16kb/Include/gcc-intrin.h @@ -1,6 +1,6 @@ /* - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. + * Copyright (c) 2011, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2014, Edward O'Callaghan <eocallaghan(a)alterapraxis.com> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -34,9 +34,9 @@ static __inline__ __attribute__((always_inline)) unsigned char __inbyte(unsigned unsigned char value; __asm__ __volatile__ ( - "in %%dx, %%al" + "in %1, %0" : "=a" (value) - : "d" (Port) + : "Nd" (Port) ); return value; @@ -47,9 +47,9 @@ static __inline__ __attribute__((always_inline)) unsigned short __inword(unsigne unsigned short value; __asm__ __volatile__ ( - "in %%dx, %%ax" + "in %1, %0" : "=a" (value) - : "d" (Port) + : "Nd" (Port) ); return value; @@ -60,9 +60,9 @@ static __inline__ __attribute__((always_inline)) unsigned long __indword(unsigne unsigned long value; __asm__ __volatile__ ( - "in %%dx, %%eax" + "in %1, %0" : "=a" (value) - : "d" (Port) + : "Nd" (Port) ); return value; @@ -71,81 +71,81 @@ static __inline__ __attribute__((always_inline)) unsigned long __indword(unsigne static __inline__ __attribute__((always_inline)) void __outbyte(unsigned short Port,unsigned char Data) { __asm__ __volatile__ ( - "out %%al, %%dx" + "out %0, %1" : - : "a" (Data), "d" (Port) + : "a" (Data), "Nd" (Port) ); } static __inline__ __attribute__((always_inline)) void __outword(unsigned short Port,unsigned short Data) { __asm__ __volatile__ ( - "out %%ax, %%dx" + "out %0, %1" : - : "a" (Data), "d" (Port) + : "a" (Data), "Nd" (Port) ); } static __inline__ __attribute__((always_inline)) void __outdword(unsigned short Port,unsigned long Data) { __asm__ __volatile__ ( - "out %%eax, %%dx" + "out %0, %1" : - : "a" (Data), "d" (Port) + : "a" (Data), "Nd" (Port) ); } static __inline__ __attribute__((always_inline)) void __inbytestring(unsigned short Port,unsigned char *Buffer,unsigned long Count) { __asm__ __volatile__ ( - "cld ; rep ; insb " - : "=D" (Buffer), "=c" (Count) - : "d"(Port), "0"(Buffer), "1" (Count) + "rep ; insb" + : "+D" (Buffer), "+c" (Count) + : "d"(Port) ); } static __inline__ __attribute__((always_inline)) void __inwordstring(unsigned short Port,unsigned short *Buffer,unsigned long Count) { __asm__ __volatile__ ( - "cld ; rep ; insw " - : "=D" (Buffer), "=c" (Count) - : "d"(Port), "0"(Buffer), "1" (Count) + "rep ; insw" + : "+D" (Buffer), "+c" (Count) + : "d"(Port) ); } static __inline__ __attribute__((always_inline)) void __indwordstring(unsigned short Port,unsigned long *Buffer,unsigned long Count) { __asm__ __volatile__ ( - "cld ; rep ; insl " - : "=D" (Buffer), "=c" (Count) - : "d"(Port), "0"(Buffer), "1" (Count) + "rep ; insl" + : "+D" (Buffer), "+c" (Count) + : "d"(Port) ); } static __inline__ __attribute__((always_inline)) void __outbytestring(unsigned short Port,unsigned char *Buffer,unsigned long Count) { __asm__ __volatile__ ( - "cld ; rep ; outsb " - : "=S" (Buffer), "=c" (Count) - : "d"(Port), "0"(Buffer), "1" (Count) + "rep ; outsb" + : "+S" (Buffer), "+c" (Count) + : "d"(Port) ); } static __inline__ __attribute__((always_inline)) void __outwordstring(unsigned short Port,unsigned short *Buffer,unsigned long Count) { __asm__ __volatile__ ( - "cld ; rep ; outsw " - : "=S" (Buffer), "=c" (Count) - : "d"(Port), "0"(Buffer), "1" (Count) + "rep ; outsw" + : "+S" (Buffer), "+c" (Count) + : "d"(Port) ); } static __inline__ __attribute__((always_inline)) void __outdwordstring(unsigned short Port,unsigned long *Buffer,unsigned long Count) { __asm__ __volatile__ ( - "cld ; rep ; outsl " - : "=S" (Buffer), "=c" (Count) - : "d"(Port), "0"(Buffer), "1" (Count) + "rep ; outsl" + : "+S" (Buffer), "+c" (Count) + : "d"(Port) ); } @@ -154,7 +154,7 @@ static __inline__ __attribute__((always_inline)) unsigned long __readdr0(void) unsigned long value; __asm__ __volatile__ ( "mov %%dr0, %[value]" - : [value] "=a" (value) + : [value] "=r" (value) ); return value; } @@ -164,7 +164,7 @@ static __inline__ __attribute__((always_inline)) unsigned long __readdr1(void) unsigned long value; __asm__ __volatile__ ( "mov %%dr1, %[value]" - : [value] "=a" (value) + : [value] "=r" (value) ); return value; } @@ -174,7 +174,7 @@ static __inline__ __attribute__((always_inline)) unsigned long __readdr2(void) unsigned long value; __asm__ __volatile__ ( "mov %%dr2, %[value]" - : [value] "=a" (value) + : [value] "=r" (value) ); return value; } @@ -184,7 +184,7 @@ static __inline__ __attribute__((always_inline)) unsigned long __readdr3(void) unsigned long value; __asm__ __volatile__ ( "mov %%dr3, %[value]" - : [value] "=a" (value) + : [value] "=r" (value) ); return value; } @@ -194,7 +194,7 @@ static __inline__ __attribute__((always_inline)) unsigned long __readdr7(void) unsigned long value; __asm__ __volatile__ ( "mov %%dr7, %[value]" - : [value] "=a" (value) + : [value] "=r" (value) ); return value; } @@ -230,45 +230,45 @@ static __inline__ __attribute__((always_inline)) unsigned long __readdr(unsigned static __inline__ __attribute__((always_inline)) void __writedr0(unsigned long Data) { __asm__ __volatile__ ( - "mov %%eax, %%dr0" + "mov %0, %%dr0" : - : "a" (Data) + : "r" (Data) ); } static __inline__ __attribute__((always_inline)) void __writedr1(unsigned long Data) { __asm__ __volatile__ ( - "mov %%eax, %%dr1" + "mov %0, %%dr1" : - : "a" (Data) + : "r" (Data) ); } static __inline__ __attribute__((always_inline)) void __writedr2(unsigned long Data) { __asm__ __volatile__ ( - "mov %%eax, %%dr2" + "mov %0, %%dr2" : - : "a" (Data) + : "r" (Data) ); } static __inline__ __attribute__((always_inline)) void __writedr3(unsigned long Data) { __asm__ __volatile__ ( - "mov %%eax, %%dr3" + "mov %0, %%dr3" : - : "a" (Data) + : "r" (Data) ); } static __inline__ __attribute__((always_inline)) void __writedr7(unsigned long Data) { __asm__ __volatile__ ( - "mov %%eax, %%dr7" + "mov %0, %%dr7" : - : "a" (Data) + : "r" (Data) ); } @@ -305,7 +305,7 @@ static __inline__ __attribute__((always_inline)) unsigned long __readcr0(void) unsigned long value; __asm__ __volatile__ ( "mov %%cr0, %[value]" - : [value] "=a" (value)); + : [value] "=r" (value)); return value; } @@ -314,7 +314,7 @@ static __inline__ __attribute__((always_inline)) unsigned long __readcr2(void) unsigned long value; __asm__ __volatile__ ( "mov %%cr2, %[value]" - : [value] "=a" (value)); + : [value] "=r" (value)); return value; } @@ -323,7 +323,7 @@ static __inline__ __attribute__((always_inline)) unsigned long __readcr3(void) unsigned long value; __asm__ __volatile__ ( "mov %%cr3, %[value]" - : [value] "=a" (value)); + : [value] "=r" (value)); return value; } @@ -332,7 +332,7 @@ static __inline__ __attribute__((always_inline)) unsigned long __readcr4(void) unsigned long value; __asm__ __volatile__ ( "mov %%cr4, %[value]" - : [value] "=a" (value)); + : [value] "=r" (value)); return value; } @@ -341,7 +341,7 @@ static __inline__ __attribute__((always_inline)) unsigned long __readcr8(void) unsigned long value; __asm__ __volatile__ ( "mov %%cr8, %[value]" - : [value] "=a" (value)); + : [value] "=r" (value)); return value; } @@ -376,45 +376,46 @@ static __inline__ __attribute__((always_inline)) unsigned long __readcr(unsigned static __inline__ __attribute__((always_inline)) void __writecr0(unsigned long Data) { __asm__ __volatile__ ( - "mov %%eax, %%cr0" + "mov %0, %%cr0" : - : "a" (Data) + : "r" (Data) + : "memory" ); } static __inline__ __attribute__((always_inline)) void __writecr2(unsigned long Data) { __asm__ __volatile__ ( - "mov %%eax, %%cr2" + "mov %0, %%cr2" : - : "a" (Data) + : "r" (Data) ); } static __inline__ __attribute__((always_inline)) void __writecr3(unsigned long Data) { __asm__ __volatile__ ( - "mov %%eax, %%cr3" + "mov %0, %%cr3" : - : "a" (Data) + : "r" (Data) ); } static __inline__ __attribute__((always_inline)) void __writecr4(unsigned long Data) { __asm__ __volatile__ ( - "mov %%eax, %%cr4" + "mov %0, %%cr4" : - : "a" (Data) + : "r" (Data) ); } static __inline__ __attribute__((always_inline)) void __writecr8(unsigned long Data) { __asm__ __volatile__ ( - "mov %%eax, %%cr8" + "mov %0, %%cr8" : - : "a" (Data) + : "r" (Data) ); } @@ -450,7 +451,7 @@ static __inline__ __attribute__((always_inline)) UINT64 __readmsr(UINT32 msr) { UINT64 retval; __asm__ __volatile__( - "rdmsr\n\t" + "rdmsr" : "=A" (retval) : "c" (msr) ); @@ -460,7 +461,7 @@ static __inline__ __attribute__((always_inline)) UINT64 __readmsr(UINT32 msr) static __inline__ __attribute__((always_inline)) void __writemsr (UINT32 msr, UINT64 Value) { __asm__ __volatile__ ( - "wrmsr\n\t" + "wrmsr" : : "c" (msr), "A" (Value) ); @@ -484,26 +485,35 @@ static __inline__ __attribute__((always_inline)) void __cpuid(int CPUInfo[], con ); } + static __inline__ __attribute__((always_inline)) void _disable(void) { __asm__ __volatile__ ("cli"); } + static __inline__ __attribute__((always_inline)) void _enable(void) { __asm__ __volatile__ ("sti"); } + static __inline__ __attribute__((always_inline)) void __halt(void) { __asm__ __volatile__ ("hlt"); } + static __inline__ __attribute__((always_inline)) void __debugbreak(void) { __asm__ __volatile__ ("int3"); } +static __inline__ __attribute__((always_inline)) void __invd(void) +{ + __asm__ __volatile__ ("invd"); +} + static __inline__ __attribute__((always_inline)) void __wbinvd(void) { __asm__ __volatile__ ("wbinvd"); @@ -514,39 +524,57 @@ static __inline__ __attribute__((always_inline)) void __lidt(void *Source) __asm__ __volatile__("lidt %0" : : "m"(*(short*)Source)); } -static __inline__ __attribute__((always_inline)) void __writefsbyte(const unsigned long Offset, const unsigned char Data) +static __inline__ __attribute__((always_inline)) void +__writefsbyte(const unsigned long Offset, const unsigned char Data) { - __asm__("movb %b[Data], %%fs:%a[Offset]" : : [Offset] "ir" (Offset), [Data] "iq" (Data)); + __asm__ ("movb %[Data], %%fs:%a[Offset]" + : + : [Offset] "ir" (Offset), [Data] "iq" (Data)); } -static __inline__ __attribute__((always_inline)) void __writefsword(const unsigned long Offset, const unsigned short Data) +static __inline__ __attribute__((always_inline)) void +__writefsword(const unsigned long Offset, const unsigned short Data) { - __asm__("movw %w[Data], %%fs:%a[Offset]" : : [Offset] "ir" (Offset), [Data] "iq" (Data)); + __asm__ ("movw %[Data], %%fs:%a[Offset]" + : + : [Offset] "ir" (Offset), [Data] "ir" (Data)); } -static __inline__ __attribute__((always_inline)) void __writefsdword(const unsigned long Offset, const unsigned long Data) +static __inline__ __attribute__((always_inline)) void +__writefsdword(const unsigned long Offset, const unsigned long Data) { - __asm__("movl %k[Data], %%fs:%a[Offset]" : : [Offset] "ir" (Offset), [Data] "iq" (Data)); + __asm__ ("movl %[Data], %%fs:%a[Offset]" + : + : [Offset] "ir" (Offset), [Data] "ir" (Data)); } -static __inline__ __attribute__((always_inline)) unsigned char __readfsbyte(const unsigned long Offset) +static __inline__ __attribute__((always_inline)) unsigned char +__readfsbyte(const unsigned long Offset) { unsigned char value; - __asm__("movb %%fs:%a[Offset], %b[value]" : [value] "=q" (value) : [Offset] "irm" (Offset)); + __asm__ ("movb %%fs:%a[Offset], %[value]" + : [value] "=q" (value) + : [Offset] "ir" (Offset)); return value; } -static __inline__ __attribute__((always_inline)) unsigned short __readfsword(const unsigned long Offset) +static __inline__ __attribute__((always_inline)) unsigned short +__readfsword(const unsigned long Offset) { unsigned short value; - __asm__("movw %%fs:%a[Offset], %w[value]" : [value] "=q" (value) : [Offset] "irm" (Offset)); + __asm__ ("movw %%fs:%a[Offset], %[value]" + : [value] "=q" (value) + : [Offset] "ir" (Offset)); return value; } -static __inline__ __attribute__((always_inline)) unsigned long long __readfsdword(unsigned long long Offset) +static __inline__ __attribute__((always_inline)) unsigned long +__readfsdword(unsigned long Offset) { - unsigned long long value; - __asm__("movl %%fs:%a[Offset], %k[value]" : [value] "=q" (value) : [Offset] "irm" (Offset)); + unsigned long value; + __asm__ ("movl %%fs:%a[Offset], %[value]" + : [value] "=r" (value) + : [Offset] "ir" (Offset)); return value; } @@ -582,23 +610,22 @@ static __inline __attribute__(( __always_inline__)) void _mm_sfence (void) { __builtin_ia32_sfence (); } -#endif +#endif /* __SSE3__ */ static __inline__ __attribute__((always_inline)) void __stosb(unsigned char *dest, unsigned char data, size_t count) { __asm__ __volatile__ ( - "cld ; rep ; stosb " - : "=D" (dest), "=c" (count) - : "a"(data), "0"(dest), "1" (count) + "rep ; stosb " + : "+D" (dest), "+c" (count) + : "a"(data) ); } static __inline__ __attribute__((always_inline)) void __movsb(unsigned char *dest, unsigned char *data, size_t count) { __asm__ __volatile__ ( - "cld ; rep ; movsb " - : "=D" (dest), "=S"(data), "=c" (count) - : "S"(data), "0"(dest), "1" (count) + "movsb " + : "+D" (dest), "+S"(data), "+c" (count) ); } @@ -621,4 +648,4 @@ void delay_point ( unsigned short Port, unsigned long Data, unsigned long delayT Index ++; } } -#endif // defined (__GNUC__) +#endif /* defined (__GNUC__) */

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