June 2022 - coreboot-gerrit - mail.coreboot.org

Change in coreboot[master]: {cpu,nb}/intel/haswell: Drop unnecessary `UL` suffix
by Angel Pons (Code Review) April 15, 2026

April 15, 2026

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46720 ) Change subject: {cpu,nb}/intel/haswell: Drop unnecessary `UL` suffix ...................................................................... {cpu,nb}/intel/haswell: Drop unnecessary `UL` suffix Tested with BUILD_TIMELESS=1, Google Wolf does not change. Change-Id: I029ab0dccbf7b61d641cccf79b491fabf97ab74a Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/intel/haswell/haswell.h M src/northbridge/intel/haswell/finalize.c M src/northbridge/intel/haswell/gma.c M src/northbridge/intel/haswell/northbridge.c 4 files changed, 8 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/46720/1 diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index fd1ce9e..e0e1e1c 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -84,7 +84,7 @@ /* PCODE MMIO communications live in the MCHBAR. */ #define BIOS_MAILBOX_INTERFACE 0x5da4 -#define MAILBOX_RUN_BUSY (1UL << 31) +#define MAILBOX_RUN_BUSY (1 << 31) #define MAILBOX_BIOS_CMD_READ_PCS 1 #define MAILBOX_BIOS_CMD_WRITE_PCS 2 #define MAILBOX_BIOS_CMD_READ_CALIBRATION 0x509 diff --git a/src/northbridge/intel/haswell/finalize.c b/src/northbridge/intel/haswell/finalize.c index 1600a42..b95b3fe 100644 --- a/src/northbridge/intel/haswell/finalize.c +++ b/src/northbridge/intel/haswell/finalize.c @@ -22,10 +22,10 @@ MCHBAR32_OR(MMIO_PAVP_MSG, 1 << 0); /* PAVP */ MCHBAR32_OR(PCU_DDR_PTM_CTL, 1 << 5); /* DDR PTM */ - MCHBAR32_OR(DMIVCLIM, 1UL << 31); + MCHBAR32_OR(DMIVCLIM, 1 << 31); MCHBAR32_OR(CRDTLCK, 1 << 0); MCHBAR32_OR(MCARBLCK, 1 << 0); - MCHBAR32_OR(REQLIM, 1UL << 31); + MCHBAR32_OR(REQLIM, 1 << 31); MCHBAR32_OR(UMAGFXCTL, 1 << 0); /* UMA GFX */ MCHBAR32_OR(VTDTRKLCK, 1 << 0); /* VTDTRK */ diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index 66c8d2d..0bca230 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -196,7 +196,7 @@ gtt_write_regs(haswell_gt_setup); /* Wait for Mailbox Ready */ - gtt_poll(0x138124, (1UL << 31), (0UL << 31)); + gtt_poll(0x138124, (1 << 31), (0 << 31)); /* Mailbox Data - RC6 VIDS */ gtt_write(0x138128, 0x00000000); @@ -205,7 +205,7 @@ gtt_write(0x138124, 0x80000004); /* Wait for Mailbox Ready */ - gtt_poll(0x138124, (1UL << 31), (0UL << 31)); + gtt_poll(0x138124, (1 << 31), (0 << 31)); /* Enable PM Interrupts */ gtt_write(GEN6_PMIER, GEN6_PM_MBOX_EVENT | GEN6_PM_THERMAL_EVENT | diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index 88ccd71..2d19ccd 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -31,18 +31,18 @@ switch ((pciexbar_reg >> 1) & 3) { case 0: /* 256MB */ - mask = (1UL << 31) | (1 << 30) | (1 << 29) | (1 << 28); + mask = (1 << 31) | (1 << 30) | (1 << 29) | (1 << 28); *base = pciexbar_reg & mask; *len = 256 * 1024 * 1024; return 1; case 1: /* 128M */ - mask = (1UL << 31) | (1 << 30) | (1 << 29) | (1 << 28); + mask = (1 << 31) | (1 << 30) | (1 << 29) | (1 << 28); mask |= (1 << 27); *base = pciexbar_reg & mask; *len = 128 * 1024 * 1024; return 1; case 2: /* 64M */ - mask = (1UL << 31) | (1 << 30) | (1 << 29) | (1 << 28); + mask = (1 << 31) | (1 << 30) | (1 << 29) | (1 << 28); mask |= (1 << 27) | (1 << 26); *base = pciexbar_reg & mask; *len = 64 * 1024 * 1024; -- To view, visit https://review.coreboot.org/c/coreboot/+/46720 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I029ab0dccbf7b61d641cccf79b491fabf97ab74a Gerrit-Change-Number: 46720 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 7

Change in coreboot[master]: cpu/intel/haswell: Clean up CPUID definitions
by Angel Pons (Code Review) April 14, 2026

April 14, 2026

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46915 ) Change subject: cpu/intel/haswell: Clean up CPUID definitions ...................................................................... cpu/intel/haswell: Clean up CPUID definitions The `mobile` suffix is misleading, since desktop CPUs share the same CPUIDs. Remove unused stepping IDs and add the full CPUIDs instead. Finally, add Broadwell CPUIDs in preparation for merging CPU code. Note that steppings for Haswell in various comments are incorrect. Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical. Change-Id: I19e56b8826b1514550ae95e6363b0df2d08e3cb7 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/intel/haswell/haswell.h M src/cpu/intel/haswell/haswell_init.c 2 files changed, 31 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/46915/1 diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index 284ff01..b23fbac 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -5,19 +5,32 @@ #include <stdint.h> -/* Haswell CPU types */ -#define HASWELL_FAMILY_MOBILE 0x306c0 -#define HASWELL_FAMILY_ULT 0x40650 +/* CPU types without stepping */ +#define HASWELL_FAMILY_TRAD 0x306c0 +#define HASWELL_FAMILY_ULT 0x40650 +#define CRYSTALWELL_FAMILY 0x306c0 +#define BROADWELL_FAMILY_ULT 0x306d0 -/* Haswell CPU steppings */ -#define HASWELL_STEPPING_MOBILE_A0 1 -#define HASWELL_STEPPING_MOBILE_B0 2 -#define HASWELL_STEPPING_MOBILE_C0 3 -#define HASWELL_STEPPING_MOBILE_D0 4 -#define HASWELL_STEPPING_ULT_B0 0 -#define HASWELL_STEPPING_ULT_C0 1 +/* Haswell CPUIDs */ +#define CPUID_HASWELL_A0 0x306c1 +#define CPUID_HASWELL_B0 0x306c2 +#define CPUID_HASWELL_C0 0x306c3 -/* Haswell bus clock is fixed at 100MHz */ +#define CPUID_HASWELL_ULT_B0 0x40650 +#define CPUID_HASWELL_ULT_C0 0x40651 + +/* Crystalwell CPUIDs */ +#define CPUID_CRYSTALWELL_B0 0x40660 +#define CPUID_CRYSTALWELL_C0 0x40661 + +/* Broadwell CPUIDs */ +#define CPUID_BROADWELL_C0 0x40671 + +#define CPUID_BROADWELL_ULT_C0 0x306d2 +#define CPUID_BROADWELL_ULT_D0 0x306d3 +#define CPUID_BROADWELL_ULT_E0 0x306d4 + +/* Haswell and Broadwell bus clock is fixed at 100MHz */ #define CPU_BCLK 100 #define MSR_CORE_THREAD_COUNT 0x35 diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 44bbbfd..438a317 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -694,13 +694,13 @@ }; static const struct cpu_device_id cpu_table[] = { - { X86_VENDOR_INTEL, 0x306c1 }, /* Intel Haswell 4+2 A0 */ - { X86_VENDOR_INTEL, 0x306c2 }, /* Intel Haswell 4+2 B0 */ - { X86_VENDOR_INTEL, 0x306c3 }, /* Intel Haswell C0 */ - { X86_VENDOR_INTEL, 0x40650 }, /* Intel Haswell ULT B0 */ - { X86_VENDOR_INTEL, 0x40651 }, /* Intel Haswell ULT B1 */ - { X86_VENDOR_INTEL, 0x40660 }, /* Intel Crystal Well C0 */ - { X86_VENDOR_INTEL, 0x40661 }, /* Intel Crystal Well C1 */ + { X86_VENDOR_INTEL, CPUID_HASWELL_A0 }, + { X86_VENDOR_INTEL, CPUID_HASWELL_B0 }, + { X86_VENDOR_INTEL, CPUID_HASWELL_C0 }, + { X86_VENDOR_INTEL, CPUID_HASWELL_ULT_B0 }, + { X86_VENDOR_INTEL, CPUID_HASWELL_ULT_C0 }, + { X86_VENDOR_INTEL, CPUID_CRYSTALWELL_B0 }, + { X86_VENDOR_INTEL, CPUID_CRYSTALWELL_C0 }, { 0, 0 }, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/46915 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I19e56b8826b1514550ae95e6363b0df2d08e3cb7 Gerrit-Change-Number: 46915 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 5

Change in coreboot[master]: mainboard/dell: Add Latitude E7440
by Pablo Stebler (Code Review) March 11, 2026

March 11, 2026

Pablo Stebler has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46540 ) Change subject: mainboard/dell: Add Latitude E7440 ...................................................................... mainboard/dell: Add Latitude E7440 Based on autoport output. Untested for now. Signed-off-by: Pablo Stebler <pablo(a)stebler.xyz> Change-Id: I9459d8dac9552529fc90633eaadd89f5118b237e --- M src/mainboard/dell/latitude_e7x40/Kconfig M src/mainboard/dell/latitude_e7x40/Kconfig.name A src/mainboard/dell/latitude_e7x40/variants/latitude_e7440/board_info.txt A src/mainboard/dell/latitude_e7x40/variants/latitude_e7440/gpio.c A src/mainboard/dell/latitude_e7x40/variants/latitude_e7440/hda_verb.c A src/mainboard/dell/latitude_e7x40/variants/latitude_e7440/overridetree.cb 6 files changed, 152 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/46540/1 diff --git a/src/mainboard/dell/latitude_e7x40/Kconfig b/src/mainboard/dell/latitude_e7x40/Kconfig index 05ed643..9b9bae7 100644 --- a/src/mainboard/dell/latitude_e7x40/Kconfig +++ b/src/mainboard/dell/latitude_e7x40/Kconfig @@ -23,10 +23,12 @@ config VARIANT_DIR string default "latitude_e7240" if BOARD_DELL_LATITUDE_E7240 + default "latitude_e7440" if BOARD_DELL_LATITUDE_E7440 config MAINBOARD_PART_NUMBER string default "Latitude E7240" if BOARD_DELL_LATITUDE_E7240 + default "Latitude E7440" if BOARD_DELL_LATITUDE_E7440 config VGA_BIOS_FILE string diff --git a/src/mainboard/dell/latitude_e7x40/Kconfig.name b/src/mainboard/dell/latitude_e7x40/Kconfig.name index 5eefdf7..4532758 100644 --- a/src/mainboard/dell/latitude_e7x40/Kconfig.name +++ b/src/mainboard/dell/latitude_e7x40/Kconfig.name @@ -4,3 +4,8 @@ bool "Latitude E7240" select BOARD_DELL_LATITUDE_E7x40 + +config BOARD_DELL_LATITUDE_E7440 + bool "Latitude E7440" + + select BOARD_DELL_LATITUDE_E7x40 diff --git a/src/mainboard/dell/latitude_e7x40/variants/latitude_e7440/board_info.txt b/src/mainboard/dell/latitude_e7x40/variants/latitude_e7440/board_info.txt new file mode 100644 index 0000000..6d6a545 --- /dev/null +++ b/src/mainboard/dell/latitude_e7x40/variants/latitude_e7440/board_info.txt @@ -0,0 +1 @@ +Board URL: https://www.dell.com/support/home/en-us/product-support/product/latitude-e7… diff --git a/src/mainboard/dell/latitude_e7x40/variants/latitude_e7440/gpio.c b/src/mainboard/dell/latitude_e7x40/variants/latitude_e7440/gpio.c new file mode 100644 index 0000000..89531a3 --- /dev/null +++ b/src/mainboard/dell/latitude_e7x40/variants/latitude_e7440/gpio.c @@ -0,0 +1,112 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/lynxpoint/lp_gpio.h> + +const struct pch_lp_gpio_map mainboard_gpio_map[] = { + [0] = LP_GPIO_OUT_LOW, + [1] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [2] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [3] = LP_GPIO_OUT_LOW, + [4] = LP_GPIO_NATIVE, + [5] = LP_GPIO_NATIVE, + [6] = LP_GPIO_NATIVE, + [7] = LP_GPIO_NATIVE, + [8] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL, + .pirq = GPIO_PIRQ_APIC_ROUTE }, + [9] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL, + .pirq = GPIO_PIRQ_APIC_ROUTE }, + [10] = LP_GPIO_OUT_LOW, + [11] = LP_GPIO_NATIVE, + [12] = LP_GPIO_NATIVE, + [13] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL, + .pirq = GPIO_PIRQ_APIC_ROUTE }, + [14] = LP_GPIO_OUT_LOW, + [15] = LP_GPIO_OUT_LOW, + [16] = LP_GPIO_OUT_HIGH, + [17] = LP_GPIO_OUT_LOW, + [18] = LP_GPIO_NATIVE, + [19] = LP_GPIO_NATIVE, + [20] = LP_GPIO_NATIVE, + [21] = LP_GPIO_NATIVE, + [22] = LP_GPIO_NATIVE, + [23] = LP_GPIO_NATIVE, + [24] = LP_GPIO_OUT_LOW, + [25] = LP_GPIO_OUT_LOW, + [26] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT }, + [27] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [28] = LP_GPIO_OUT_LOW, + [29] = LP_GPIO_NATIVE, + [30] = LP_GPIO_NATIVE, + [31] = LP_GPIO_NATIVE, + [32] = LP_GPIO_NATIVE, + [33] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [34] = LP_GPIO_OUT_HIGH, + [35] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [36] = LP_GPIO_OUT_LOW, + [37] = LP_GPIO_NATIVE, + [38] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [39] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [40] = LP_GPIO_NATIVE, + [41] = LP_GPIO_NATIVE, + [42] = LP_GPIO_NATIVE, + [43] = LP_GPIO_NATIVE, + [44] = LP_GPIO_OUT_LOW, + [45] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL, + .route = GPIO_ROUTE_SMI, + .pirq = GPIO_PIRQ_APIC_ROUTE }, + [46] = LP_GPIO_OUT_LOW, + [47] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT, + .pirq = GPIO_PIRQ_APIC_ROUTE }, + [48] = LP_GPIO_OUT_LOW, + [49] = LP_GPIO_OUT_LOW, + [50] = LP_GPIO_OUT_HIGH, + [51] = LP_GPIO_OUT_LOW, + [52] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL, + .pirq = GPIO_PIRQ_APIC_ROUTE }, + [53] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, + .pirq = GPIO_PIRQ_APIC_ROUTE }, + [54] = LP_GPIO_OUT_LOW, + [55] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT, + .pirq = GPIO_PIRQ_APIC_ROUTE }, + [56] = LP_GPIO_OUT_HIGH, + [57] = LP_GPIO_OUT_HIGH, + [58] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT }, + [59] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [60] = LP_GPIO_OUT_LOW, + [61] = LP_GPIO_NATIVE, + [62] = LP_GPIO_NATIVE, + [63] = LP_GPIO_NATIVE, + [64] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [65] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [66] = LP_GPIO_OUT_LOW, + [67] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [68] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [69] = LP_GPIO_OUT_HIGH, + [70] = LP_GPIO_OUT_LOW, + [71] = LP_GPIO_NATIVE, + [72] = LP_GPIO_NATIVE, + [73] = LP_GPIO_OUT_LOW, + [74] = LP_GPIO_NATIVE, + [75] = LP_GPIO_NATIVE, + [76] = LP_GPIO_OUT_HIGH, + [77] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [78] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL, + .route = GPIO_ROUTE_SMI }, + [79] = LP_GPIO_NATIVE, + [80] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [81] = LP_GPIO_NATIVE, + [82] = LP_GPIO_NATIVE, + [83] = LP_GPIO_OUT_HIGH, + [84] = LP_GPIO_OUT_HIGH, + [85] = LP_GPIO_OUT_HIGH, + [86] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [87] = LP_GPIO_OUT_LOW, + [88] = LP_GPIO_OUT_LOW, + [89] = LP_GPIO_OUT_HIGH, + [90] = LP_GPIO_OUT_HIGH, + [91] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [92] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [93] = LP_GPIO_OUT_LOW, + [94] = LP_GPIO_OUT_LOW, + LP_GPIO_END +}; diff --git a/src/mainboard/dell/latitude_e7x40/variants/latitude_e7440/hda_verb.c b/src/mainboard/dell/latitude_e7x40/variants/latitude_e7440/hda_verb.c new file mode 100644 index 0000000..e358006 --- /dev/null +++ b/src/mainboard/dell/latitude_e7x40/variants/latitude_e7440/hda_verb.c @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0292, /* Codec Vendor / Device ID: Realtek */ + 0x102805cb, /* Subsystem ID */ + 12, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x102805cb), + AZALIA_PIN_CFG(0, 0x12, 0x90a60140), + AZALIA_PIN_CFG(0, 0x13, 0x411111f0), + AZALIA_PIN_CFG(0, 0x14, 0x90170110), + AZALIA_PIN_CFG(0, 0x15, 0x0221401f), + AZALIA_PIN_CFG(0, 0x16, 0x01014020), + AZALIA_PIN_CFG(0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, 0x01a19030), + AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x40700001), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/dell/latitude_e7x40/variants/latitude_e7440/overridetree.cb b/src/mainboard/dell/latitude_e7x40/variants/latitude_e7440/overridetree.cb new file mode 100644 index 0000000..cc31dc8 --- /dev/null +++ b/src/mainboard/dell/latitude_e7x40/variants/latitude_e7440/overridetree.cb @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-only + +chip northbridge/intel/haswell + device domain 0x0 on + subsystemid 0x1028 0x05cb inherit + end +end -- To view, visit https://review.coreboot.org/c/coreboot/+/46540 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9459d8dac9552529fc90633eaadd89f5118b237e Gerrit-Change-Number: 46540 Gerrit-PatchSet: 1 Gerrit-Owner: Pablo Stebler <pablo(a)stebler.xyz> Gerrit-MessageType: newchange

5 6

Change in coreboot[master]: sb/intel/lynxpoint: Use Broadwell SerialIO implementation
by Angel Pons (Code Review) Feb. 28, 2026

Feb. 28, 2026

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46969 ) Change subject: sb/intel/lynxpoint: Use Broadwell SerialIO implementation ...................................................................... sb/intel/lynxpoint: Use Broadwell SerialIO implementation Add power state control methods for more devices using helper methods. Change-Id: I96a3b896346f6f1e5aa4a1dc45638cbcff01b7dd Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/lynxpoint/acpi/serialio.asl 1 file changed, 96 insertions(+), 34 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/46969/1 diff --git a/src/southbridge/intel/lynxpoint/acpi/serialio.asl b/src/southbridge/intel/lynxpoint/acpi/serialio.asl index 845949c..0e246f7 100644 --- a/src/southbridge/intel/lynxpoint/acpi/serialio.asl +++ b/src/southbridge/intel/lynxpoint/acpi/serialio.asl @@ -16,6 +16,28 @@ External (\S6EN) External (\S7EN) +// Put SerialIO device in D0 state +// Arg0 - Ref to offset 0x84 of device's PCI config space +Method (LPD0, 1, Serialized) +{ + DeRefOf (Arg0) &= 0xFFFFFFFC + Local0 = DeRefOf (Arg0) // Read back after writing + + // Use Local0 to avoid iasl warning: Method Local is set but never used + Local0 &= Ones +} + +// Put SerialIO device in D3 state +// Arg0 - Ref to offset 0x84 of device's PCI config space +Method (LPD3, 1, Serialized) +{ + DeRefOf (Arg0) |= 0x3 + Local0 = DeRefOf (Arg0) // Read back after writing + + // Use Local0 to avoid iasl warning: Method Local is set but never used + Local0 &= Ones +} + // Serial IO Resource Consumption for BAR1 Device (SIOR) { @@ -193,32 +215,20 @@ } } - // Access to PCI Config in ACPI mode - OperationRegion (KEYS, SystemMemory, \S1B1, 0x100) - Field (KEYS, DWordAcc, NoLock, Preserve) + OperationRegion (SPRT, SystemMemory, \S1B1 + 0x84, 4) + Field (SPRT, DWordAcc, NoLock, Preserve) { - Offset (0x84), - PSAT, 32, + SPCS, 32 } - // Put controller in D0 state Method (_PS0, 0, Serialized) { - ^PSAT &= 0xfffffffc - Local0 = ^PSAT // Read back after writing - - // Use Local0 to avoid iasl warning: Method Local is set but never used - Local0 &= Ones + ^^LPD0 (RefOf (SPCS)) } - // Put controller in D3Hot state Method (_PS3, 0, Serialized) { - ^PSAT |= 0x00000003 - Local0 = ^PSAT // Read back after writing - - // Use Local0 to avoid iasl warning: Method Local is set but never used - Local0 &= Ones + ^^LPD3 (RefOf (SPCS)) } } @@ -273,32 +283,20 @@ } } - // Access to PCI Config in ACPI mode - OperationRegion (KEYS, SystemMemory, \S2B1, 0x100) - Field (KEYS, DWordAcc, NoLock, Preserve) + OperationRegion (SPRT, SystemMemory, \S2B1 + 0x84, 4) + Field (SPRT, DWordAcc, NoLock, Preserve) { - Offset (0x84), - PSAT, 32, + SPCS, 32 } - // Put controller in D0 state Method (_PS0, 0, Serialized) { - ^PSAT &= 0xfffffffc - Local0 = ^PSAT // Read back after writing - - // Use Local0 to avoid iasl warning: Method Local is set but never used - Local0 &= Ones + ^^LPD0 (RefOf (SPCS)) } - // Put controller in D3Hot state Method (_PS3, 0, Serialized) { - ^PSAT |= 0x00000003 - Local0 = ^PSAT // Read back after writing - - // Use Local0 to avoid iasl warning: Method Local is set but never used - Local0 &= Ones + ^^LPD3 (RefOf (SPCS)) } } @@ -337,6 +335,22 @@ Return (0xF) } } + + OperationRegion (SPRT, SystemMemory, \S3B1 + 0x84, 4) + Field (SPRT, DWordAcc, NoLock, Preserve) + { + SPCS, 32 + } + + Method (_PS0, 0, Serialized) + { + ^^LPD0 (RefOf (SPCS)) + } + + Method (_PS3, 0, Serialized) + { + ^^LPD3 (RefOf (SPCS)) + } } Device (SPI1) @@ -386,6 +400,22 @@ Return (0xF) } } + + OperationRegion (SPRT, SystemMemory, \S4B1 + 0x84, 4) + Field (SPRT, DWordAcc, NoLock, Preserve) + { + SPCS, 32 + } + + Method (_PS0, 0, Serialized) + { + ^^LPD0 (RefOf (SPCS)) + } + + Method (_PS3, 0, Serialized) + { + ^^LPD3 (RefOf (SPCS)) + } } Device (UAR0) @@ -435,6 +465,22 @@ Return (0xF) } } + + OperationRegion (SPRT, SystemMemory, \S5B1 + 0x84, 4) + Field (SPRT, DWordAcc, NoLock, Preserve) + { + SPCS, 32 + } + + Method (_PS0, 0, Serialized) + { + ^^LPD0 (RefOf (SPCS)) + } + + Method (_PS3, 0, Serialized) + { + ^^LPD3 (RefOf (SPCS)) + } } Device (UAR1) @@ -472,6 +518,22 @@ Return (0xF) } } + + OperationRegion (SPRT, SystemMemory, \S6B1 + 0x84, 4) + Field (SPRT, DWordAcc, NoLock, Preserve) + { + SPCS, 32 + } + + Method (_PS0, 0, Serialized) + { + ^^LPD0 (RefOf (SPCS)) + } + + Method (_PS3, 0, Serialized) + { + ^^LPD3 (RefOf (SPCS)) + } } Device (SDIO) -- To view, visit https://review.coreboot.org/c/coreboot/+/46969 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I96a3b896346f6f1e5aa4a1dc45638cbcff01b7dd Gerrit-Change-Number: 46969 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

3 8

Change in coreboot[master]: soc/intel/broadwell: Improve LPD0/LPD3 SerialIO ACPI methods
by Angel Pons (Code Review) Feb. 28, 2026

Feb. 28, 2026

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46967 ) Change subject: soc/intel/broadwell: Improve LPD0/LPD3 SerialIO ACPI methods ...................................................................... soc/intel/broadwell: Improve LPD0/LPD3 SerialIO ACPI methods Creating named objects within a method is highly inefficient. So, pass a reference to the OperationRegion field that needs to be updated instead. Change-Id: I88272fc5cbe35427ccb5fc50789d47b66ace88fe Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/pch/acpi/serialio.asl 1 file changed, 54 insertions(+), 30 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/46967/1 diff --git a/src/soc/intel/broadwell/pch/acpi/serialio.asl b/src/soc/intel/broadwell/pch/acpi/serialio.asl index b03bcdd..35b15b4 100644 --- a/src/soc/intel/broadwell/pch/acpi/serialio.asl +++ b/src/soc/intel/broadwell/pch/acpi/serialio.asl @@ -6,34 +6,22 @@ #define SIO_BAR_LEN 0x1000 // Put SerialIO device in D0 state -// Arg0 - BAR1 of device +// Arg0 - Ref to offset 0x84 of device's PCI config space Method (LPD0, 1, Serialized) { - OperationRegion (SPRT, SystemMemory, Arg0 + 0x84, 4) - Field (SPRT, DWordAcc, NoLock, Preserve) - { - SPCS, 32 - } - - SPCS &= 0xFFFFFFFC - Local0 = SPCS // Read back after writing + DeRefOf (Arg0) &= 0xFFFFFFFC + Local0 = DeRefOf (Arg0) // Read back after writing // Use Local0 to avoid iasl warning: Method Local is set but never used Local0 &= Ones } // Put SerialIO device in D3 state -// Arg0 - BAR1 of device +// Arg0 - Ref to offset 0x84 of device's PCI config space Method (LPD3, 1, Serialized) { - OperationRegion (SPRT, SystemMemory, Arg0 + 0x84, 4) - Field (SPRT, DWordAcc, NoLock, Preserve) - { - SPCS, 32 - } - - SPCS |= 0x3 - Local0 = SPCS // Read back after writing + DeRefOf (Arg0) |= 0x3 + Local0 = DeRefOf (Arg0) // Read back after writing // Use Local0 to avoid iasl warning: Method Local is set but never used Local0 &= Ones @@ -226,14 +214,20 @@ } } + OperationRegion (SPRT, SystemMemory, \S1B1 + 0x84, 4) + Field (SPRT, DWordAcc, NoLock, Preserve) + { + SPCS, 32 + } + Method (_PS0, 0, Serialized) { - ^^LPD0 (\S1B1) + ^^LPD0 (RefOf (SPCS)) } Method (_PS3, 0, Serialized) { - ^^LPD3 (\S1B1) + ^^LPD3 (RefOf (SPCS)) } } @@ -297,14 +291,20 @@ } } + OperationRegion (SPRT, SystemMemory, \S2B1 + 0x84, 4) + Field (SPRT, DWordAcc, NoLock, Preserve) + { + SPCS, 32 + } + Method (_PS0, 0, Serialized) { - ^^LPD0 (\S2B1) + ^^LPD0 (RefOf (SPCS)) } Method (_PS3, 0, Serialized) { - ^^LPD3 (\S2B1) + ^^LPD3 (RefOf (SPCS)) } } @@ -353,14 +353,20 @@ } } + OperationRegion (SPRT, SystemMemory, \S3B1 + 0x84, 4) + Field (SPRT, DWordAcc, NoLock, Preserve) + { + SPCS, 32 + } + Method (_PS0, 0, Serialized) { - ^^LPD0 (\S3B1) + ^^LPD0 (RefOf (SPCS)) } Method (_PS3, 0, Serialized) { - ^^LPD3 (\S3B1) + ^^LPD3 (RefOf (SPCS)) } } @@ -421,14 +427,20 @@ } } + OperationRegion (SPRT, SystemMemory, \S4B1 + 0x84, 4) + Field (SPRT, DWordAcc, NoLock, Preserve) + { + SPCS, 32 + } + Method (_PS0, 0, Serialized) { - ^^LPD0 (\S4B1) + ^^LPD0 (RefOf (SPCS)) } Method (_PS3, 0, Serialized) { - ^^LPD3 (\S4B1) + ^^LPD3 (RefOf (SPCS)) } } @@ -489,14 +501,20 @@ } } + OperationRegion (SPRT, SystemMemory, \S5B1 + 0x84, 4) + Field (SPRT, DWordAcc, NoLock, Preserve) + { + SPCS, 32 + } + Method (_PS0, 0, Serialized) { - ^^LPD0 (\S5B1) + ^^LPD0 (RefOf (SPCS)) } Method (_PS3, 0, Serialized) { - ^^LPD3 (\S5B1) + ^^LPD3 (RefOf (SPCS)) } } @@ -545,14 +563,20 @@ } } + OperationRegion (SPRT, SystemMemory, \S6B1 + 0x84, 4) + Field (SPRT, DWordAcc, NoLock, Preserve) + { + SPCS, 32 + } + Method (_PS0, 0, Serialized) { - ^^LPD0 (\S6B1) + ^^LPD0 (RefOf (SPCS)) } Method (_PS3, 0, Serialized) { - ^^LPD3 (\S6B1) + ^^LPD3 (RefOf (SPCS)) } } -- To view, visit https://review.coreboot.org/c/coreboot/+/46967 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I88272fc5cbe35427ccb5fc50789d47b66ace88fe Gerrit-Change-Number: 46967 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 8

Change in ...coreboot[master]: mb/apple: Add MacBook Pro 10,1 (A1398) support
by Evgeny Zinoviev (Code Review) Jan. 18, 2026

Jan. 18, 2026

Evgeny Zinoviev has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32673 Change subject: mb/apple: Add MacBook Pro 10,1 (A1398) support ...................................................................... mb/apple: Add MacBook Pro 10,1 (A1398) support MacBook Pro Retina 15 (Mid 2012) with Ivy Bridge CPU. This is WIP. Not for merging. Change-Id: Ica03aba442493c0d369a3d360ad569ddc16954df Signed-off-by: Evgeny Zinoviev <me(a)ch1p.io> --- M 3rdparty/vboot A src/mainboard/apple/macbookpro10_1/Kconfig A src/mainboard/apple/macbookpro10_1/Kconfig.name A src/mainboard/apple/macbookpro10_1/Makefile.inc A src/mainboard/apple/macbookpro10_1/acpi/ec.asl A src/mainboard/apple/macbookpro10_1/acpi/platform.asl A src/mainboard/apple/macbookpro10_1/acpi/superio.asl A src/mainboard/apple/macbookpro10_1/acpi_tables.c A src/mainboard/apple/macbookpro10_1/board_info.txt A src/mainboard/apple/macbookpro10_1/devicetree.cb A src/mainboard/apple/macbookpro10_1/dsdt.asl A src/mainboard/apple/macbookpro10_1/gma-mainboard.ads A src/mainboard/apple/macbookpro10_1/gpio.c A src/mainboard/apple/macbookpro10_1/hda_verb.c A src/mainboard/apple/macbookpro10_1/mainboard.c A src/mainboard/apple/macbookpro10_1/romstage.c 16 files changed, 758 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/32673/1 diff --git a/3rdparty/vboot b/3rdparty/vboot index e7edff6..304aa42 160000 --- a/3rdparty/vboot +++ b/3rdparty/vboot @@ -1 +1 @@ -Subproject commit e7edff6653e16ed915c3ad12234d133d1ef4dcc9 +Subproject commit 304aa429c1a04cda3ab2ce37b9e31af84405bfca diff --git a/src/mainboard/apple/macbookpro10_1/Kconfig b/src/mainboard/apple/macbookpro10_1/Kconfig new file mode 100644 index 0000000..603f3ee --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/Kconfig @@ -0,0 +1,46 @@ +if BOARD_APPLE_MACBOOKPRO10_1 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select EC_ACPI + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_INT15 + select NORTHBRIDGE_INTEL_IVYBRIDGE + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_C216 + select SYSTEM_TYPE_LAPTOP + select USE_NATIVE_RAMINIT + select MAINBOARD_HAS_LIBGFXINIT + select GFX_GMA_INTERNAL_IS_EDP + select SERIRQ_CONTINUOUS_MODE + +config MAINBOARD_DIR + string + default apple/macbookpro10_1 + +config MAINBOARD_PART_NUMBER + string + default "MacBookPro10,1" + +config VGA_BIOS_FILE + string + default "pci8086,0166.rom" + +config VGA_BIOS_ID + string + default "8086,0166" + +config DRAM_RESET_GATE_GPIO + int + default 28 + +config MAX_CPUS + int + default 8 + +config USBDEBUG_HCD_INDEX # FIXME: check this + int + default 2 +endif diff --git a/src/mainboard/apple/macbookpro10_1/Kconfig.name b/src/mainboard/apple/macbookpro10_1/Kconfig.name new file mode 100644 index 0000000..c257f7a --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_APPLE_MACBOOKPRO10_1 + bool "MacBookPro10,1" diff --git a/src/mainboard/apple/macbookpro10_1/Makefile.inc b/src/mainboard/apple/macbookpro10_1/Makefile.inc new file mode 100644 index 0000000..fd60338 --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/Makefile.inc @@ -0,0 +1,7 @@ +romstage-y += gpio.c + +cbfs-files-y += spd.bin +spd.bin-file := spd.bin +spd.bin-type := spd + +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/apple/macbookpro10_1/acpi/ec.asl b/src/mainboard/apple/macbookpro10_1/acpi/ec.asl new file mode 100644 index 0000000..f70cb3d --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/acpi/ec.asl @@ -0,0 +1,20 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device(EC) +{ + Name (_HID, EISAID("PNP0C09")) + Name (_UID, 0) + Name (_GPE, 23) +/* FIXME: EC support */ +} diff --git a/src/mainboard/apple/macbookpro10_1/acpi/platform.asl b/src/mainboard/apple/macbookpro10_1/acpi/platform.asl new file mode 100644 index 0000000..a17c6ea --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/acpi/platform.asl @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Method(_WAK,1) +{ + /* FIXME: EC support */ + Return(Package(){0,0}) +} + +Method(_PTS,1) +{ + /* FIXME: EC support */ +} diff --git a/src/mainboard/apple/macbookpro10_1/acpi/superio.asl b/src/mainboard/apple/macbookpro10_1/acpi/superio.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/acpi/superio.asl diff --git a/src/mainboard/apple/macbookpro10_1/acpi_tables.c b/src/mainboard/apple/macbookpro10_1/acpi_tables.c new file mode 100644 index 0000000..c48f0bd --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/acpi_tables.c @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/bd82x6x/nvs.h> + +/* FIXME: check this function. */ +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + /* Disable USB ports in S3 by default */ + gnvs->s3u0 = 0; + gnvs->s3u1 = 0; + + /* Disable USB ports in S5 by default */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + // the lid is open by default. + gnvs->lids = 1; + + gnvs->tcrt = 100; + gnvs->tpsv = 90; +} diff --git a/src/mainboard/apple/macbookpro10_1/board_info.txt b/src/mainboard/apple/macbookpro10_1/board_info.txt new file mode 100644 index 0000000..81a5134 --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/board_info.txt @@ -0,0 +1,6 @@ +Category: laptop +ROM protocol: SPI +Flashrom support: n +ROM package: SOIC-8 +ROM socketed: n +Release year: 2012 diff --git a/src/mainboard/apple/macbookpro10_1/devicetree.cb b/src/mainboard/apple/macbookpro10_1/devicetree.cb new file mode 100644 index 0000000..f9e7eb4 --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/devicetree.cb @@ -0,0 +1,124 @@ +chip northbridge/intel/sandybridge # FIXME: check gfx.ndid and gfx.did + #register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }" + register "gfx.did" = "{ 0x80000410, 0x80000320, 0x80000410, 0x80000410, 0x00000005 }" + register "gfx.link_frequency_270_mhz" = "0" + register "gfx.ndid" = "3" + register "gfx.use_spread_spectrum_clock" = "1" + register "gpu_cpu_backlight" = "0xffffffff" + register "gpu_dp_b_hotplug" = "7" + register "gpu_dp_c_hotplug" = "7" + register "gpu_dp_d_hotplug" = "7" + register "gpu_panel_port_select" = "3" + register "gpu_panel_power_backlight_off_delay" = "8191" + register "gpu_panel_power_backlight_on_delay" = "8191" + register "gpu_panel_power_cycle_delay" = "255" + register "gpu_panel_power_down_delay" = "8191" + register "gpu_panel_power_up_delay" = "8191" + register "gpu_pch_backlight" = "0xffffffff" + device cpu_cluster 0x0 on + chip cpu/intel/model_206ax # FIXME: check all registers + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0x0 on + end + device lapic 0xacac off + end + end + end + device domain 0x0 on + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "c2_latency" = "0x0065" + register "docking_supported" = "0" + register "gen1_dec" = "0x000c0681" + register "gen2_dec" = "0x000c1641" + register "gen3_dec" = "0x001c0301" + register "gen4_dec" = "0x00fc0701" + register "gpi7_routing" = "2" + register "p_cnt_throttling_supported" = "1" + register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" + register "pcie_port_coalesce" = "1" + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x1" + register "spi_lvscc" = "0x0" + register "spi_uvscc" = "0x2005" + register "superspeed_capable_ports" = "0x0000000f" + register "xhci_overcurrent_mapping" = "0x08040201" + register "xhci_switchable_ports" = "0x0000000f" + device pci 14.0 on # USB 3.0 Controller + subsystemid 0x8086 0x7270 + end + device pci 16.0 on # Management Engine Interface 1 + subsystemid 0x8086 0x7270 + end + device pci 16.1 off # Management Engine Interface 2 + end + device pci 16.2 off # Management Engine IDE-R + end + device pci 16.3 off # Management Engine KT + end + device pci 19.0 off # Intel Gigabit Ethernet + end + device pci 1a.0 on # USB2 EHCI #2 + subsystemid 0x8086 0x7270 + end + device pci 1b.0 on # High Definition Audio Audio controller + subsystemid 0x8086 0x7270 + end + device pci 1c.0 on # PCIe Port #1 + subsystemid 0x8086 0x7270 + end + device pci 1c.1 on # PCIe Port #2 + subsystemid 0x8086 0x7270 + end + device pci 1c.2 off # PCIe Port #3 + end + device pci 1c.3 off # PCIe Port #4 + end + device pci 1c.4 off # PCIe Port #5 + end + device pci 1c.5 off # PCIe Port #6 + end + device pci 1c.6 off # PCIe Port #7 + end + device pci 1c.7 off # PCIe Port #8 + end + device pci 1d.0 on # USB2 EHCI #1 + subsystemid 0x8086 0x7270 + end + device pci 1e.0 off # PCI bridge + end + device pci 1f.0 on # LPC bridge PCI-LPC bridge + subsystemid 0x8086 0x7270 + end + device pci 1f.2 on # SATA Controller 1 + subsystemid 0x8086 0x7270 + end + device pci 1f.3 on # SMBus + subsystemid 0x8086 0x7270 + end + device pci 1f.5 off # SATA Controller 2 + end + device pci 1f.6 off # Thermal + end + end + device pci 00.0 on # Host bridge Host bridge + subsystemid 0x106b 0x00f7 + end + device pci 01.0 on # PCIe Bridge for discrete graphics + subsystemid 0x106b 0x00f7 + end + device pci 02.0 on # Internal graphics VGA controller + subsystemid 0x106b 0x00f7 + end + device pci 01.2 on + subsystemid 0x106b 0x00f7 + end + device pci 01.1 on + subsystemid 0x106b 0x00f7 + end + end +end diff --git a/src/mainboard/apple/macbookpro10_1/dsdt.asl b/src/mainboard/apple/macbookpro10_1/dsdt.asl new file mode 100644 index 0000000..455ac17 --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/dsdt.asl @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB +#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB +#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 + +#include <arch/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI 2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 // OEM revision +) +{ + /* Some generic macros */ + #include "acpi/platform.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/bd82x6x/acpi/platform.asl> + /* global NVS and variables. */ + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> + + Device (\_SB.PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } +} diff --git a/src/mainboard/apple/macbookpro10_1/gma-mainboard.ads b/src/mainboard/apple/macbookpro10_1/gma-mainboard.ads new file mode 100644 index 0000000..d4a5d7d --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/gma-mainboard.ads @@ -0,0 +1,34 @@ +-- +-- This file is part of the coreboot project. +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP1, + DP2, + DP3, + HDMI1, + HDMI2, + HDMI3, + Analog, + Internal, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/apple/macbookpro10_1/gpio.c b/src/mainboard/apple/macbookpro10_1/gpio.c new file mode 100644 index 0000000..a445687 --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/gpio.c @@ -0,0 +1,243 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_GPIO, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_OUTPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_OUTPUT, + .gpio21 = GPIO_DIR_OUTPUT, + .gpio22 = GPIO_DIR_OUTPUT, + .gpio23 = GPIO_DIR_OUTPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio26 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio8 = GPIO_LEVEL_HIGH, + .gpio12 = GPIO_LEVEL_LOW, + .gpio15 = GPIO_LEVEL_HIGH, + .gpio16 = GPIO_LEVEL_LOW, + .gpio19 = GPIO_LEVEL_HIGH, + .gpio21 = GPIO_LEVEL_LOW, + .gpio22 = GPIO_LEVEL_LOW, + .gpio23 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio11 = GPIO_RESET_RSMRST, + .gpio15 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio1 = GPIO_INVERT, + .gpio2 = GPIO_INVERT, + .gpio4 = GPIO_INVERT, + .gpio5 = GPIO_INVERT, + .gpio7 = GPIO_INVERT, + .gpio14 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_GPIO, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_GPIO, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_GPIO, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio33 = GPIO_DIR_INPUT, + .gpio34 = GPIO_DIR_OUTPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio36 = GPIO_DIR_OUTPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio47 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_OUTPUT, + .gpio49 = GPIO_DIR_OUTPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_OUTPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_OUTPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio56 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio34 = GPIO_LEVEL_HIGH, + .gpio35 = GPIO_LEVEL_LOW, + .gpio36 = GPIO_LEVEL_LOW, + .gpio48 = GPIO_LEVEL_HIGH, + .gpio49 = GPIO_LEVEL_HIGH, + .gpio51 = GPIO_LEVEL_HIGH, + .gpio52 = GPIO_LEVEL_LOW, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio54 = GPIO_LEVEL_LOW, + .gpio55 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_GPIO, + .gpio65 = GPIO_MODE_GPIO, + .gpio66 = GPIO_MODE_GPIO, + .gpio67 = GPIO_MODE_GPIO, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_NATIVE, + .gpio73 = GPIO_MODE_GPIO, + .gpio74 = GPIO_MODE_GPIO, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio64 = GPIO_DIR_OUTPUT, + .gpio65 = GPIO_DIR_OUTPUT, + .gpio66 = GPIO_DIR_OUTPUT, + .gpio67 = GPIO_DIR_OUTPUT, + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_INPUT, + .gpio73 = GPIO_DIR_INPUT, + .gpio74 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio64 = GPIO_LEVEL_LOW, + .gpio65 = GPIO_LEVEL_LOW, + .gpio66 = GPIO_LEVEL_LOW, + .gpio67 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/apple/macbookpro10_1/hda_verb.c b/src/mainboard/apple/macbookpro10_1/hda_verb.c new file mode 100644 index 0000000..b8e4855 --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/hda_verb.c @@ -0,0 +1,58 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10134206, /* Codec Vendor / Device ID: Cirrus */ + 0x106b2800, /* Subsystem ID */ + + 0x0000000b, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x0, 0x106b2800), + + /* NID 0x09. */ + AZALIA_PIN_CFG(0x0, 0x09, 0x002b4020), + + /* NID 0x0a. */ + AZALIA_PIN_CFG(0x0, 0x0a, 0x90100112), + + /* NID 0x0b. */ + AZALIA_PIN_CFG(0x0, 0x0b, 0x90100110), + + /* NID 0x0c. */ + AZALIA_PIN_CFG(0x0, 0x0c, 0x400000f0), + + /* NID 0x0d. */ + AZALIA_PIN_CFG(0x0, 0x0d, 0x400000f0), + + /* NID 0x0e. */ + AZALIA_PIN_CFG(0x0, 0x0e, 0x90a60100), + + /* NID 0x0f. */ + AZALIA_PIN_CFG(0x0, 0x0f, 0x400000f0), + + /* NID 0x10. */ + AZALIA_PIN_CFG(0x0, 0x10, 0x004be030), + + /* NID 0x12. */ + AZALIA_PIN_CFG(0x0, 0x12, 0x400000f0), + + /* NID 0x15. */ + AZALIA_PIN_CFG(0x0, 0x15, 0x400000f0), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/apple/macbookpro10_1/mainboard.c b/src/mainboard/apple/macbookpro10_1/mainboard.c new file mode 100644 index 0000000..3910541 --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/mainboard.c @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <ec/acpi/ec.h> +#include <console/console.h> + +static void mainboard_init(struct device *dev) +{ + +} + +static void mainboard_enable(struct device *dev) +{ + dev->ops->init = mainboard_init; + + /* FIXME: fix those values*/ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/apple/macbookpro10_1/romstage.c b/src/mainboard/apple/macbookpro10_1/romstage.c new file mode 100644 index 0000000..c35604b --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/romstage.c @@ -0,0 +1,82 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* FIXME: Check if all includes are needed. */ + +#include <stdint.h> +#include <string.h> +#include <timestamp.h> +#include <arch/byteorder.h> +#include <arch/io.h> +#include <device/mmio.h> +#include <device/pci_ops.h> +#include <device/pnp_ops.h> +#include <console/console.h> +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/common/gpio.h> +#include <cbfs.h> + +void pch_enable_lpc(void) +{ + pci_write_config16(PCH_LPC_DEV, 0x82, 0x3f0f); + pci_write_config32(PCH_LPC_DEV, 0x84, 0x000c0681); + pci_write_config32(PCH_LPC_DEV, 0x88, 0x000c1641); + pci_write_config32(PCH_LPC_DEV, 0x8c, 0x001c0301); + pci_write_config32(PCH_LPC_DEV, 0x90, 0x00fc0701); + pci_write_config16(PCH_LPC_DEV, 0x80, 0x0070); +} + +void mainboard_rcba_config(void) +{ +} + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 0, 0 }, + { 1, 0, 1 }, + { 1, 0, 2 }, + { 1, 0, 3 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, +}; + +void mainboard_early_init(int s3resume) +{ +} + +void mainboard_config_superio(void) +{ +} + +// FIXME +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + void *spd_file; + size_t spd_file_len = 0; + spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, + &spd_file_len); + if (spd_file && spd_file_len >= 128) { + memcpy(&spd[0], spd_file, 128); + memcpy(&spd[2], spd_file, 128); + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/32673 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica03aba442493c0d369a3d360ad569ddc16954df Gerrit-Change-Number: 32673 Gerrit-PatchSet: 1 Gerrit-Owner: Evgeny Zinoviev <me(a)ch1p.com> Gerrit-MessageType: newchange

11 70

Change in coreboot[master]: mb/google/octopus/variants/dood: Disable XHCI LFPS power management
by Kenneth Chan (Code Review) Nov. 28, 2025

Nov. 28, 2025

Kenneth Chan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41143 ) Change subject: mb/google/octopus/variants/dood: Disable XHCI LFPS power management ...................................................................... mb/google/octopus/variants/dood: Disable XHCI LFPS power management LTE module is lost after idle overnight, with this workaround, host will not initiate U3 wakeup at the same time with device, which will avoid the race condition. Disable XHCI LFPS power management. If the option is set in the devicetree, the bits[7:4] in XHCI MMIO BAR + offset 0x80A4 (PMCTRL_REG) will be updated from default 9 to 0. BUG=b:155955302 BRANCH=octopus TEST=build coreboot with DisableXhciLfpsPM being set to 1 and flash the image to the device. Run following command to check if bits[7:4] is set 0: >iotools mmio_read32 "XHCI MMIO BAR + 0x80A4" Signed-off-by: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Change-Id: I88357f44317a5cff2e04508638eb065e5ada4c4c --- M src/mainboard/google/octopus/variants/dood/overridetree.cb M src/mainboard/google/octopus/variants/dood/variant.c 2 files changed, 20 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/41143/1 diff --git a/src/mainboard/google/octopus/variants/dood/overridetree.cb b/src/mainboard/google/octopus/variants/dood/overridetree.cb index 6df9f53..e1f12cf 100644 --- a/src/mainboard/google/octopus/variants/dood/overridetree.cb +++ b/src/mainboard/google/octopus/variants/dood/overridetree.cb @@ -149,4 +149,5 @@ # Disable compliance mode register "DisableComplianceMode" = "1" + register "disable_xhci_lfps_pm" = "0" end diff --git a/src/mainboard/google/octopus/variants/dood/variant.c b/src/mainboard/google/octopus/variants/dood/variant.c index e728fe3..ab049a8 100644 --- a/src/mainboard/google/octopus/variants/dood/variant.c +++ b/src/mainboard/google/octopus/variants/dood/variant.c @@ -8,6 +8,7 @@ #include <delay.h> #include <gpio.h> #include <ec/google/chromeec/ec.h> +#include <soc/intel/apollolake/chip.h> enum { SKU_1_LTE = 1, /* Wifi + LTE */ @@ -61,3 +62,21 @@ return; } } + +void variant_update_devtree(struct device *dev) +{ + struct soc_intel_apollolake_config *cfg = NULL; + + cfg = (struct soc_intel_apollolake_config *)dev->chip_info; + + if (cfg != NULL && cfg->disable_xhci_lfps_pm) { + switch (google_chromeec_get_board_sku()) { + case SKU_1_LTE: + case SKU_3_LTE_2CAM: + cfg->disable_xhci_lfps_pm = 1; + return; + default: + return; + } + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/41143 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I88357f44317a5cff2e04508638eb065e5ada4c4c Gerrit-Change-Number: 41143 Gerrit-PatchSet: 1 Gerrit-Owner: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

5 13

Change in coreboot[master]: mb/google/dedede/var/magolor: Configure I2C high and low time
by Ren Kuo (Code Review) Sept. 17, 2025

Sept. 17, 2025

Ren Kuo has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46613 ) Change subject: mb/google/dedede/var/magolor: Configure I2C high and low time ...................................................................... mb/google/dedede/var/magolor: Configure I2C high and low time Configure the I2C bus high and low time for all enabled I2C buses. BUG=b:168783630 TEST=Measured the I2C bus frequency reduce to 387 KHz. Signed-off-by: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Change-Id: I9f5b81815f86db7bdcea95a95b9c9b235b4a34b1 --- M src/mainboard/google/dedede/variants/magolor/overridetree.cb 1 file changed, 24 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/46613/1 diff --git a/src/mainboard/google/dedede/variants/magolor/overridetree.cb b/src/mainboard/google/dedede/variants/magolor/overridetree.cb index f41e9fa..625546e 100644 --- a/src/mainboard/google/dedede/variants/magolor/overridetree.cb +++ b/src/mainboard/google/dedede/variants/magolor/overridetree.cb @@ -25,18 +25,42 @@ }, .i2c[0] = { .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 190, + .scl_hcnt = 100, + .sda_hold = 40, + } }, .i2c[1] = { .speed = I2C_SPEED_FAST, }, .i2c[2] = { .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 190, + .scl_hcnt = 100, + .sda_hold = 40, + } }, .i2c[3] = { .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 190, + .scl_hcnt = 100, + .sda_hold = 40, + } }, .i2c[4] = { .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 190, + .scl_hcnt = 100, + .sda_hold = 40, + } }, }" -- To view, visit https://review.coreboot.org/c/coreboot/+/46613 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9f5b81815f86db7bdcea95a95b9c9b235b4a34b1 Gerrit-Change-Number: 46613 Gerrit-PatchSet: 1 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

4 8

Change in ...coreboot[master]: SeaBIOS - unofficial patches: advanced_bootmenu and multiple_floppies
by mikeb mikeb (Code Review) June 13, 2025

June 13, 2025

Hello Mike Banon, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/32351 to review the following change. Change subject: SeaBIOS - unofficial patches: advanced_bootmenu and multiple_floppies ...................................................................... SeaBIOS - unofficial patches: advanced_bootmenu and multiple_floppies If you'd like to add the useful floppies to your coreboot (read about them at http://dangerousprototypes.com/docs/Lenovo_G505S_hacking#Useful_floppies ), or to use your USB numpad for choosing a SeaBIOS boot entry, then this change is for you! It contains two valuable patches together with a Makefile mod needed to automatically apply these patches to a cloned SeaBIOS before its' compilation. advanced_bootmenu: up to 35 entries (2 pages if >18), numpad support (console) https://mail.coreboot.org/hyperkitty/list/seabios@seabios.org/thread/CKWLNT… [PATCH v2] ramdisk: search for all available floppy images instead of one https://mail.coreboot.org/pipermail/seabios/2018-December/012670.html Patch descriptions are available at these links, and just in case here's a copy: advanced_bootmenu: up to 35 entries (2 pages if >18), numpad support (console) Add support for up to 35 boot menu entries (2 pages if >18). To solve the ">10" problem currently experienced by SeaBIOS users (there are no 11, 12, etc. keys on a keyboard - so impossible to choose the last menu entries if you got >10 entries because of multiple hard drives / secondary payloads / floppies) - the boot menu has been extended to the letter keys. NOTE: TPM menu has been moved from T to M letter: it is at the end of keyboard's 3rd row of letters and "Trusted" is adjective while "Module" is a noun; alternatively could press '-'. Also, add support for a numpad. Small USB numpad could be really convenient for choosing the boot entries at coreboot boards used as (maybe headless) servers. '/' char on numpad could be used to open the boot menu or to exit it. If there are >10 boot menu entries - the numpad console interface will be enabled: press one or two digit keys and then ENTER to confirm your choice, or remove a digit by pressing the '.Del' key. Also you could call TPM with '-' key at any moment, or boot with a single key press of your fullsize keyboard. [PATCH v2] ramdisk: search for all available floppy images instead of one All the floppy images available at CBFS will be found and listed in a boot menu, instead of the first found. Could be highly valuable if you are participating in a hobby OS development - would like to test multiple versions of your floppy at the same coreboot image, to reduce the amount of re-flashes and accelerate the development at bare metal - or simply you would like to access multiple floppies as a coreboot user. For example: KolibriOS (nice assembly OS with GUI and apps), FreeDOS, MichalOS, Snowdrop and memtest (coreboot's memtest version is buggy, e.g. external USB keyboard isn't working at some laptops; floppy is much better) Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: Idf4efba31091a8678b51c2f6541d440c5cc6d37d --- M payloads/external/SeaBIOS/Makefile A payloads/external/SeaBIOS/advanced_bootmenu.patch A payloads/external/SeaBIOS/multiple_floppies.patch 3 files changed, 551 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/32351/1 diff --git a/payloads/external/SeaBIOS/Makefile b/payloads/external/SeaBIOS/Makefile index e505c8c..ae58c8c 100644 --- a/payloads/external/SeaBIOS/Makefile +++ b/payloads/external/SeaBIOS/Makefile @@ -76,7 +76,18 @@ # echo "# CONFIG_SMBIOS is not set" >> seabios/.config $(MAKE) -C seabios olddefconfig OUT=out/ -build: config +patch: + if [ -d seabios ]; then \ + cd seabios; \ + if [ ! -f .patched ]; then \ + echo " PATCH SeaBIOS $(TAG-y)"; \ + patch -p1 < ./../advanced_bootmenu.patch; \ + patch -p1 < ./../multiple_floppies.patch; \ + touch .patched; \ + fi; \ + fi + +build: config patch echo " MAKE SeaBIOS $(TAG-y)" $(MAKE) -C seabios OUT=out/ diff --git a/payloads/external/SeaBIOS/advanced_bootmenu.patch b/payloads/external/SeaBIOS/advanced_bootmenu.patch new file mode 100644 index 0000000..c914588 --- /dev/null +++ b/payloads/external/SeaBIOS/advanced_bootmenu.patch @@ -0,0 +1,332 @@ +diff --git a/src/boot.c b/src/boot.c +index 9f82f3c..f94dd27 100644 +--- a/src/boot.c ++++ b/src/boot.c +@@ -463,6 +463,7 @@ get_keystroke(int msec) + * Boot menu and BCV execution + ****************************************************************/ + ++#define BOOTMENU_PAGE_SIZE 18 + #define DEFAULT_BOOTMENU_WAIT 2500 + + // Show IPL option menu. +@@ -478,59 +479,282 @@ interactive_bootmenu(void) + ; + + char *bootmsg = romfile_loadfile("etc/boot-menu-message", NULL); +- int menukey = romfile_loadint("etc/boot-menu-key", 1); +- printf("%s", bootmsg ?: "\nPress ESC for boot menu.\n\n"); ++ int menukey = romfile_loadint("etc/boot-menu-key", 1); // custom menukey ++ printf("%s", bootmsg ?: "\nPress ESC or \\ / slash for boot menu.\n\n"); + free(bootmsg); + + u32 menutime = romfile_loadint("etc/boot-menu-wait", DEFAULT_BOOTMENU_WAIT); + enable_bootsplash(); + int scan_code = get_keystroke(menutime); + disable_bootsplash(); +- if (scan_code != menukey) ++ if (scan_code != menukey && // custom menukey ++ scan_code != 1 && // ESC ++ scan_code != 43 && // '\' char on keyboard ++ scan_code != 53 && // '/' char on keyboard ++ scan_code != 98) { // '/' char on numpad ++ if (scan_code == -1) ++ printf("No key pressed.\n"); ++ else ++ printf("Not a menukey pressed.\n"); + return; ++ } + + while (get_keystroke(0) >= 0) + ; + +- printf("Select boot device:\n\n"); + wait_threads(); + +- // Show menu items ++ char keyboard_keys[35] = {'1','2','3','4','5','6','7','8','9','0', ++ 'q','w','e','r','t','y','u','i','o','p', ++ 'a','s','d','f','g','h','j','k','l', ++ 'z','x','c','v','b','n'}; /* m = TPM */ ++ int numpad_scancodes[10] = { 82, 79, 80, 81, 75, 76, 77, 71, 72, 73 }; ++ int numpi = 0; // Key index: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9. ++ int digits = 0; // Numerical length of a current choice number. ++ int decode = 0; // Decode the current choice number into a letter? ++ int entry_id = 0; ++ char desc[77]; ++ ++ printf("Select boot device"); ++ ++ // Show menu items after counting them and determining a number of pages. ++ // Only 35 boot menu items (36 if to count a TPM) are supported currently. ++ + int maxmenu = 0; + struct bootentry_s *pos; +- hlist_for_each_entry(pos, &BootList, node) { +- char desc[77]; ++ hlist_for_each_entry(pos, &BootList, node) + maxmenu++; +- printf("%d. %s\n", maxmenu ++ ++ if (maxmenu > 10) { ++ if (maxmenu > 35) ++ maxmenu = 35; ++ if (maxmenu > BOOTMENU_PAGE_SIZE) ++ printf(" - page 1 :"); ++ else ++ printf(": "); ++ printf(" // press ENTER after your numpad input"); ++ if (maxmenu > BOOTMENU_PAGE_SIZE) ++ printf(" - if any -\n " ++ " // - or to switch between the pages...\n"); ++ else ++ printf(" (if any)\n\n"); ++ } else { ++ printf(":\n\n"); ++ } ++ ++ hlist_for_each_entry(pos, &BootList, node) { ++ if (entry_id == BOOTMENU_PAGE_SIZE) // Show only the first page. ++ break; ++ printf("%c. %s\n", keyboard_keys[entry_id] + , strtcpy(desc, pos->description, ARRAY_SIZE(desc))); ++ entry_id++; + } ++ int tpm_cshm = 0; + if (tpm_can_show_menu()) { +- printf("\nt. TPM Configuration\n"); ++ tpm_cshm = 1; ++ printf("\nm-. TPM Configuration"); + } +- +- // Get key press. If the menu key is ESC, do not restart boot unless +- // 1.5 seconds have passed. Otherwise users (trained by years of +- // repeatedly hitting keys to enter the BIOS) will end up hitting ESC +- // multiple times and immediately booting the primary boot device. +- int esc_accepted_time = irqtimer_calc(menukey == 1 ? 1500 : 0); ++ printf("\n> "); ++ ++ // Do not restart boot on menukey press, unless DEFAULT_BOOTMENU_WAIT msecs ++ // have passed. Otherwise users (trained by years of repeatedly hitting keys ++ // to enter the BIOS) will end up hitting menukey multiple times and ++ // immediately booting the primary boot device. ++ int esc_accepted_time = irqtimer_calc(DEFAULT_BOOTMENU_WAIT); ++ int choice = 0, kb_choice = 0; ++ int page_num = 1; ++ int enter = 0; ++ int backspace = 0; ++ int tpm_show_menu = 0; + for (;;) { + scan_code = get_keystroke(1000); +- if (scan_code == 1 && !irqtimer_check(esc_accepted_time)) +- continue; +- if (tpm_can_show_menu() && scan_code == 20 /* t */) { ++ if (scan_code == menukey || // custom menukey ++ scan_code == 1 || // ESC ++ scan_code == 43 || // '\' char on keyboard ++ scan_code == 53 || // '/' char on keyboard ++ scan_code == 98) { // '/' char on numpad ++ if (!irqtimer_check(esc_accepted_time)) ++ continue; ++ if (digits == 2) // Remove the decoded "(*)" ++ printf(" \b\b\b"); ++ /* Remove the existing input before printing a message. */ ++ for (; digits > 0; digits--) ++ printf("\b \b"); ++ printf("Menukey pressed.\n"); ++ return; ++ } ++ kb_choice = 0; ++ /* 4 rows of keyboard_keys: 1 row with numbers, 3 rows with letters. ++ Use any of them to select a boot device (except the TPM 'm-' keys) */ ++ // 1st range: 1-9 and 0 (10) keys <==> 2-11 scan codes <==> 1-10 choice ++ if (scan_code >= 2 && scan_code <= 11) kb_choice = scan_code - 1; ++ // 2nd range: Q-P row of letters <==> 16-25 scan codes <==> 11-20 choice ++ if (scan_code >= 16 && scan_code <= 25) kb_choice = scan_code - 5; ++ // 3rd range: A-L row of letters <==> 30-38 scan codes <==> 21-29 choice ++ if (scan_code >= 30 && scan_code <= 38) kb_choice = scan_code - 9; ++ // 4th range: Z-N row of letters <==> 44-49 scan codes <==> 30-35 choice ++ if (scan_code >= 44 && scan_code <= 49) kb_choice = scan_code - 14; ++ // ENTER: (28) on keyboard, (96) on numpad. ++ if (scan_code == 28 || scan_code == 96) ++ enter = 1; ++ // BCKSPC: '<-'(14) and 'Delete'(111) on keyboard, '.Del'(83) on numpad. ++ if (scan_code == 14 || scan_code == 111 || scan_code == 83) ++ backspace = 1; ++ // TPM keys: 'm'(50) and '-'(12) chars on keyboard, '-'(74) on numpad. ++ if ((scan_code == 50 || scan_code == 12 || scan_code == 74) && tpm_cshm) ++ tpm_show_menu = 1; ++ ++ if (kb_choice != 0 || tpm_show_menu) { ++ if (kb_choice > maxmenu) { ++ if (!tpm_show_menu) ++ continue; ++ } else { ++ choice = kb_choice; ++ } ++ if (digits == 2) // Remove the decoded "(*)" ++ printf(" \b\b\b"); ++ /* Remove the existing input before printing a choice. */ ++ for (; digits > 0; digits--) ++ printf("\b \b"); ++ if (!tpm_show_menu) { ++ // Choice is any of the detected boot devices ==> lets boot! ++ break; ++ } ++ } else { ++ // Internal/USB Numpad console interface. ++ if (digits < 9) { ++ for (numpi = 0; numpi < 10; numpi++) { ++ if (scan_code == numpad_scancodes[numpi]) { ++ if (maxmenu <= 10) { // Console interface is not needed. ++ if ((numpi != 0 && numpi <= maxmenu) || ++ (numpi == 0 && 10 <= maxmenu)) { // 10(0) ++ choice = numpi; ++ enter = 1; // Fake ENTER to boot this entry now. ++ } else { // If no such an entry, don't try to boot. ++ break; ++ } ++ } else { ++ if (digits == 2) { ++ printf(" \b\b\b"); // Remove the decoded "(*)" ++ if (choice == 0) { ++ printf("\b\b \b\b"); // Remove "10". ++ digits = 0; ++ } ++ } ++ choice = 10 * choice + numpi; ++ } ++ if (choice > 0) { ++ printf("%d", numpi); // Print the entered digit. ++ digits++; ++ } else { ++ if (10 <= maxmenu) ++ printf("10(0)\b\b\b"); ++ else ++ printf("10(?)\b\b\b"); ++ digits = 2; ++ } ++ if (choice > 9 && digits == 2) // Decode into a letter. ++ decode = 1; ++ break; ++ } ++ } ++ } ++ if (backspace && digits > 0) { ++ backspace = 0; ++ choice = choice / 10; ++ if (digits == 2) { ++ printf(" \b\b\b"); // Remove the decoded "(*)" ++ // 0 turned into 10: one more Backspace is needed to remove. ++ if (choice == 0) { ++ printf("\b \b"); ++ digits--; ++ } ++ } ++ printf("\b \b"); // Remove the last entered digit. ++ digits--; ++ if (choice > 9 && digits == 2) // Decode into a letter. ++ decode = 1; ++ } ++ if (decode) { // Decode the current choice number into a letter. ++ decode = 0; ++ if (choice <= maxmenu) { ++ printf("(%c)", keyboard_keys[choice-1]); ++ } else { ++ if (tpm_cshm && choice == 36) ++ printf("(m)"); // For TPM. ++ else ++ printf("(?)"); // No matching letter found. ++ } ++ printf("\b\b\b"); // Move a cursor before the "(*)" ++ } ++ } ++ ++ if (enter) { ++ enter = 0; ++ if (choice == 0) { ++ if (digits == 2) { // for 0 that turned into 10 ++ if (10 <= maxmenu) ++ break; ++ else ++ continue; ++ } ++ // If there are two pages - switch between them. ++ if (maxmenu > BOOTMENU_PAGE_SIZE) { ++ entry_id = 0; ++ page_num = 3 - page_num; // 3 - 1 = 2; 3 - 2 = 1. ++ printf("\n\nSelect boot device - page %d :" ++ " // press ENTER after your numpad input" ++ " - if any -\n " ++ " // - or to switch between the pages...\n", ++ page_num); ++ hlist_for_each_entry(pos, &BootList, node) { ++ if ((page_num == 1 && entry_id == BOOTMENU_PAGE_SIZE) || ++ (page_num == 2 && entry_id == 35)) ++ break; ++ if (page_num == 1 || entry_id >= BOOTMENU_PAGE_SIZE) ++ printf("%c. %s\n", keyboard_keys[entry_id], ++ strtcpy(desc, pos->description, ARRAY_SIZE(desc))); ++ entry_id++; ++ } ++ if (tpm_cshm) ++ printf("\nm-. TPM Configuration"); ++ printf("\n> "); ++ } ++ } else { ++ if (choice > maxmenu) { ++ if (tpm_cshm && choice == 36) ++ tpm_show_menu = 1; ++ } else { ++ // Choice is any of the detected boot devices ==> lets boot! ++ break; ++ } ++ } ++ } ++ ++ if (tpm_show_menu) { ++ tpm_show_menu = 0; ++ choice = 0; ++ if (digits == 0) ++ printf("TPM key pressed."); ++ else ++ digits = 0; + printf("\n"); + tpm_menu(); ++ printf("> "); + } +- if (scan_code >= 1 && scan_code <= maxmenu+1) +- break; ++ } ++ ++ if (choice == 0) // 10(0) ++ choice = 10; ++ ++ if (digits == 0 && choice < 36) { ++ printf("%c", keyboard_keys[choice-1]); ++ if (choice > 9) // Decode into a number. ++ printf("(%d)", choice); + } + printf("\n"); +- if (scan_code == 0x01) +- // ESC +- return; + + // Find entry and make top priority. +- int choice = scan_code - 1; + hlist_for_each_entry(pos, &BootList, node) { + if (! --choice) + break; +diff --git a/src/config.h b/src/config.h +index 93c8dbc..f85cc14 100644 +--- a/src/config.h ++++ b/src/config.h +@@ -19,7 +19,7 @@ + // Space to reserve in high-memory for tables + #define BUILD_MAX_HIGHTABLE (256*1024) + // Largest supported externaly facing drive id +-#define BUILD_MAX_EXTDRIVE 16 ++#define BUILD_MAX_EXTDRIVE 36 + // Number of bytes the smbios may be and still live in the f-segment + #define BUILD_MAX_SMBIOS_FSEG 600 + // Maximum number of bytes the mptable may be and still be copied to f-segment diff --git a/payloads/external/SeaBIOS/multiple_floppies.patch b/payloads/external/SeaBIOS/multiple_floppies.patch new file mode 100644 index 0000000..5249394 --- /dev/null +++ b/payloads/external/SeaBIOS/multiple_floppies.patch @@ -0,0 +1,207 @@ +diff --git a/src/block.h b/src/block.h +index f64e880..aaa236f 100644 +--- a/src/block.h ++++ b/src/block.h +@@ -2,7 +2,7 @@ + #define __BLOCK_H + + #include "types.h" // u32 +- ++#include "romfile.h" // struct romfile_s + + /**************************************************************** + * Disk command request +@@ -48,6 +48,7 @@ struct drive_s { + struct drive_s { + u8 type; // Driver type (DTYPE_*) + u8 floppy_type; // Type of floppy (only for floppy drives). ++ struct romfile_s *floppy_file; // Floppy file (only for virtual floppies). + struct chs_s lchs; // Logical CHS + u64 sectors; // Total sectors count + u32 cntl_id; // Unique id for a given driver type. +diff --git a/src/boot.c b/src/boot.c +index 9f82f3c..79f1e7d 100644 +--- a/src/boot.c ++++ b/src/boot.c +@@ -584,7 +584,7 @@ bcv_prepboot(void) + break; + case IPL_TYPE_FLOPPY: + map_floppy_drive(pos->drive); +- add_bev(IPL_TYPE_FLOPPY, 0); ++ add_bev(IPL_TYPE_FLOPPY, (u32)pos->drive); + break; + case IPL_TYPE_HARDDISK: + map_hd_drive(pos->drive); +@@ -733,6 +733,12 @@ do_boot(int seq_nr) + static void + do_boot(int seq_nr) + { ++ ++ int ret; ++ void *pos; ++ struct romfile_s *file; ++ struct drive_s *drive; ++ + if (! CONFIG_BOOT) + panic("Boot support not compiled in.\n"); + +@@ -744,6 +750,16 @@ do_boot(int seq_nr) + switch (ie->type) { + case IPL_TYPE_FLOPPY: + printf("Booting from Floppy...\n"); ++ drive = (struct drive_s *)ie->vector; ++ file = drive->floppy_file; ++ // File is NULL if a floppy is physical. ++ if (file) { ++ // Copy virtual floppy image into ram. ++ pos = (void *)drive->cntl_id; ++ ret = file->copy(file, pos, file->size); ++ if (ret < 0) ++ break; ++ } + boot_disk(0x00, CheckFloppySig); + break; + case IPL_TYPE_HARDDISK: +diff --git a/src/hw/floppy.c b/src/hw/floppy.c +index 9e6647d..5b37c6c 100644 +--- a/src/hw/floppy.c ++++ b/src/hw/floppy.c +@@ -107,7 +107,7 @@ struct floppyinfo_s FloppyInfo[] VARFSEG = { + }; + + struct drive_s * +-init_floppy(int floppyid, int ftype) ++init_floppy(int floppyid, int ftype, struct romfile_s *ffile) + { + if (ftype <= 0 || ftype >= ARRAY_SIZE(FloppyInfo)) { + dprintf(1, "Bad floppy type %d\n", ftype); +@@ -124,6 +124,7 @@ init_floppy(int floppyid, int ftype) + drive->type = DTYPE_FLOPPY; + drive->blksize = DISK_SECTOR_SIZE; + drive->floppy_type = ftype; ++ drive->floppy_file = ffile; + drive->sectors = (u64)-1; + + memcpy(&drive->lchs, &FloppyInfo[ftype].chs +@@ -134,7 +135,7 @@ addFloppy(int floppyid, int ftype) + static void + addFloppy(int floppyid, int ftype) + { +- struct drive_s *drive = init_floppy(floppyid, ftype); ++ struct drive_s *drive = init_floppy(floppyid, ftype, 0); + if (!drive) + return; + char *desc = znprintf(MAXDESCSIZE, "Floppy [drive %c]", 'A' + floppyid); +diff --git a/src/hw/ramdisk.c b/src/hw/ramdisk.c +index b9e9baa..a679385 100644 +--- a/src/hw/ramdisk.c ++++ b/src/hw/ramdisk.c +@@ -23,40 +23,69 @@ ramdisk_setup(void) + if (!CONFIG_FLASH_FLOPPY) + return; + +- // Find image. +- struct romfile_s *file = romfile_findprefix("floppyimg/", NULL); +- if (!file) +- return; +- const char *filename = file->name; +- u32 size = file->size; +- dprintf(3, "Found floppy file %s of size %d\n", filename, size); +- int ftype = find_floppy_type(size); +- if (ftype < 0) { +- dprintf(3, "No floppy type found for ramdisk size\n"); ++ struct romfile_s *file = NULL; ++ char *filename, *desc; ++ u32 size, max_size = 0; ++ int ftype; ++ void *pos; ++ struct drive_s *drive; ++ ++ // Find the max floppy size ++ for (;;) { ++ // Find the next image. ++ file = romfile_findprefix("floppyimg/", file); ++ if (!file) ++ break; ++ filename = file->name; ++ size = file->size; ++ dprintf(3, "Found floppy file %s of size %d\n", filename, size); ++ // Check if this size is valid. ++ ftype = find_floppy_type(size); ++ if (ftype < 0) { ++ dprintf(3, "No floppy type found for ramdisk size\n"); ++ } else { ++ if (size > max_size) ++ max_size = size; ++ } ++ } ++ if (max_size == 0) { ++ dprintf(3, "No floppies found\n"); + return; + } + + // Allocate ram for image. +- void *pos = memalign_tmphigh(PAGE_SIZE, size); ++ pos = memalign_tmphigh(PAGE_SIZE, max_size); + if (!pos) { + warn_noalloc(); + return; + } +- e820_add((u32)pos, size, E820_RESERVED); ++ e820_add((u32)pos, max_size, E820_RESERVED); ++ dprintf(3, "Allocate %u bytes for a floppy\n", max_size); + +- // Copy image into ram. +- int ret = file->copy(file, pos, size); +- if (ret < 0) +- return; +- +- // Setup driver. +- struct drive_s *drive = init_floppy((u32)pos, ftype); +- if (!drive) +- return; +- drive->type = DTYPE_RAMDISK; +- dprintf(1, "Mapping floppy %s to addr %p\n", filename, pos); +- char *desc = znprintf(MAXDESCSIZE, "Ramdisk [%s]", &filename[10]); +- boot_add_floppy(drive, desc, bootprio_find_named_rom(filename, 0)); ++ // Setup the floppy drivers. ++ file = NULL; ++ for (;;) { ++ // Find the next image. ++ file = romfile_findprefix("floppyimg/", file); ++ if (!file) ++ return; ++ filename = file->name; ++ size = file->size; ++ dprintf(3, "Found floppy file %s of size %d\n", filename, size); ++ ftype = find_floppy_type(size); ++ if (ftype < 0) { ++ dprintf(3, "No floppy type found for ramdisk size\n"); ++ } else { ++ // Setup driver. ++ drive = init_floppy((u32)pos, ftype, file); ++ if (!drive) ++ return; ++ drive->type = DTYPE_RAMDISK; ++ dprintf(1, "Mapping floppy %s to addr %p\n", filename, pos); ++ desc = znprintf(MAXDESCSIZE, "Ramdisk [%s]", &filename[10]); ++ boot_add_floppy(drive, desc, bootprio_find_named_rom(filename, 0)); ++ } ++ } + } + + static int +diff --git a/src/util.h b/src/util.h +index 9c06850..ce3a26d 100644 +--- a/src/util.h ++++ b/src/util.h +@@ -147,7 +147,8 @@ void dma_setup(void); + // hw/floppy.c + extern struct floppy_ext_dbt_s diskette_param_table2; + void floppy_setup(void); +-struct drive_s *init_floppy(int floppyid, int ftype); ++extern struct romfile_s *ffile; ++struct drive_s *init_floppy(int floppyid, int ftype, struct romfile_s *ffile); + int find_floppy_type(u32 size); + int floppy_process_op(struct disk_op_s *op); + void floppy_tick(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/32351 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idf4efba31091a8678b51c2f6541d440c5cc6d37d Gerrit-Change-Number: 32351 Gerrit-PatchSet: 1 Gerrit-Owner: mikeb mikeb <mikebdp2(a)gmail.com> Gerrit-Reviewer: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: pci: Add support for assigning resources to SR-IOV VF BARs
by Name of user not set (Code Review) May 28, 2025

May 28, 2025

stephend(a)silicom-usa.com has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34620 ) Change subject: pci: Add support for assigning resources to SR-IOV VF BARs ...................................................................... pci: Add support for assigning resources to SR-IOV VF BARs This ensures that bridge windows allocate enough space to cover SR-IOV BARs. Without this Linux will print messages like: pci 0000:03:00.0: BAR 7: no space for [mem size 0x00100000 64bit] pci 0000:03:00.0: BAR 7: failed to assign [mem size 0x00100000 64bit] Tested on Camelback Mountain, and Harcuvar. Change-Id: Ib169efe5a6b998a8342a895f1456a280669c719d Signed-off-by: Stephen Douthit <stephend(a)silicom-usa.com> --- M src/device/pci_device.c M src/device/pciexp_device.c M src/include/device/pci_def.h M src/include/device/pciexp.h 4 files changed, 112 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/34620/1 diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 7786043..c96fc8d 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -439,6 +439,11 @@ { pci_read_bases(dev, 6); pci_get_rom_resource(dev, PCI_ROM_ADDRESS); + +#if CONFIG(PCIEXP_PLUGIN_SUPPORT) + /* Check for SR-IOV BARs if we have PCIe support */ + pciexp_dev_read_resources(dev); +#endif } void pci_bus_read_resources(struct device *dev) diff --git a/src/device/pciexp_device.c b/src/device/pciexp_device.c index c209816..8d660b1 100644 --- a/src/device/pciexp_device.c +++ b/src/device/pciexp_device.c @@ -442,6 +442,82 @@ pciexp_enable_aspm(root, root_cap, dev, cap); } +/* + * Check if this is an SR-IOV capable device and add resources for all VF bars + * + * @param dev Pointer to the dev structure. + */ +void pciexp_dev_read_resources(struct device *dev) +{ + unsigned long sriovpos; + u16 numvfs, i; + + sriovpos = pci_find_capability(dev, PCI_CAP_ID_PCIE); + if (!sriovpos) { + return; + } + + sriovpos = pciexp_find_extended_cap(dev, PCI_EXT_CAP_ID_SRIOV); + if (!sriovpos) { + return; + } + + numvfs = pci_read_config16(dev, sriovpos + PCI_SRIOV_TOT_VFS); + printk(BIOS_DEBUG, "%s: supports %d SR-IOV VFs\n", dev_path(dev), numvfs); + + /* The spec allows this to be 0 for some reason. Nothing to do. */ + if (numvfs == 0) { + return; + } + + for (int off = 0; off < 6; off++) { + unsigned long res_ix = sriovpos + PCI_SRIOV_VFBAR0 + off * 4; + struct resource *resource; + + resource = pci_get_resource(dev, res_ix); + + /* VF BARs aren't necessarily contiguous, skip the unused ones */ + if (resource->size == 0) { + continue; + } + + printk(BIOS_DEBUG, "%s: found %dbit SR-IOV BAR, size 0x%llx @ index %lx\n", + dev_path(dev), (resource->flags & IORESOURCE_PCI64) ? 64 : 32, + resource->size, resource->index); + + if (resource->flags & IORESOURCE_PCI64) { + off++; + } + + /* + * SR-IOV BARs break the resource allocator assumption for PCI + * dev resources that size = gran = alignment. + * + * alignment = gran = pci_get_resource() result, but... + * size is pci_get_resource()->size * numvfs, and there's no + * power of two guarantee on size either since numvfs is just + * an integer. + * + * Rather than add code to handle this as a special case in the + * resource allocator, just round up the size. In practice + * MaxVfs tends to be 2^n or 2^n - 1, so the holes produced + * should only be the size of a single VF BAR + */ + for (i = 1; i < numvfs; i <<= 1) { + resource->size <<= 1; + resource->align += 1; + resource->gran += 1; + } + + if (i != numvfs) { + printk(BIOS_DEBUG, "%s: VFs != 2^n, wasting MMIO space...\n", + dev_path(dev)); + } + } + + compact_resources(dev); +} + void pciexp_scan_bus(struct bus *bus, unsigned int min_devfn, unsigned int max_devfn) { diff --git a/src/include/device/pci_def.h b/src/include/device/pci_def.h index bc5bc79..39a6137 100644 --- a/src/include/device/pci_def.h +++ b/src/include/device/pci_def.h @@ -453,6 +453,7 @@ #define PCI_EXT_CAP_ID_VC 2 #define PCI_EXT_CAP_ID_DSN 3 #define PCI_EXT_CAP_ID_PWR 4 +#define PCI_EXT_CAP_ID_SRIOV 0x0010 /* Extended Capability lists*/ #define PCIE_EXT_CAP_OFFSET 0x100 @@ -518,6 +519,34 @@ #define PCI_PWR_CAP 12 /* Capability */ #define PCI_PWR_CAP_BUDGET(x) ((x) & 1) /* Included in system budget */ +/* SR-IOV */ +#define PCI_SRIOV_CAPS 0x04 /* SR-IOV capabilities */ +#define PCI_SRIOV_VF_MIG (1 << 0) /* VF Migration capable */ +#define PCI_SRIOV_ARI_CAP (1 << 1) /* ARI Capable Hierarchy Preserved */ +#define PCI_SRIOV_MIG_INT(x) (((x) >> 21) & 0x7ff) +#define PCI_SRIOV_CTRL 0x08 /* SR-IOV Control */ +#define PCI_SRIOV_VF_EN (1 << 0) +#define PCI_SRIOV_MIG_EN (1 << 1) +#define PCI_SRIOV_MIG_INT_EN (1 << 2) +#define PCI_SRIOV_MSE (1 << 3) +#define PCI_SRIOV_ARI_CAP_EN (1 << 4) +#define PCI_SRIOV_STATUS 0x0A /* SR-IOV Status */ +#define PCI_SRIOV_INIT_VFS 0x0C +#define PCI_SRIOV_TOT_VFS 0x0E +#define PCI_SRIOV_NUM_VFS 0x10 +#define PCI_SRIOV_FN_DEP_LINK 0x12 +#define PCI_SRIOV_VF_OFF 0x14 +#define PCI_SRIOV_VF_STRIDE 0x16 +#define PCI_SRIOV_VF_DEVID 0x1A +#define PCI_SRIOV_SUP_PAGE_SIZE 0x1C +#define PCI_SRIOV_PAGE_SIZE 0x20 +#define PCI_SRIOV_VFBAR0 0x24 +#define PCI_SRIOV_VFBAR1 0x28 +#define PCI_SRIOV_VFBAR2 0x2C +#define PCI_SRIOV_VFBAR3 0x30 +#define PCI_SRIOV_VFBAR4 0x34 +#define PCI_SRIOV_VFBAR5 0x38 +#define PCI_SRIOV_MIG_ARRAY 0x3C /* * The PCI interface treats multi-function devices as independent diff --git a/src/include/device/pciexp.h b/src/include/device/pciexp.h index 3a9825d..94a80bf 100644 --- a/src/include/device/pciexp.h +++ b/src/include/device/pciexp.h @@ -19,6 +19,8 @@ /* Latency tolerance reporting, max snoop latency value 3.14ms */ #define PCIE_LTR_MAX_SNOOP_LATENCY_3146US 0x1003 +void pciexp_dev_read_resources(struct device *dev); + void pciexp_scan_bus(struct bus *bus, unsigned int min_devfn, unsigned int max_devfn); -- To view, visit https://review.coreboot.org/c/coreboot/+/34620 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib169efe5a6b998a8342a895f1456a280669c719d Gerrit-Change-Number: 34620 Gerrit-PatchSet: 1 Gerrit-Owner: stephend(a)silicom-usa.com Gerrit-MessageType: newchange

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