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Change subject: superio/fintek/f81866d: Fix UART numbers
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Patch Set 1: Code-Review+2
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Change subject: SNB/BD82x6x boards: Remove old USB configurations
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Patch Set 2:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/81882/comment/b6e704b8_63af6248 :
PS2, Line 7: SNB/BD82x6x boards:
Maybe (to start with lowercase letter):
> mb: SNB/BD82x6x: …
https://review.coreboot.org/c/coreboot/+/81882/comment/306eb605_4914a61d :
PS2, Line 13:
It’d be great if you documented the boards, the tested boards.
Patchset:
PS2:
Great work. Thank you.
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Change subject: acpigen_ps2_keybd: Add support for dictation key
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Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/81863/comment/d4ccee89_c108e16f :
PS2, Line 14: Flash DUT that emits a scancode for a dictation key, verify that it
: is mapped to KEY_DICTATE in the Linux kernel.
Next time, it’d be great if you also documented your comments, so it’s easier for people to reproduce. (I guess `evtest` or `libinput` was used.)
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Change subject: soc/intel/common: Add Lunar Lake CNVI device IDs
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Patch Set 3:
(1 comment)
File src/soc/intel/common/block/cnvi/cnvi.c:
https://review.coreboot.org/c/coreboot/+/81846/comment/dbac843f_8291cf3f :
PS2, Line 27: PCI_DID_INTEL_LNL_CNVI_WIFI_3,
> > `please, no spaces at the start of a line` […]
ACK.
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Change subject: soc/intel/lunarlake: Support stepping A0_2
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Patch Set 3:
(7 comments)
Commit Message:
PS2:
> Just reading the commit message, I would have thought the diff to be different. […]
ACK.
https://review.coreboot.org/c/coreboot/+/81847/comment/65f610c2_13ccac2a :
PS2, Line 7: soc/intel/{common, lunarlake}: Add support for new MCH
> The prefix does not need to be the path. Maybe: […]
ACK.
https://review.coreboot.org/c/coreboot/+/81847/comment/e5d58c9b_8d3c6883 :
PS2, Line 10: (ID:0x6410)
> I’d write: … with id 0x640 […]
Done
https://review.coreboot.org/c/coreboot/+/81847/comment/8cb5fe71_10f971db :
PS2, Line 10: The patch adds
> “The patch” is redundant [1]. Just use the imperative mood: […]
ACK.
https://review.coreboot.org/c/coreboot/+/81847/comment/f233c9b8_1a1eb884 :
PS2, Line 11: Add new CPU ID (ID:0xb06d1)
> Add new CPU id 0xb06d1
ACK.
https://review.coreboot.org/c/coreboot/+/81847/comment/97d6153c_7d410f6e :
PS2, Line 16: TEST=Build and boot the system having MCH ID:0x6410.
> Which log line is that?
Updated.
File src/include/device/pci_ids.h:
https://review.coreboot.org/c/coreboot/+/81847/comment/bf42278b_611aded1 :
PS2, Line 4292: #define PCI_DID_INTEL_LNL_M_ID_1 0x6410
> Name the above …1, and this one _2 for alignment reasons?
ACK.
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