coreboot-gerrit March 2024

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[XS] Change in coreboot[main]: soc/intel/xeon_sp: Add utils to detect domain0 and stack0
by Lean Sheng Tan (Code Review) 14 Mar '24

14 Mar '24

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81199?usp=email ) ( 5 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/intel/xeon_sp: Add utils to detect domain0 and stack0 ...................................................................... soc/intel/xeon_sp: Add utils to detect domain0 and stack0 In Xeon-SP, the domain0, which is located at stack0, usually needs special handling due to the compatible devices on it (HEPT, IO-APIC and legacy IOs). This patch adds util function detect whether a give domain or stack is with such a role. TEST=intel/archercity CRB Change-Id: I2f26b4ac54091c24c554f17964502c364288aa40 Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81199 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/intel/xeon_sp/chip_common.c M src/soc/intel/xeon_sp/include/soc/chip_common.h 2 files changed, 6 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved diff --git a/src/soc/intel/xeon_sp/chip_common.c b/src/soc/intel/xeon_sp/chip_common.c index d0e01bc..ef504d7 100644 --- a/src/soc/intel/xeon_sp/chip_common.c +++ b/src/soc/intel/xeon_sp/chip_common.c @@ -199,7 +199,7 @@ int index = 0; - if (dev->path.domain.domain == 0) { + if (is_domain0(dev)) { /* The 0 - 0xfff IO range is not reported by the HOB but still gets decoded */ res = new_resource(dev, index++); res->base = 0; diff --git a/src/soc/intel/xeon_sp/include/soc/chip_common.h b/src/soc/intel/xeon_sp/include/soc/chip_common.h index 40c7ffa..53deffa 100644 --- a/src/soc/intel/xeon_sp/include/soc/chip_common.h +++ b/src/soc/intel/xeon_sp/include/soc/chip_common.h @@ -77,4 +77,9 @@ #define is_dev_on_ubox_domain(dev) is_ubox_domain(dev_get_pci_domain(dev)) #define is_dev_on_cxl_domain(dev) is_cxl_domain(dev_get_pci_domain(dev)) +#define is_domain0(dev) (dev && dev->path.type == DEVICE_PATH_DOMAIN &&\ + dev->path.domain.domain == 0) +#define is_dev_on_domain0(dev) (is_domain0(dev_get_pci_domain(dev))) +#define is_stack0(socket, stack) (socket == 0 && stack == IioStack0) + #endif /* _CHIP_COMMON_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/81199?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2f26b4ac54091c24c554f17964502c364288aa40 Gerrit-Change-Number: 81199 Gerrit-PatchSet: 7 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: soc/intel/xeon_sp: Add domain role checking utils
by Lean Sheng Tan (Code Review) 14 Mar '24

14 Mar '24

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81046?usp=email ) ( 14 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/intel/xeon_sp: Add domain role checking utils ...................................................................... soc/intel/xeon_sp: Add domain role checking utils For Xeon-SP, there are 4 main domain roles (PCIe/CXL/IOAT/UBOX). This patch adds util function to check whether a given domain belongs to one of these roles, or a give device belongs to a domain of the specific role. TEST=intel/archercity CRB Change-Id: I6b31c29564c774c27e86f55749ca9eca057a0cfe Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81046 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/intel/xeon_sp/chip_common.c M src/soc/intel/xeon_sp/include/soc/chip_common.h 2 files changed, 49 insertions(+), 0 deletions(-) Approvals: Patrick Rudolph: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/intel/xeon_sp/chip_common.c b/src/soc/intel/xeon_sp/chip_common.c index b461f0e..d0e01bc 100644 --- a/src/soc/intel/xeon_sp/chip_common.c +++ b/src/soc/intel/xeon_sp/chip_common.c @@ -400,3 +400,41 @@ } } } + +bool is_pcie_domain(struct device *dev) +{ + if ((!dev) || (dev->path.type != DEVICE_PATH_DOMAIN)) + return false; + + return strstr(dev->name, DOMAIN_TYPE_PCIE); +} + +bool is_ioat_domain(struct device *dev) +{ + if ((!dev) || (dev->path.type != DEVICE_PATH_DOMAIN)) + return false; + + return (strstr(dev->name, DOMAIN_TYPE_CPM0) || + strstr(dev->name, DOMAIN_TYPE_CPM1) || + strstr(dev->name, DOMAIN_TYPE_DINO) || + strstr(dev->name, DOMAIN_TYPE_HQM0) || + strstr(dev->name, DOMAIN_TYPE_HQM1)); +} + +bool is_ubox_domain(struct device *dev) +{ + if ((!dev) || (dev->path.type != DEVICE_PATH_DOMAIN)) + return false; + + return (strstr(dev->name, DOMAIN_TYPE_UBX0) || + strstr(dev->name, DOMAIN_TYPE_UBX1)); + +} + +bool is_cxl_domain(struct device *dev) +{ + if ((!dev) || (dev->path.type != DEVICE_PATH_DOMAIN)) + return false; + + return strstr(dev->name, DOMAIN_TYPE_CXL); +} diff --git a/src/soc/intel/xeon_sp/include/soc/chip_common.h b/src/soc/intel/xeon_sp/include/soc/chip_common.h index 4dae550..40c7ffa 100644 --- a/src/soc/intel/xeon_sp/include/soc/chip_common.h +++ b/src/soc/intel/xeon_sp/include/soc/chip_common.h @@ -3,6 +3,7 @@ #ifndef _CHIP_COMMON_H_ #define _CHIP_COMMON_H_ +#include <device/device.h> #include <device/path.h> #include <hob_iiouds.h> @@ -66,4 +67,14 @@ int iio_pci_domain_socket_from_dev(struct device *dev); int iio_pci_domain_stack_from_dev(struct device *dev); +bool is_pcie_domain(struct device *dev); +bool is_ioat_domain(struct device *dev); +bool is_ubox_domain(struct device *dev); +bool is_cxl_domain(struct device *dev); + +#define is_dev_on_pcie_domain(dev) is_pcie_domain(dev_get_pci_domain(dev)) +#define is_dev_on_ioat_domain(dev) is_ioat_domain(dev_get_pci_domain(dev)) +#define is_dev_on_ubox_domain(dev) is_ubox_domain(dev_get_pci_domain(dev)) +#define is_dev_on_cxl_domain(dev) is_cxl_domain(dev_get_pci_domain(dev)) + #endif /* _CHIP_COMMON_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/81046?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6b31c29564c774c27e86f55749ca9eca057a0cfe Gerrit-Change-Number: 81046 Gerrit-PatchSet: 16 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: mb/google/brox: Select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS
by Shelley Chen (Code Review) 14 Mar '24

14 Mar '24

Attention is currently required from: Ashish Kumar Mishra, Karthik Ramasubramanian. Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81224?usp=email ) Change subject: mb/google/brox: Select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > No change required. So I tried applying this patch and was still getting failures on suspend_stress_test. I was never able to successfully getting through a call to `suspend_stress_test -c 10`. Is Intel seeing any suspend failures with this fix? Although it does seem like it's an EC interrupt that is causing the premature wake. -- To view, visit https://review.coreboot.org/c/coreboot/+/81224?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iabd0b3a83aa386e09310b671632368807a4018d4 Gerrit-Change-Number: 81224 Gerrit-PatchSet: 2 Gerrit-Owner: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Thu, 14 Mar 2024 18:57:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Shelley Chen <shchen(a)google.com> Comment-In-Reply-To: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: soc/intel/xeon_sp/uncore_acpi: Fix debug print
by Lean Sheng Tan (Code Review) 14 Mar '24

14 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Patrick Rudolph, Shuo Liu, Tim Chu. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81186?usp=email ) Change subject: soc/intel/xeon_sp/uncore_acpi: Fix debug print ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: This patch needs manual rebase -- To view, visit https://review.coreboot.org/c/coreboot/+/81186?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I009fbfb9f9d62855d351c5db2d3d88722b5dbfa2 Gerrit-Change-Number: 81186 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Thu, 14 Mar 2024 18:57:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[L] Change in coreboot[main]: soc/intel/xeon_sp: Use common _CRS code generation
by Lean Sheng Tan (Code Review) 14 Mar '24

14 Mar '24

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80796?usp=email ) Change subject: soc/intel/xeon_sp: Use common _CRS code generation ...................................................................... soc/intel/xeon_sp: Use common _CRS code generation Drop SoC specific code and use generic implementation provided by pci_domain_fill_ssdt. TEST=Booted on IBM/SBP1 to Ubuntu 22.04. TEST=intel/archercity CRB Change-Id: I8b0bc2eb02569b5d74f8521d79e0af8fee880c80 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80796 Reviewed-by: Shuo Liu <shuo.liu(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> --- M src/soc/intel/xeon_sp/chip_common.c M src/soc/intel/xeon_sp/cpx/chip.c M src/soc/intel/xeon_sp/cpx/soc_acpi.c M src/soc/intel/xeon_sp/skx/chip.c M src/soc/intel/xeon_sp/skx/soc_acpi.c M src/soc/intel/xeon_sp/spr/chip.c M src/soc/intel/xeon_sp/spr/ioat.c M src/soc/intel/xeon_sp/spr/soc_acpi.c 8 files changed, 13 insertions(+), 424 deletions(-) Approvals: build bot (Jenkins): Verified Shuo Liu: Looks good to me, approved Lean Sheng Tan: Looks good to me, approved diff --git a/src/soc/intel/xeon_sp/chip_common.c b/src/soc/intel/xeon_sp/chip_common.c index 853b6bf..b461f0e 100644 --- a/src/soc/intel/xeon_sp/chip_common.c +++ b/src/soc/intel/xeon_sp/chip_common.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ +#include <acpi/acpigen_pci.h> #include <assert.h> #include <console/console.h> #include <device/pci.h> @@ -243,6 +244,7 @@ #if CONFIG(HAVE_ACPI_TABLES) .acpi_name = soc_acpi_name, .write_acpi_tables = northbridge_write_acpi_tables, + .acpi_fill_ssdt = pci_domain_fill_ssdt, #endif }; @@ -257,6 +259,7 @@ #if CONFIG(HAVE_ACPI_TABLES) .acpi_name = soc_acpi_name, .write_acpi_tables = northbridge_write_acpi_tables, + .acpi_fill_ssdt = pci_domain_fill_ssdt, #endif }; @@ -348,6 +351,7 @@ #if CONFIG(HAVE_ACPI_TABLES) .acpi_name = soc_acpi_name, .write_acpi_tables = northbridge_write_acpi_tables, + .acpi_fill_ssdt = pci_domain_fill_ssdt, #endif }; diff --git a/src/soc/intel/xeon_sp/cpx/chip.c b/src/soc/intel/xeon_sp/cpx/chip.c index 8a828c6..1fc9c75 100644 --- a/src/soc/intel/xeon_sp/cpx/chip.c +++ b/src/soc/intel/xeon_sp/cpx/chip.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ - +#include <acpi/acpigen_pci.h> #include <arch/ioapic.h> #include <console/console.h> #include <console/debug.h> diff --git a/src/soc/intel/xeon_sp/cpx/soc_acpi.c b/src/soc/intel/xeon_sp/cpx/soc_acpi.c index 8b24ba2..b2d6d79 100644 --- a/src/soc/intel/xeon_sp/cpx/soc_acpi.c +++ b/src/soc/intel/xeon_sp/cpx/soc_acpi.c @@ -43,72 +43,6 @@ void uncore_fill_ssdt(const struct device *device) { - struct iiostack_resource stack_info = {0}; - - /* Only add RTxx entries once. */ - if (device->upstream->secondary != 0 || device->upstream->segment_group != 0) - return; - - get_iiostack_info(&stack_info); - - for (uint8_t stack = 0; stack < stack_info.no_of_stacks; ++stack) { - const STACK_RES *ri = &stack_info.res[stack]; - char rtname[16]; - - snprintf(rtname, sizeof(rtname), "\\_SB.PC%02x", stack); - acpigen_write_scope(rtname); - - acpigen_write_name("_CRS"); - printk(BIOS_DEBUG, "\tCreating ResourceTemplate %s for stack: %d\n", - rtname, stack); - - acpigen_write_resourcetemplate_header(); - - /* bus resource */ - acpigen_resource_word(2, 0xc, 0, 0, ri->BusBase, ri->BusLimit, - 0x0, (ri->BusLimit - ri->BusBase + 1)); - - /* additional io resources on socket 0 bus 0 */ - if (stack == 0) { - /* ACPI 6.4.2.5 I/O Port Descriptor */ - acpigen_write_io16(0xCF8, 0xCFF, 0x1, 0x8, 1); - - /* IO decode CF8-CFF */ - acpigen_resource_word(1, 0xc, 0x3, 0, 0x0000, 0x03AF, 0, 0x03B0); - acpigen_resource_word(1, 0xc, 0x3, 0, 0x03E0, 0x0CF7, 0, 0x0918); - acpigen_resource_word(1, 0xc, 0x3, 0, 0x03B0, 0x03BB, 0, 0x000C); - acpigen_resource_word(1, 0xc, 0x3, 0, 0x03C0, 0x03DF, 0, 0x0020); - } - - /* IO resource */ - acpigen_resource_word(1, 0xc, 0x3, 0, ri->PciResourceIoBase, - ri->PciResourceIoLimit, 0x0, - (ri->PciResourceIoLimit - ri->PciResourceIoBase + 1)); - - /* additional mem32 resources on socket 0 bus 0 */ - if (stack == 0) { - acpigen_resource_dword(0, 0xc, 3, 0, VGA_MMIO_BASE, - VGA_MMIO_LIMIT, 0x0, VGA_MMIO_SIZE); - acpigen_resource_dword(0, 0xc, 1, 0, SPI_BASE_ADDRESS, - (SPI_BASE_ADDRESS + SPI_BASE_SIZE - 1), 0x0, - SPI_BASE_SIZE); - } - - /* Mem32 resource */ - acpigen_resource_dword(0, 0xc, 1, 0, ri->PciResourceMem32Base, - ri->PciResourceMem32Limit, 0x0, - (ri->PciResourceMem32Limit - ri->PciResourceMem32Base + 1)); - - /* Mem64 resource */ - acpigen_resource_qword(0, 0xc, 1, 0, ri->PciResourceMem64Base, - ri->PciResourceMem64Limit, 0x0, - (ri->PciResourceMem64Limit - ri->PciResourceMem64Base + 1)); - - acpigen_write_resourcetemplate_footer(); - - /* Scope */ - acpigen_pop_len(); - } } /* TODO: See if we can use the common generate_p_state_entries */ diff --git a/src/soc/intel/xeon_sp/skx/chip.c b/src/soc/intel/xeon_sp/skx/chip.c index 1911e06..d8b3161 100644 --- a/src/soc/intel/xeon_sp/skx/chip.c +++ b/src/soc/intel/xeon_sp/skx/chip.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ - +#include <acpi/acpigen_pci.h> #include <cbfs.h> #include <console/console.h> #include <device/pci.h> diff --git a/src/soc/intel/xeon_sp/skx/soc_acpi.c b/src/soc/intel/xeon_sp/skx/soc_acpi.c index 2e2b14a..b98e998 100644 --- a/src/soc/intel/xeon_sp/skx/soc_acpi.c +++ b/src/soc/intel/xeon_sp/skx/soc_acpi.c @@ -56,82 +56,6 @@ void uncore_fill_ssdt(const struct device *device) { - const IIO_UDS *hob = get_iio_uds(); - - /* Only add RTxx entries once. */ - if (device->upstream->secondary != 0) - return; - - for (int socket = 0, iio = 0; iio < hob->PlatformData.numofIIO; ++socket) { - if (!soc_cpu_is_enabled(socket)) - continue; - iio++; - IIO_RESOURCE_INSTANCE iio_resource = - hob->PlatformData.IIO_resource[socket]; - for (int stack = 0; stack <= PSTACK2; ++stack) { - const STACK_RES *ri = &iio_resource.StackRes[stack]; - char rtname[16]; - - snprintf(rtname, sizeof(rtname), "\\_SB.PC%02x", socket * MAX_IIO_STACK + stack); - acpigen_write_scope(rtname); - - acpigen_write_name("_CRS"); - - printk(BIOS_DEBUG, "\tCreating ResourceTemplate %s for socket: %d, stack: %d\n", - rtname, socket, stack); - - acpigen_write_resourcetemplate_header(); - - /* bus resource */ - acpigen_resource_word(2, 0xc, 0, 0, ri->BusBase, ri->BusLimit, - 0x0, (ri->BusLimit - ri->BusBase + 1)); - - // additional io resources on socket 0 bus 0 - if (socket == 0 && stack == 0) { - /* ACPI 6.4.2.5 I/O Port Descriptor */ - acpigen_write_io16(0xCF8, 0xCFF, 0x1, 0x8, 1); - - /* IO decode CF8-CFF */ - acpigen_resource_word(1, 0xc, 0x3, 0, 0x0000, 0x03AF, - 0, 0x03B0); - acpigen_resource_word(1, 0xc, 0x3, 0, 0x03E0, 0x0CF7, - 0, 0x0918); - acpigen_resource_word(1, 0xc, 0x3, 0, 0x03B0, 0x03BB, - 0, 0x000C); - acpigen_resource_word(1, 0xc, 0x3, 0, 0x03C0, 0x03DF, - 0, 0x0020); - } - - /* IO resource */ - acpigen_resource_word(1, 0xc, 0x3, 0, ri->PciResourceIoBase, - ri->PciResourceIoLimit, 0x0, - (ri->PciResourceIoLimit - ri->PciResourceIoBase + 1)); - - // additional mem32 resources on socket 0 bus 0 - if (socket == 0 && stack == 0) { - acpigen_resource_dword(0, 0xc, 3, 0, VGA_MMIO_BASE, - VGA_MMIO_LIMIT, 0x0, VGA_MMIO_SIZE); - acpigen_resource_dword(0, 0xc, 1, 0, SPI_BASE_ADDRESS, - (SPI_BASE_ADDRESS + SPI_BASE_SIZE - 1), 0x0, - SPI_BASE_SIZE); - } - - /* Mem32 resource */ - acpigen_resource_dword(0, 0xc, 1, 0, ri->PciResourceMem32Base, - ri->PciResourceMem32Limit, 0x0, - (ri->PciResourceMem32Limit - ri->PciResourceMem32Base + 1)); - - /* Mem64 resource */ - acpigen_resource_qword(0, 0xc, 1, 0, ri->PciResourceMem64Base, - ri->PciResourceMem64Limit, 0x0, - (ri->PciResourceMem64Limit - ri->PciResourceMem64Base + 1)); - - acpigen_write_resourcetemplate_footer(); - - /* Scope */ - acpigen_pop_len(); - } - } } void soc_power_states_generation(int core, int cores_per_package) diff --git a/src/soc/intel/xeon_sp/spr/chip.c b/src/soc/intel/xeon_sp/spr/chip.c index a9387f4..7b934ba 100644 --- a/src/soc/intel/xeon_sp/spr/chip.c +++ b/src/soc/intel/xeon_sp/spr/chip.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ - +#include <acpi/acpigen_pci.h> #include <arch/ioapic.h> #include <console/console.h> #include <console/debug.h> diff --git a/src/soc/intel/xeon_sp/spr/ioat.c b/src/soc/intel/xeon_sp/spr/ioat.c index 2b6aafa..2e3baa3 100644 --- a/src/soc/intel/xeon_sp/spr/ioat.c +++ b/src/soc/intel/xeon_sp/spr/ioat.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ - +#include <acpi/acpigen_pci.h> #include <stdbool.h> #include <console/console.h> @@ -26,6 +26,7 @@ #if CONFIG(HAVE_ACPI_TABLES) .acpi_name = soc_acpi_name, .write_acpi_tables = northbridge_write_acpi_tables, + .acpi_fill_ssdt = pci_domain_fill_ssdt, #endif }; diff --git a/src/soc/intel/xeon_sp/spr/soc_acpi.c b/src/soc/intel/xeon_sp/spr/soc_acpi.c index ca1cdf9..0b6e491 100644 --- a/src/soc/intel/xeon_sp/spr/soc_acpi.c +++ b/src/soc/intel/xeon_sp/spr/soc_acpi.c @@ -53,279 +53,11 @@ fill_fadt_extended_pm_io(fadt); } -static void create_dsdt_iou_pci_resource(uint8_t socket, uint8_t stack, const STACK_RES *ri, - bool stack_enabled) -{ - /* - Stacks 0 (TYPE_UBOX_IIO) - Scope: PC<socket><stack>, ResourceTemplate: P0RS - Stacks 1 .. 5 (TYPE_UBOX_IIO) - Scope: PC<socket><stack>, ResourceTemplate: RBRS - */ - /* write _CRS scope */ - char tres[16]; - snprintf(tres, sizeof(tres), "\\_SB.PC%d%X", socket, stack); - acpigen_write_scope(tres); - acpigen_write_name("_CRS"); - - printk(BIOS_DEBUG, "\tCreating ResourceTemplate %s for socket: %d, stack: %d\n", tres, - socket, stack); - - acpigen_write_resourcetemplate_header(); - - /* Bus Resource */ - if (stack_enabled) { - /* For stack with CXL device, the PCIe bus resource is BusBase only. */ - if (is_iio_cxl_stack_res(ri)) - acpigen_resource_word(2, 0xc, 0, 0, ri->BusBase, ri->BusBase, 0x0, 1); - else - acpigen_resource_word(2, 0xc, 0, 0, ri->BusBase, ri->BusLimit, 0x0, - (ri->BusLimit - ri->BusBase + 1)); - } else { - acpigen_resource_word(2, 0, 0, 0, 0, 0, 0, 0); - } - - /* Additional IO resources on socket 0 bus 0 */ - if (socket == 0 && stack == 0) { - /* ACPI 6.4.2.5 I/O Port Descriptor */ - acpigen_write_io16(0xCF8, 0xCFF, 0x1, 0x8, 1); - - /* IO decode CF8-CFF */ - acpigen_resource_word(1, 0xc, 0x3, 0, 0x0000, 0x03AF, 0, 0x03B0); - acpigen_resource_word(1, 0xc, 0x3, 0, 0x03E0, 0x0CF7, 0, 0x0918); - acpigen_resource_word(1, 0xc, 0x3, 0, 0x03B0, 0x03BB, 0, 0x000C); - acpigen_resource_word(1, 0xc, 0x3, 0, 0x03C0, 0x03DF, 0, 0x0020); - } - - /* IO resource */ - if (stack_enabled) { - acpigen_resource_word(1, 0xc, 0x3, 0, ri->PciResourceIoBase, - ri->PciResourceIoLimit, 0x0, - (ri->PciResourceIoLimit - ri->PciResourceIoBase + 1)); - - /* Additional Mem32 resources on socket 0 bus 0 */ - if (socket == 0 && stack == 0) { - acpigen_resource_dword(0, 0xc, 3, 0, VGA_MMIO_BASE, - VGA_MMIO_LIMIT, 0x0, VGA_MMIO_SIZE); - acpigen_resource_dword(0, 0xc, 1, 0, SPI_BASE_ADDRESS, - (SPI_BASE_ADDRESS + SPI_BASE_SIZE - 1), 0x0, - SPI_BASE_SIZE); - } - - /* Mem32 resource */ - acpigen_resource_dword( - 0, 0xc, 1, 0, ri->PciResourceMem32Base, ri->PciResourceMem32Limit, 0x0, - (ri->PciResourceMem32Limit - ri->PciResourceMem32Base + 1)); - - /* Mem64 resource */ - acpigen_resource_qword( - 0, 0xc, 1, 0, ri->PciResourceMem64Base, ri->PciResourceMem64Limit, 0x0, - (ri->PciResourceMem64Limit - ri->PciResourceMem64Base + 1)); - } else { - /* Zeroed IO resource */ - acpigen_resource_word(1, 0, 3, 0, 0, 0, 0, 0); - - /* Zeroed Mem32 resource */ - acpigen_resource_dword(0, 0, 1, 0, 0, 0, 0, 0); - - /* Zeroed Mem64 resource */ - acpigen_resource_dword(0, 0, 1, 0, 0, 0, 0, 0); - } - - acpigen_write_resourcetemplate_footer(); - acpigen_pop_len(); -} - -static void create_dsdt_iou_cxl_resource(uint8_t socket, uint8_t stack, const STACK_RES *ri, bool stack_enabled) -{ - /* - Stacks 1 .. 5 (TYPE_UBOX_IIO) - Scope: CX<socket><stack>, ResourceTemplate: RBRS - */ - /* write _CRS scope */ - char tres[16]; - snprintf(tres, sizeof(tres), "\\_SB.CX%d%X", socket, stack); - acpigen_write_scope(tres); - acpigen_write_name("_CRS"); - - printk(BIOS_DEBUG, "\tCreating ResourceTemplate %s for socket: %d, stack: %d\n", tres, - socket, stack); - - acpigen_write_resourcetemplate_header(); - - if (stack_enabled) { - /* bus resource, from (BusBase + 1) to BusLimit */ - acpigen_resource_word(2, 0xc, 0, 0, ri->BusBase + 1, ri->BusLimit, 0x0, - (ri->BusLimit - ri->BusBase)); - - /* IO resource */ - acpigen_resource_word(1, 0xc, 0x3, 0, ri->IoBase, ri->PciResourceIoBase - 1, - 0x0, ri->PciResourceIoBase - ri->IoBase); - - /* Mem32 resource */ - acpigen_resource_dword(0, 0xc, 1, 0, ri->Mmio32Base, - ri->PciResourceMem32Base - 1, 0x0, - ri->PciResourceMem32Base - ri->Mmio32Base); - - /* Mem64 resource */ - acpigen_resource_qword(0, 0xc, 1, 0, ri->Mmio64Base, - ri->PciResourceMem64Base - 1, 0x0, - ri->PciResourceMem64Base - ri->Mmio64Base); - } else { - /* bus resource, from (BusBase + 1) to BusLimit */ - acpigen_resource_word(2, 0, 0, 0, 0, 0, 0, 0); - - /* IO resource */ - acpigen_resource_word(1, 0, 3, 0, 0, 0, 0, 0); - - /* Mem32 resource */ - acpigen_resource_dword(0, 0, 1, 0, 0, 0, 0, 0); - - /* Mem64 resource */ - acpigen_resource_qword(0, 0, 1, 0, 0, 0, 0, 0); - } - - acpigen_write_resourcetemplate_footer(); - acpigen_pop_len(); -} - -static void create_dsdt_ioat_resource(uint8_t socket, uint8_t stack, const STACK_RES *ri, bool stack_enabled) -{ - if (!stack_enabled) - return; - - /* - Stacks 8 .. B (TYPE_DINO) - Scope: DI<socket><stack> for DINO, ResourceTemplate: DT - Scope: CP<socket><stack> for CPM (i.e., QAT), ResourceTemplate: MT - Scope: HQ<socket><stack> for HQM (i.e., DLB), ResourceTemplate: HT - */ - - enum { - DSDT_DINO = 0, - DSDT_CPM, - DSDT_HQM, - DSDT_CPM1, - DSDT_HQM1 - }; - uint8_t rlist[] = {DSDT_DINO, DSDT_CPM, DSDT_HQM, DSDT_CPM1, DSDT_HQM1}; - - for (int i = 0; i < ARRAY_SIZE(rlist); ++i) { - uint8_t bus_base, bus_limit; - uint64_t mem64_base, mem64_limit; - char tres[16]; - - /* Note, This allocates the resources in a different order than - * coreboot (DINO base is last). This causes the kernel to - * reallocate the DINO BARs. - * TODO: Use the resource settings from coreboot */ - if (rlist[i] == DSDT_DINO) { - bus_base = ri->BusBase; - bus_limit = ri->BusBase; - mem64_base = ri->PciResourceMem64Base + CPM_MMIO_SIZE + HQM_MMIO_SIZE - + CPM_MMIO_SIZE + HQM_MMIO_SIZE; - mem64_limit = ri->PciResourceMem64Limit; - snprintf(tres, sizeof(tres), "\\_SB.DI%d%X", socket, stack); - } else if (rlist[i] == DSDT_CPM) { - bus_base = ri->BusBase + CPM_BUS_OFFSET; - bus_limit = bus_base + CPM_RESERVED_BUS; - mem64_base = ri->PciResourceMem64Base; - mem64_limit = mem64_base + CPM_MMIO_SIZE - 1; - snprintf(tres, sizeof(tres), "\\_SB.PM%d%X", socket, stack); - } else if (rlist[i] == DSDT_HQM) { - bus_base = ri->BusBase + HQM_BUS_OFFSET; - bus_limit = bus_base + HQM_RESERVED_BUS; - mem64_base = ri->PciResourceMem64Base + CPM_MMIO_SIZE; - mem64_limit = mem64_base + HQM_MMIO_SIZE - 1; - snprintf(tres, sizeof(tres), "\\_SB.HQ%d%X", socket, stack); - } else if (rlist[i] == DSDT_CPM1) { - bus_base = ri->BusBase + CPM1_BUS_OFFSET; - bus_limit = bus_base + CPM_RESERVED_BUS; - mem64_base = ri->PciResourceMem64Base + CPM_MMIO_SIZE + HQM_MMIO_SIZE; - mem64_limit = mem64_base + CPM_MMIO_SIZE - 1; - snprintf(tres, sizeof(tres), "\\_SB.PN%d%X", socket, stack); - } else { - bus_base = ri->BusBase + HQM1_BUS_OFFSET; - bus_limit = bus_base + HQM_RESERVED_BUS; - mem64_base = ri->PciResourceMem64Base + CPM_MMIO_SIZE + HQM_MMIO_SIZE - + CPM_MMIO_SIZE; - mem64_limit = mem64_base + HQM_MMIO_SIZE - 1; - snprintf(tres, sizeof(tres), "\\_SB.HR%d%X", socket, stack); - } - - /* Note, some SKU doesn't provide CPM1 and HQM1 and owns smaller bus ranges - accordingly*/ - if (bus_limit > ri->BusLimit) - continue; - - printk(BIOS_DEBUG, - "\tCreating Dino ResourceTemplate %s for socket: %d, " - "stack: %d\n bus_base:0x%x, bus_limit:0x%x\n", - tres, socket, stack, bus_base, bus_limit); - - acpigen_write_scope(tres); - acpigen_write_name("_CRS"); - acpigen_write_resourcetemplate_header(); - - acpigen_resource_word(2, 0xc, 0, 0, bus_base, bus_limit, 0x0, - (bus_limit - bus_base + 1)); - - /* Mem32 resource */ - if (rlist[i] == DSDT_DINO) - acpigen_resource_dword(0, 0xc, 1, 0, ri->PciResourceMem32Base, - ri->PciResourceMem32Limit, 0x0, - (ri->PciResourceMem32Limit - - ri->PciResourceMem32Base + 1)); - - /* Mem64 resource */ - acpigen_resource_qword(0, 0xc, 1, 0, mem64_base, mem64_limit, 0, - (mem64_limit - mem64_base + 1)); - - acpigen_write_resourcetemplate_footer(); - acpigen_pop_len(); - } -} - -static void create_dsdt_ubox_resource(uint8_t socket, uint8_t stack, const STACK_RES *ri, bool stack_enabled) -{ - /* - Stacks D .. E (TYPE_UBOX) - Scope: UC/UD<socket><0..1> for UBOX[1-2], ResourceTemplate: UT/UU - */ - for (int i = 0; i < 2; ++i) { - char tres[16]; - /* write _CRS scope */ - if (i == 0) - snprintf(tres, sizeof(tres), "\\_SB.UC%d%X", socket, stack); - else - snprintf(tres, sizeof(tres), "\\_SB.UD%d%X", socket, stack); - - printk(BIOS_DEBUG, "\tCreating ResourceTemplate %s for socket: %d, stack: %d\n", - tres, socket, stack); - - acpigen_write_scope(tres); - acpigen_write_name("_CRS"); - acpigen_write_resourcetemplate_header(); - - if (!stack_enabled) - acpigen_resource_word(2, 0, 0, 0, 0, 0, 0, 0); - else if (i == 0) - acpigen_resource_word(2, 0xc, 0, 0, ri->BusBase, ri->BusBase, 0x0, 1); - else - acpigen_resource_word(2, 0xc, 0, 0, ri->BusBase + 1, ri->BusBase + 1, - 0x0, 1); - - acpigen_write_resourcetemplate_footer(); - acpigen_pop_len(); - } -} - - /* * Add a DSDT ACPI Name field for STACK enable setting. * This is retrieved by the device _STA defined in iiostack.asl */ -static void create_dsdt_stack_sta(uint8_t socket, uint8_t stack, const STACK_RES *ri, bool stack_enabled) +static void create_dsdt_stack_sta(uint8_t socket, uint8_t stack, bool stack_enabled) { char stack_sta[16]; snprintf(stack_sta, sizeof(stack_sta), "ST%d%X", socket, stack); @@ -375,17 +107,11 @@ __func__, socket, stack, ri->Personality); if (stack <= IioStack5) { // TYPE_UBOX_IIO - create_dsdt_iou_pci_resource(socket, stack, ri, stack_enabled); - if (is_iio_cxl_stack_res(ri)) - create_dsdt_iou_cxl_resource(socket, stack, ri, - stack_enabled); - create_dsdt_stack_sta(socket, stack, ri, stack_enabled); + create_dsdt_stack_sta(socket, stack, stack_enabled); } else if (stack >= IioStack8 && stack <= IioStack11) { // TYPE_DINO - create_dsdt_ioat_resource(socket, stack, ri, stack_enabled); - create_dsdt_stack_sta(socket, stack, ri, stack_enabled); + create_dsdt_stack_sta(socket, stack, stack_enabled); } else if (stack == IioStack13) { // TYPE_UBOX - create_dsdt_ubox_resource(socket, stack, ri, stack_enabled); - create_dsdt_stack_sta(socket, stack, ri, stack_enabled); + create_dsdt_stack_sta(socket, stack, stack_enabled); } } } -- To view, visit https://review.coreboot.org/c/coreboot/+/80796?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8b0bc2eb02569b5d74f8521d79e0af8fee880c80 Gerrit-Change-Number: 80796 Gerrit-PatchSet: 12 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[L] Change in coreboot[main]: soc/intel/xeon_sp: Use common _CRS code generation
by Lean Sheng Tan (Code Review) 14 Mar '24

14 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Patrick Rudolph, Shuo Liu, Tim Chu. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80796?usp=email ) Change subject: soc/intel/xeon_sp: Use common _CRS code generation ...................................................................... Patch Set 11: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/80796?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8b0bc2eb02569b5d74f8521d79e0af8fee880c80 Gerrit-Change-Number: 80796 Gerrit-PatchSet: 11 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Thu, 14 Mar 2024 18:56:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: soc/intel/xeon_sp: Drop IIO_UDS argument
by Lean Sheng Tan (Code Review) 14 Mar '24

14 Mar '24

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81181?usp=email ) Change subject: soc/intel/xeon_sp: Drop IIO_UDS argument ...................................................................... soc/intel/xeon_sp: Drop IIO_UDS argument Use CONFIG_MAX_SOCKET instead of the IIO_UDS hob. Allows to drop the argument in Xeon-SP common layer. TEST=intel/archercity CRB Change-Id: I05ec127f2bf84d3c242c3b0bca9709a0a7a4b52b Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Signed-off-by: Jincheng Li <jincheng.li(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81181 Reviewed-by: Shuo Liu <shuo.liu(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> --- M src/soc/intel/xeon_sp/acpi.c M src/soc/intel/xeon_sp/chip_common.c M src/soc/intel/xeon_sp/uncore_acpi.c 3 files changed, 7 insertions(+), 7 deletions(-) Approvals: Shuo Liu: Looks good to me, approved build bot (Jenkins): Verified Lean Sheng Tan: Looks good to me, approved diff --git a/src/soc/intel/xeon_sp/acpi.c b/src/soc/intel/xeon_sp/acpi.c index 0cc0931..11913d3 100644 --- a/src/soc/intel/xeon_sp/acpi.c +++ b/src/soc/intel/xeon_sp/acpi.c @@ -99,10 +99,9 @@ *ioapic_bases = xeonsp_ioapic_bases; - for (int socket = 0, iio = 0; iio < hob->PlatformData.numofIIO; socket++) { + for (int socket = 0; socket < CONFIG_MAX_SOCKET; socket++) { if (!soc_cpu_is_enabled(socket)) continue; - iio++; for (int stack = 0; stack < MAX_IIO_STACK; ++stack) { const STACK_RES *ri = &hob->PlatformData.IIO_resource[socket].StackRes[stack]; diff --git a/src/soc/intel/xeon_sp/chip_common.c b/src/soc/intel/xeon_sp/chip_common.c index da97d1a..853b6bf 100644 --- a/src/soc/intel/xeon_sp/chip_common.c +++ b/src/soc/intel/xeon_sp/chip_common.c @@ -373,7 +373,9 @@ return; struct bus *root_bus = dev_root.downstream; - for (int s = 0; s < hob->PlatformData.numofIIO; ++s) { + for (int s = 0; s < CONFIG_MAX_SOCKET; ++s) { + if (!soc_cpu_is_enabled(s)) + continue; for (int x = 0; x < MAX_LOGIC_IIO_STACK; ++x) { const STACK_RES *ri = &hob->PlatformData.IIO_resource[s].StackRes[x]; if (ri->BusBase > ri->BusLimit) diff --git a/src/soc/intel/xeon_sp/uncore_acpi.c b/src/soc/intel/xeon_sp/uncore_acpi.c index bee6a3b..96a2b3f 100644 --- a/src/soc/intel/xeon_sp/uncore_acpi.c +++ b/src/soc/intel/xeon_sp/uncore_acpi.c @@ -379,7 +379,7 @@ return current; } -static unsigned long acpi_create_atsr(unsigned long current, const IIO_UDS *hob) +static unsigned long acpi_create_atsr(unsigned long current) { struct device *child, *dev; struct resource *resource; @@ -391,10 +391,9 @@ * This is easier than to sort the host bridges by PCI segment group first * and then generate one ATSR header for every new segment. */ - for (int socket = 0, iio = 0; iio < hob->PlatformData.numofIIO; ++socket) { + for (int socket = 0; socket < CONFIG_MAX_SOCKET; ++socket) { if (!soc_cpu_is_enabled(socket)) continue; - iio++; unsigned long tmp = current; bool first = true; @@ -542,7 +541,7 @@ current = acpi_create_rmrr(current); // Root Port ATS Capability - current = acpi_create_atsr(current, hob); + current = acpi_create_atsr(current); // RHSA current = acpi_create_rhsa(current); -- To view, visit https://review.coreboot.org/c/coreboot/+/81181?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I05ec127f2bf84d3c242c3b0bca9709a0a7a4b52b Gerrit-Change-Number: 81181 Gerrit-PatchSet: 7 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: soc/intel/xeon_sp: Drop IIO_UDS argument
by Lean Sheng Tan (Code Review) 14 Mar '24

14 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, Jincheng Li, Johnny Lin, Patrick Rudolph, Shuo Liu, Tim Chu. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81181?usp=email ) Change subject: soc/intel/xeon_sp: Drop IIO_UDS argument ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81181?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I05ec127f2bf84d3c242c3b0bca9709a0a7a4b52b Gerrit-Change-Number: 81181 Gerrit-PatchSet: 6 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Thu, 14 Mar 2024 18:54:32 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: util/intelmetool: Print the address in `map_physical` errors in hex
by Nico Huber (Code Review) 14 Mar '24

14 Mar '24

Attention is currently required from: Christian Walter, Máté Kukri. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81191?usp=email ) Change subject: util/intelmetool: Print the address in `map_physical` errors in hex ...................................................................... Patch Set 1: (1 comment) File util/intelmetool/mmap.c: https://review.coreboot.org/c/coreboot/+/81191/comment/efc17c93_4065e2ee : PS1, Line 22: (intmax_t)phys_addr, len, err, strerror(err)); > The reason I left is because my manpage says: […] That's for `j`, which is only a length modifier. `x` is the conversion specifier and unsigned. -- To view, visit https://review.coreboot.org/c/coreboot/+/81191?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib97bd86ee0e0c8fe8c3785e22a4d9f6def3cae61 Gerrit-Change-Number: 81191 Gerrit-PatchSet: 1 Gerrit-Owner: Máté Kukri <kukri.mate(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Máté Kukri <kukri.mate(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Comment-Date: Thu, 14 Mar 2024 18:53:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Máté Kukri <kukri.mate(a)gmail.com> Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: util/nixshell: Add a dev shell for i386 arch
by Felix Singer (Code Review) 14 Mar '24

14 Mar '24

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80644?usp=email ) Change subject: util/nixshell: Add a dev shell for i386 arch ...................................................................... util/nixshell: Add a dev shell for i386 arch Add a Nix shell file to provide a simple environment for coreboot development of i386 architecture. Currently, this environment is capable of completing Tutorial Part 1 in https://doc.coreboot.org. The Nix shell can be used by running the following command: $ nix-shell --pure util/nixshell/devshell-i386.nix The `--pure` parameter is optional. In Nixpkgs, there is a package called 'coreboot-toolchain'. It fetches the source code of coreboot, build crossgcc, and export it as output. With the binary cache mechanism of Nix, crossgcc can be directly downloaded and used without compiling on user's machine. This Nix shell has been tested on a NixOS laptop and a Debian 12 server, and they both work fine. Change-Id: Idcfe10be214e9bca590a62b8a207267493a4861f Signed-off-by: Crabtux <crabtux(a)mail.ustc.edu.cn> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80644 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> --- A util/nixshell/devshell-i386.nix 1 file changed, 29 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved diff --git a/util/nixshell/devshell-i386.nix b/util/nixshell/devshell-i386.nix new file mode 100644 index 0000000..88a67dc --- /dev/null +++ b/util/nixshell/devshell-i386.nix @@ -0,0 +1,29 @@ +with import <nixpkgs> {}; + +pkgs.mkShell { + name = "coreboot-devshell-i386"; + + packages = [ + cacert + gdb + git + qemu + ]; + + buildInputs = [ + ncurses + openssl + ]; + + nativeBuildInputs = [ + coreboot-toolchain.i386 + pkg-config + openssh + ]; + + shellHook = '' + # In Nix, stdenv sets a STRIP environment variable, which has conflict + # with libpayload/Makefile.payload. Unset the variable. + unset STRIP + ''; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/80644?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idcfe10be214e9bca590a62b8a207267493a4861f Gerrit-Change-Number: 80644 Gerrit-PatchSet: 3 Gerrit-Owner: 忧郁沙茶 <crabtux(a)mail.ustc.edu.cn> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: merged

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