coreboot-gerrit March 2024

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[XS] Change in coreboot[main]: symbols: Add __maybe_unused flag to region variable symbols
by Julius Werner (Code Review) 14 Mar '24

14 Mar '24

Attention is currently required from: Arthur Heymans, Lean Sheng Tan, Patrick Rudolph, Shuo Liu. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81209?usp=email ) Change subject: symbols: Add __maybe_unused flag to region variable symbols ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > Since this is a workaround, we didn't intend to spread the changes to a global context. […] I mean, I still don't see why you can't just declare it at global scope in the `memory_init.c` file. I guess I don't really mind adding the `__maybe_unused` either... but if you want to do that please add it t everything (`_name`, `_ename` and `_name_size` for both `DECLARE_REGION` and `DECLARE_OPTIONAL_REGION`), to keep things consistent. -- To view, visit https://review.coreboot.org/c/coreboot/+/81209?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia5ed183b2dd7a474ce51de47dbc1f9e3f61e5a41 Gerrit-Change-Number: 81209 Gerrit-PatchSet: 2 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Thu, 14 Mar 2024 15:06:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: include/imd{,_private}.h: Move define LIMIT_ALIGN to <imd.h>
by Elyes Haouas (Code Review) 14 Mar '24

14 Mar '24

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81278?usp=email ) Change subject: include/imd{,_private}.h: Move define LIMIT_ALIGN to <imd.h> ...................................................................... include/imd{,_private}.h: Move define LIMIT_ALIGN to <imd.h> Change-Id: I583cbd1d20f8f0a70e246eebc085477852d77d39 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/include/imd.h M src/include/imd_private.h 2 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/81278/1 diff --git a/src/include/imd.h b/src/include/imd.h index df669fd..ccbb5a5 100644 --- a/src/include/imd.h +++ b/src/include/imd.h @@ -6,6 +6,8 @@ #include <stdint.h> #include <stddef.h> +#define LIMIT_ALIGN 4096 + /* * imd is an in-memory database/directory/datastore (whatever d word you * desire). It grows downwards in memory from provided upper limit and @@ -40,8 +42,6 @@ struct imd_entry; struct imd; -static const size_t LIMIT_ALIGN = 4096; - /* * Initialize handle to use for working with an imd. Upper limit is the * exclusive address (aligned down to LIMIT_ALIGN) to start allocating down diff --git a/src/include/imd_private.h b/src/include/imd_private.h index 3ff6a51..c565d2b 100644 --- a/src/include/imd_private.h +++ b/src/include/imd_private.h @@ -5,6 +5,7 @@ #include <cbmem.h> #include <commonlib/bsd/helpers.h> +#include <imd.h> /* In-memory data structures. */ struct imd_root_pointer { @@ -34,7 +35,6 @@ #define IMD_ROOT_PTR_MAGIC 0xc0389481 #define IMD_ENTRY_MAGIC (~0xc0389481) #define SMALL_REGION_ID CBMEM_ID_IMD_SMALL -#define LIMIT_ALIGN 4096 #define IMD_FLAG_LOCKED 1 -- To view, visit https://review.coreboot.org/c/coreboot/+/81278?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I583cbd1d20f8f0a70e246eebc085477852d77d39 Gerrit-Change-Number: 81278 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: vc/amd/opensil: don't use source path when using stub
by Felix Held (Code Review) 14 Mar '24

14 Mar '24

Attention is currently required from: Marshall Dawson. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81189?usp=email ) Change subject: vc/amd/opensil: don't use source path when using stub ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81189?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic050ff0fa3f428e6adff3357f476fcd8a88cdf7e Gerrit-Change-Number: 81189 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Comment-Date: Thu, 14 Mar 2024 14:34:01 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: soc/amd/phoenix: make openSIL stub optional
by Felix Held (Code Review) 14 Mar '24

14 Mar '24

Attention is currently required from: Fred Reitberger, Jason Glenesk, Marshall Dawson, Matt DeVillier. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81188?usp=email ) Change subject: soc/amd/phoenix: make openSIL stub optional ...................................................................... Patch Set 1: Code-Review+1 (1 comment) File src/soc/amd/phoenix/Kconfig: https://review.coreboot.org/c/coreboot/+/81188/comment/d0c9dbf8_71b9d248 : PS1, Line 476: help : Select this option to include the openSIL stub in the build that can : be used for build-testing before the actual openSIL source code for a : SoC is released. neither the help text nor the type are needed here, but apart from that, this change will help quite a bit -- To view, visit https://review.coreboot.org/c/coreboot/+/81188?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2b48e2bbf71cd94ac7ecec13834ba36aa6c241ce Gerrit-Change-Number: 81188 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Thu, 14 Mar 2024 14:03:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: payload/external/edk2: Explicitly define the build arch as X64
by Sean Rhodes (Code Review) 14 Mar '24

14 Mar '24

Attention is currently required from: Arthur Heymans, Arthur Heymans, Benjamin Doron, Martin L Roth, Matt DeVillier, Nicholas Sudsgaard, Sean Rhodes. Sean Rhodes has uploaded a new patch set (#7) to the change originally created by Nicholas Sudsgaard. ( https://review.coreboot.org/c/coreboot/+/80883?usp=email ) The following approvals got outdated and were removed: Code-Review+1 by Benjamin Doron, Code-Review+1 by Sean Rhodes, Verified+1 by build bot (Jenkins) Change subject: payload/external/edk2: Explicitly define the build arch as X64 ...................................................................... payload/external/edk2: Explicitly define the build arch as X64 Upstream commit 11ad164bce (UefiPayloadPkg: Make UPL build script arch agnostic, 2024-02-22) changes the build script's behavior to not assume the arch. Without defining BUILD_ARCH, the build script will not function properly and results in the payload failing to build. Both UefiPayload and Universal Payload can only be built in X64. Change-Id: Icd942d0c15a99231d09f9cbdc5eb48333b6aa6e5 Signed-off-by: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> --- M payloads/external/edk2/Makefile 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/80883/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/80883?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icd942d0c15a99231d09f9cbdc5eb48333b6aa6e5 Gerrit-Change-Number: 80883 Gerrit-PatchSet: 7 Gerrit-Owner: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[main]: security/tpm: make tis_probe() return tpm_family
by Krystian Hebel (Code Review) 14 Mar '24

14 Mar '24

Attention is currently required from: Christian Walter, Julius Werner, Jérémy Compostella, Martin L Roth, Michał Żygowski, Sergii Dmytruk. Krystian Hebel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69159?usp=email ) Change subject: security/tpm: make tis_probe() return tpm_family ...................................................................... Patch Set 26: (1 comment) File src/drivers/i2c/tpm/tpm.c: https://review.coreboot.org/c/coreboot/+/69159/comment/87936ac3_58099a84 : PS1, Line 461: *tpm_family = 1; > Updated both `tpm.c` and `tis_atmel.c`. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/69159?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5006e0cdfef76ff79ce9e1cf280fcd5515ae01b0 Gerrit-Change-Number: 69159 Gerrit-PatchSet: 26 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Comment-Date: Thu, 14 Mar 2024 13:37:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Krystian Hebel <krystian.hebel(a)3mdeb.com> Comment-In-Reply-To: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: soc/intel/xeon_sp/spr: Rewrite acpi_fill_cedt
by Patrick Rudolph (Code Review) 14 Mar '24

14 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Lean Sheng Tan, Patrick Rudolph, Shuo Liu, Tim Chu. Hello Arthur Heymans, Christian Walter, Johnny Lin, Lean Sheng Tan, Shuo Liu, Tim Chu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81274?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: soc/intel/xeon_sp/spr: Rewrite acpi_fill_cedt ...................................................................... soc/intel/xeon_sp/spr: Rewrite acpi_fill_cedt Rewrite acpi_fill_cedt based on the newly introduced domain code and thus allow dropping the use of FSP HOBs and the use of hob_iiouds.h. TODO: Needs tests on CXL enabled platforms. Change-Id: I1a1ad0386523862a075eec478a3d785fa7423b45 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/intel/xeon_sp/include/soc/acpi.h M src/soc/intel/xeon_sp/spr/soc_acpi.c M src/soc/intel/xeon_sp/uncore_acpi.c 3 files changed, 23 insertions(+), 42 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/81274/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81274?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1a1ad0386523862a075eec478a3d785fa7423b45 Gerrit-Change-Number: 81274 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: drivers/pc80/tpm: Support Xeon-SP
by Patrick Rudolph (Code Review) 14 Mar '24

14 Mar '24

Attention is currently required from: Christian Walter, Jérémy Compostella. Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81276?usp=email ) Change subject: drivers/pc80/tpm: Support Xeon-SP ...................................................................... drivers/pc80/tpm: Support Xeon-SP On Xeon-SP the first PCI domain isn't named PCI0 and thus the TPM ACPI code fails to evaluate. Instead of hardcoding an ACPI path use the domain name set in the SoC chip_ops. Change-Id: I6130b937ec81bbde78d2619eb859ecf354fc3854 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/drivers/pc80/tpm/tis.c 1 file changed, 13 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/81276/1 diff --git a/src/drivers/pc80/tpm/tis.c b/src/drivers/pc80/tpm/tis.c index 90fa32e..fda89c4 100644 --- a/src/drivers/pc80/tpm/tis.c +++ b/src/drivers/pc80/tpm/tis.c @@ -799,9 +799,20 @@ #if CONFIG(HAVE_ACPI_TABLES) static void lpc_tpm_fill_ssdt(const struct device *dev) { - /* Windows 11 requires the following path for TPM to be detected */ - const char *path = "\\_SB_.PCI0"; + const struct device *domain = dev_get_pci_domain(dev); + const char *path; + /* Windows 11 requires the following path for TPM to be detected */ + assert(domain); + if (domain) + path = acpi_device_path(domain); + else + path = "\\_SB_.PCI0"; + +#if !DEVTREE_EARLY + printk(BIOS_INFO, "%s.%s: %s %s\n", path, acpi_device_name(dev), + dev->chip_ops->name, dev_path(dev)); +#endif /* Device */ acpigen_write_scope(path); acpigen_write_device(acpi_device_name(dev)); @@ -867,11 +878,6 @@ acpigen_pop_len(); /* Device */ acpigen_pop_len(); /* Scope */ - -#if !DEVTREE_EARLY - printk(BIOS_INFO, "%s.%s: %s %s\n", path, acpi_device_name(dev), - dev->chip_ops->name, dev_path(dev)); -#endif } static const char *lpc_tpm_acpi_name(const struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/81276?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6130b937ec81bbde78d2619eb859ecf354fc3854 Gerrit-Change-Number: 81276 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: device/device_util: Use const qualifier
by Patrick Rudolph (Code Review) 14 Mar '24

14 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Lean Sheng Tan, Shuo Liu, Tim Chu. Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81275?usp=email ) Change subject: device/device_util: Use const qualifier ...................................................................... device/device_util: Use const qualifier Allows to use the function in more places that expect the struct device to be readonly. Change-Id: Iac04fe6931a43070f6638b399adbff2ce64829c9 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/device/device_util.c M src/include/device/device.h M src/soc/intel/xeon_sp/chip_common.c M src/soc/intel/xeon_sp/include/soc/chip_common.h M src/soc/intel/xeon_sp/uncore_acpi.c 5 files changed, 14 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/81275/1 diff --git a/src/device/device_util.c b/src/device/device_util.c index b5d0d98..5af80a4 100644 --- a/src/device/device_util.c +++ b/src/device/device_util.c @@ -250,7 +250,7 @@ } /* Returns the PCI domain for the given PCI device */ -struct device *dev_get_pci_domain(struct device *dev) +const struct device *dev_get_pci_domain(const struct device *dev) { /* Walk up the tree up to the PCI domain */ while (dev && dev->upstream && !is_root_device(dev)) { diff --git a/src/include/device/device.h b/src/include/device/device.h index 25f730b..67b641f 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -182,7 +182,7 @@ const char *dev_name(const struct device *dev); const char *dev_path(const struct device *dev); u32 dev_path_encode(const struct device *dev); -struct device *dev_get_pci_domain(struct device *dev); +const struct device *dev_get_pci_domain(const struct device *dev); void dev_set_enabled(struct device *dev, int enable); void disable_children(struct bus *bus); bool dev_is_active_bridge(struct device *dev); diff --git a/src/soc/intel/xeon_sp/chip_common.c b/src/soc/intel/xeon_sp/chip_common.c index a178d3d..d8aaecb 100644 --- a/src/soc/intel/xeon_sp/chip_common.c +++ b/src/soc/intel/xeon_sp/chip_common.c @@ -67,7 +67,7 @@ static int filter_device_on_stack(struct device *dev, uint8_t socket, uint8_t stack, u16 vendor, u16 device) { - struct device *domain = dev_get_pci_domain(dev); + const struct device *domain = dev_get_pci_domain(dev); if (!domain) return 0; if (dev->path.type != DEVICE_PATH_PCI) @@ -158,7 +158,7 @@ */ int iio_pci_domain_socket_from_dev(struct device *dev) { - struct device *domain; + const struct device *domain; union xeon_domain_path dn; if (dev->path.type == DEVICE_PATH_DOMAIN) @@ -184,7 +184,7 @@ */ int iio_pci_domain_stack_from_dev(struct device *dev) { - struct device *domain; + const struct device *domain; union xeon_domain_path dn; if (dev->path.type == DEVICE_PATH_DOMAIN) @@ -413,7 +413,7 @@ } } -bool is_pcie_domain(struct device *dev) +bool is_pcie_domain(const struct device *dev) { if ((!dev) || (dev->path.type != DEVICE_PATH_DOMAIN)) return false; @@ -421,7 +421,7 @@ return strstr(dev->name, DOMAIN_TYPE_PCIE); } -bool is_ioat_domain(struct device *dev) +bool is_ioat_domain(const struct device *dev) { if ((!dev) || (dev->path.type != DEVICE_PATH_DOMAIN)) return false; @@ -433,7 +433,7 @@ strstr(dev->name, DOMAIN_TYPE_HQM1)); } -bool is_ubox_domain(struct device *dev) +bool is_ubox_domain(const struct device *dev) { if ((!dev) || (dev->path.type != DEVICE_PATH_DOMAIN)) return false; @@ -443,7 +443,7 @@ } -bool is_cxl_domain(struct device *dev) +bool is_cxl_domain(const struct device *dev) { if ((!dev) || (dev->path.type != DEVICE_PATH_DOMAIN)) return false; diff --git a/src/soc/intel/xeon_sp/include/soc/chip_common.h b/src/soc/intel/xeon_sp/include/soc/chip_common.h index c61e51a..6238ebb 100644 --- a/src/soc/intel/xeon_sp/include/soc/chip_common.h +++ b/src/soc/intel/xeon_sp/include/soc/chip_common.h @@ -74,10 +74,10 @@ int iio_pci_domain_socket_from_dev(struct device *dev); int iio_pci_domain_stack_from_dev(struct device *dev); -bool is_pcie_domain(struct device *dev); -bool is_ioat_domain(struct device *dev); -bool is_ubox_domain(struct device *dev); -bool is_cxl_domain(struct device *dev); +bool is_pcie_domain(const struct device *dev); +bool is_ioat_domain(const struct device *dev); +bool is_ubox_domain(const struct device *dev); +bool is_cxl_domain(const struct device *dev); #define is_dev_on_pcie_domain(dev) is_pcie_domain(dev_get_pci_domain(dev)) #define is_dev_on_ioat_domain(dev) is_ioat_domain(dev_get_pci_domain(dev)) diff --git a/src/soc/intel/xeon_sp/uncore_acpi.c b/src/soc/intel/xeon_sp/uncore_acpi.c index 12d99da..0635671 100644 --- a/src/soc/intel/xeon_sp/uncore_acpi.c +++ b/src/soc/intel/xeon_sp/uncore_acpi.c @@ -316,7 +316,7 @@ // Add PCIe Ports if (!is_dev_on_domain0(iommu)) { - struct device *domain = dev_get_pci_domain(iommu); + const struct device *domain = dev_get_pci_domain(iommu); struct device *dev = NULL; while ((dev = dev_bus_each_child(domain->downstream, dev))) if ((dev->hdr_type & 0x7f) == PCI_HEADER_TYPE_BRIDGE) -- To view, visit https://review.coreboot.org/c/coreboot/+/81275?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iac04fe6931a43070f6638b399adbff2ce64829c9 Gerrit-Change-Number: 81275 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[main]: soc/intel/xeon_sp/spr: Rewrite acpi_fill_cedt
by Patrick Rudolph (Code Review) 14 Mar '24

14 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Lean Sheng Tan, Shuo Liu, Tim Chu. Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81274?usp=email ) Change subject: soc/intel/xeon_sp/spr: Rewrite acpi_fill_cedt ...................................................................... soc/intel/xeon_sp/spr: Rewrite acpi_fill_cedt Rewrite acpi_fill_cedt based on the newly introduced domain code and thus allow dropping the use of FSP HOBs and the use of hob_iiouds.h. TODO: Needs tests on CXL enabled platforms. Change-Id: I1a1ad0386523862a075eec478a3d785fa7423b45 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/intel/xeon_sp/include/soc/acpi.h M src/soc/intel/xeon_sp/spr/soc_acpi.c M src/soc/intel/xeon_sp/uncore_acpi.c 3 files changed, 24 insertions(+), 43 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/81274/1 diff --git a/src/soc/intel/xeon_sp/include/soc/acpi.h b/src/soc/intel/xeon_sp/include/soc/acpi.h index 882c226..b76fb7e 100644 --- a/src/soc/intel/xeon_sp/include/soc/acpi.h +++ b/src/soc/intel/xeon_sp/include/soc/acpi.h @@ -24,7 +24,6 @@ unsigned long northbridge_write_acpi_tables(const struct device *device, unsigned long current, struct acpi_rsdp *rsdp); unsigned long xeonsp_acpi_create_madt_lapics(unsigned long current); -unsigned long acpi_fill_cedt(unsigned long current); unsigned long acpi_fill_hmat(unsigned long current); unsigned long cxl_fill_srat(unsigned long current); diff --git a/src/soc/intel/xeon_sp/spr/soc_acpi.c b/src/soc/intel/xeon_sp/spr/soc_acpi.c index 607ee6c..4b88900 100644 --- a/src/soc/intel/xeon_sp/spr/soc_acpi.c +++ b/src/soc/intel/xeon_sp/spr/soc_acpi.c @@ -18,7 +18,6 @@ #include <soc/pm.h> #include <soc/soc_util.h> #include <soc/util.h> -#include <hob_iiouds.h> int soc_madt_sci_irq_polarity(int sci) { @@ -174,44 +173,4 @@ } return current; -} - -unsigned long acpi_fill_cedt(unsigned long current) -{ - const IIO_UDS *hob = get_iio_uds(); - union uid { - uint32_t data; - struct { - uint8_t byte0; - uint8_t byte1; - uint8_t byte2; - uint8_t byte3; - }; - } cxl_uid; - u32 cxl_ver; - u64 base; - - cxl_uid.byte0 = 'C'; - cxl_uid.byte1 = 'X'; - /* Loop through all sockets and stacks, add CHBS for each CXL IIO stack */ - for (uint8_t socket = 0, iio = 0; iio < hob->PlatformData.numofIIO; ++socket) { - if (!soc_cpu_is_enabled(socket)) - continue; - iio++; - for (int x = 0; x < MAX_LOGIC_IIO_STACK; ++x) { - const STACK_RES *ri; - ri = &hob->PlatformData.IIO_resource[socket].StackRes[x]; - if (!is_iio_cxl_stack_res(ri)) - continue; - /* uid needs to match with ACPI CXL device ID, eg. acpi/iiostack.asl */ - cxl_uid.byte2 = socket + '0'; - cxl_uid.byte3 = x + '0'; - cxl_ver = ACPI_CEDT_CHBS_CXL_VER_1_1; - base = ri->Mmio32Base; /* DP RCRB base */ - current += acpi_create_cedt_chbs((acpi_cedt_chbs_t *)current, - cxl_uid.data, cxl_ver, base); - } - } - - return current; -} +} \ No newline at end of file diff --git a/src/soc/intel/xeon_sp/uncore_acpi.c b/src/soc/intel/xeon_sp/uncore_acpi.c index ef72335..12d99da 100644 --- a/src/soc/intel/xeon_sp/uncore_acpi.c +++ b/src/soc/intel/xeon_sp/uncore_acpi.c @@ -587,6 +587,29 @@ return current; } +static unsigned long acpi_fill_cedt(unsigned long current) +{ + struct device *dev = NULL; + u32 uid, cxl_ver = ACPI_CEDT_CHBS_CXL_VER_1_1; + + while ((dev = dev_find_path(dev, DEVICE_PATH_DOMAIN))) { + if (!is_cxl_domain(dev)) + continue; + + /* FIXME: Use define for resource index */ + struct resource *res = probe_resource(dev, 1); + assert (res); + if (!res) + continue; + + /* uid needs to match with ACPI CXL device ID, eg. acpi/iiostack.asl */ + memcpy(&uid, dev->name, sizeof(uid)); + current += acpi_create_cedt_chbs((acpi_cedt_chbs_t *)current, uid, + cxl_ver, res->base); + } + return current; +} + unsigned long northbridge_write_acpi_tables(const struct device *device, unsigned long current, struct acpi_rsdp *rsdp) { -- To view, visit https://review.coreboot.org/c/coreboot/+/81274?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1a1ad0386523862a075eec478a3d785fa7423b45 Gerrit-Change-Number: 81274 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newchange

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