coreboot-gerrit March 2024

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[S] Change in coreboot[main]: util/nixshell: Add a dev shell for i386 arch
by Felix Singer (Code Review) 14 Mar '24

14 Mar '24

Attention is currently required from: 忧郁沙茶. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80644?usp=email ) Change subject: util/nixshell: Add a dev shell for i386 arch ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/80644?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idcfe10be214e9bca590a62b8a207267493a4861f Gerrit-Change-Number: 80644 Gerrit-PatchSet: 2 Gerrit-Owner: 忧郁沙茶 <crabtux(a)mail.ustc.edu.cn> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: 忧郁沙茶 <crabtux(a)mail.ustc.edu.cn> Gerrit-Comment-Date: Thu, 14 Mar 2024 18:15:43 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: include/imd{,_private}.h: Move define LIMIT_ALIGN to <imd.h>
by Paul Menzel (Code Review) 14 Mar '24

14 Mar '24

Attention is currently required from: Elyes Haouas. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81278?usp=email ) Change subject: include/imd{,_private}.h: Move define LIMIT_ALIGN to <imd.h> ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/81278/comment/45c8bcaa_1d1e9664 : PS1, Line 8: Why? -- To view, visit https://review.coreboot.org/c/coreboot/+/81278?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I583cbd1d20f8f0a70e246eebc085477852d77d39 Gerrit-Change-Number: 81278 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Thu, 14 Mar 2024 17:45:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: soc/amd/phoenix: make openSIL stub optional
by Marshall Dawson (Code Review) 14 Mar '24

14 Mar '24

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, Varshit Pandya. Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81188?usp=email ) Change subject: soc/amd/phoenix: make openSIL stub optional ...................................................................... Patch Set 2: (1 comment) File src/soc/amd/phoenix/Kconfig: https://review.coreboot.org/c/coreboot/+/81188/comment/06f762cc_988087bd : PS1, Line 476: help : Select this option to include the openSIL stub in the build that can : be used for build-testing before the actual openSIL source code for a : SoC is released. > neither the help text nor the type are needed here, but apart from that, this change will help quite […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/81188?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2b48e2bbf71cd94ac7ecec13834ba36aa6c241ce Gerrit-Change-Number: 81188 Gerrit-PatchSet: 2 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 14 Mar 2024 17:36:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: soc/amd/phoenix: make openSIL stub optional
by Marshall Dawson (Code Review) 14 Mar '24

14 Mar '24

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Marshall Dawson, Matt DeVillier, Varshit Pandya. Hello Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, Varshit Pandya, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81188?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Code-Review+1 by Felix Held, Verified+1 by build bot (Jenkins) Change subject: soc/amd/phoenix: make openSIL stub optional ...................................................................... soc/amd/phoenix: make openSIL stub optional Convert the 'select SOC_AMD_OPENSIL_STUB' statement to a config option and give it a prompt. This allows for internal development of openSIL and corresponding coreboot source, and controllable using a defconfig. Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Change-Id: I2b48e2bbf71cd94ac7ecec13834ba36aa6c241ce --- M src/soc/amd/phoenix/Kconfig 1 file changed, 8 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/81188/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81188?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2b48e2bbf71cd94ac7ecec13834ba36aa6c241ce Gerrit-Change-Number: 81188 Gerrit-PatchSet: 2 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: vc/amd/opensil: don't use source path when using stub
by Varshit Pandya (Code Review) 14 Mar '24

14 Mar '24

Attention is currently required from: Marshall Dawson. Varshit Pandya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81189?usp=email ) Change subject: vc/amd/opensil: don't use source path when using stub ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81189?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic050ff0fa3f428e6adff3357f476fcd8a88cdf7e Gerrit-Change-Number: 81189 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Comment-Date: Thu, 14 Mar 2024 16:59:07 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[main]: ec/hp/kbc1126: Use ec/acpi/ec.h instead of its own implementation
by Felix Held (Code Review) 14 Mar '24

14 Mar '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81204?usp=email ) Change subject: ec/hp/kbc1126: Use ec/acpi/ec.h instead of its own implementation ...................................................................... ec/hp/kbc1126: Use ec/acpi/ec.h instead of its own implementation This also does some light cleaning up: - Place spaces in function names to make it easier to read. - Adds a newline to a console message. TEST=Tested to work on HP ProBook 450 G3 Change-Id: I73e60c5baa9db6874e480ecef41cf1006150e081 Signed-off-by: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81204 Reviewed-by: Nicholas Chin <nic.c3.14(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/ec/hp/kbc1126/Kconfig M src/ec/hp/kbc1126/ec.c 2 files changed, 21 insertions(+), 71 deletions(-) Approvals: build bot (Jenkins): Verified Nicholas Chin: Looks good to me, approved diff --git a/src/ec/hp/kbc1126/Kconfig b/src/ec/hp/kbc1126/Kconfig index 5e6edd6..79fba69 100644 --- a/src/ec/hp/kbc1126/Kconfig +++ b/src/ec/hp/kbc1126/Kconfig @@ -2,6 +2,7 @@ config EC_HP_KBC1126 bool + select EC_ACPI help Interface to SMSC KBC1126 embedded controller in HP laptops. diff --git a/src/ec/hp/kbc1126/ec.c b/src/ec/hp/kbc1126/ec.c index 2a71079..292736f 100644 --- a/src/ec/hp/kbc1126/ec.c +++ b/src/ec/hp/kbc1126/ec.c @@ -1,93 +1,41 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <arch/io.h> #include <console/console.h> #include <device/device.h> -#include <delay.h> +#include <ec/acpi/ec.h> -#include "ec.h" #include "chip.h" -static u16 ec_data_port; -static u16 ec_cmd_port; - -#define KBD_IBF (1 << 1) /* 1: input buffer full (data ready for ec) */ -#define KBD_OBF (1 << 0) /* 1: output buffer full (data ready for host) */ - -static void ec_setports(u16 data, u16 cmd) -{ - ec_data_port = data; - ec_cmd_port = cmd; -} - -static int send_kbd_command(u8 command) -{ - int timeout; - - timeout = 100000; /* 1 second */ - while ((inb(ec_cmd_port) & KBD_IBF) && --timeout) { - udelay(10); - if ((timeout & 0xff) == 0) - printk(BIOS_SPEW, "."); - } - if (!timeout) { - printk(BIOS_DEBUG, "Timeout while sending command 0x%02x to EC!\n", - command); - return -1; - } - - outb(command, ec_cmd_port); - return 0; -} - -static int send_kbd_data(u8 data) -{ - int timeout; - - timeout = 100000; /* 1 second */ - while ((inb(ec_cmd_port) & KBD_IBF) && --timeout) { /* wait for IBF = 0 */ - udelay(10); - if ((timeout & 0xff) == 0) - printk(BIOS_SPEW, "."); - } - if (!timeout) { - printk(BIOS_DEBUG, "Timeout while sending data 0x%02x to EC!\n", - data); - return -1; - } - - outb(data, ec_data_port); - return 0; -} +#define KBC_TIMEOUT_US 1000000 // 1s /* - * kbc1126_thermalinit: initialize fan control + * kbc1126_thermal_init: initialize fan control * The code is found in EcThermalInit of the vendor firmware. */ -static int kbc1126_thermalinit(u8 cmd, u8 value) +static int kbc1126_thermal_init(u8 cmd, u8 value) { - printk(BIOS_DEBUG, "KBC1126: initialize fan control."); + printk(BIOS_DEBUG, "KBC1126: initialize fan control.\n"); - if (send_kbd_command(cmd) < 0) + if (send_ec_command_timeout(cmd, KBC_TIMEOUT_US) < 0) return -1; - if (send_kbd_data(0x27) < 0) + if (send_ec_data_timeout(0x27, KBC_TIMEOUT_US) < 0) return -1; - if (send_kbd_data(0x01) < 0) + if (send_ec_data_timeout(0x01, KBC_TIMEOUT_US) < 0) return -1; /* * The following code is needed for fan control when AC is plugged in. */ - if (send_kbd_command(cmd) < 0) + if (send_ec_command_timeout(cmd, KBC_TIMEOUT_US) < 0) return -1; - if (send_kbd_data(0xd5) < 0) + if (send_ec_data_timeout(0xd5, KBC_TIMEOUT_US) < 0) return -1; - if (send_kbd_data(value) < 0) + if (send_ec_data_timeout(value, KBC_TIMEOUT_US) < 0) return -1; printk(BIOS_DEBUG, "KBC1126: fan control initialized.\n"); @@ -95,27 +43,28 @@ } /* - * kbc1126_kbdled: set CapsLock and NumLock LEDs + * kbc1126_kbd_led: set CapsLock and NumLock LEDs * This is used in MemoryErrorReport of the vendor firmware. */ -static void kbc1126_kbdled(u8 cmd, u8 val) +static void kbc1126_kbd_led(u8 cmd, u8 val) { - if (send_kbd_command(cmd) < 0) + if (send_ec_command_timeout(cmd, KBC_TIMEOUT_US) < 0) return; - if (send_kbd_data(0xf0) < 0) + if (send_ec_data_timeout(0xf0, KBC_TIMEOUT_US) < 0) return; - if (send_kbd_data(val) < 0) + if (send_ec_data_timeout(val, KBC_TIMEOUT_US) < 0) return; } static void kbc1126_enable(struct device *dev) { struct ec_hp_kbc1126_config *conf = dev->chip_info; - ec_setports(conf->ec_data_port, conf->ec_cmd_port); - kbc1126_kbdled(conf->ec_ctrl_reg, 0); - if (kbc1126_thermalinit(conf->ec_ctrl_reg, conf->ec_fan_ctrl_value) < 0) + + ec_set_ports(conf->ec_cmd_port, conf->ec_data_port); + kbc1126_kbd_led(conf->ec_ctrl_reg, 0); + if (kbc1126_thermal_init(conf->ec_ctrl_reg, conf->ec_fan_ctrl_value) < 0) printk(BIOS_DEBUG, "KBC1126: error when initializing fan control.\n"); } -- To view, visit https://review.coreboot.org/c/coreboot/+/81204?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I73e60c5baa9db6874e480ecef41cf1006150e081 Gerrit-Change-Number: 81204 Gerrit-PatchSet: 5 Gerrit-Owner: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: vendorcode/edk2-stable202302: Remove wchar_t asserts
by Subrata Banik (Code Review) 14 Mar '24

14 Mar '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81192?usp=email ) Change subject: vendorcode/edk2-stable202302: Remove wchar_t asserts ...................................................................... vendorcode/edk2-stable202302: Remove wchar_t asserts Remove those MSVC compiler defaults checks so that the GCC defaults for wchar_t can be used. The FSP interface does not depend on wchar_t. TEST: the resulting binaries are the same for intel/mtlrvp Change-Id: I0ee1abc7e9ba46665838b63a6cfe0f4aa300114c Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81192 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim(a)intel.com> Reviewed-by: Dinesh Gehlot <digehlot(a)google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Reviewed-by: Ronak Kanabar <ronak.kanabar(a)intel.com> Reviewed-by: Jérémy Compostella <jeremy.compostella(a)intel.com> --- M src/soc/intel/meteorlake/Makefile.mk M src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Base.h 2 files changed, 3 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Jérémy Compostella: Looks good to me, but someone else must approve Dinesh Gehlot: Looks good to me, approved Ronak Kanabar: Looks good to me, approved Subrata Banik: Looks good to me, approved Wonkyu Kim: Looks good to me, but someone else must approve Felix Singer: Looks good to me, approved diff --git a/src/soc/intel/meteorlake/Makefile.mk b/src/soc/intel/meteorlake/Makefile.mk index 39a1d65..893523c 100644 --- a/src/soc/intel/meteorlake/Makefile.mk +++ b/src/soc/intel/meteorlake/Makefile.mk @@ -60,5 +60,4 @@ CPPFLAGS_common += -I$(src)/soc/intel/meteorlake CPPFLAGS_common += -I$(src)/soc/intel/meteorlake/include -CFLAGS_common += -fshort-wchar endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Base.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Base.h index f1b9c14..8cdf6aa 100644 --- a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Base.h +++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Base.h @@ -792,8 +792,9 @@ STATIC_ASSERT (sizeof (UINT64) == 8, "sizeof (UINT64) does not meet UEFI Specification Data Type requirements"); STATIC_ASSERT (sizeof (CHAR8) == 1, "sizeof (CHAR8) does not meet UEFI Specification Data Type requirements"); STATIC_ASSERT (sizeof (CHAR16) == 2, "sizeof (CHAR16) does not meet UEFI Specification Data Type requirements"); -STATIC_ASSERT (sizeof (L'A') == 2, "sizeof (L'A') does not meet UEFI Specification Data Type requirements"); -STATIC_ASSERT (sizeof (L"A") == 4, "sizeof (L\"A\") does not meet UEFI Specification Data Type requirements"); +// Removed to have coreboot code compile with the Linux gcc defaults. The FSP interface does not need wchar_t anyway. +//STATIC_ASSERT (sizeof (L'A') == 2, "sizeof (L'A') does not meet UEFI Specification Data Type requirements"); +//STATIC_ASSERT (sizeof (L"A") == 4, "sizeof (L\"A\") does not meet UEFI Specification Data Type requirements"); // // The following three enum types are used to verify that the compiler -- To view, visit https://review.coreboot.org/c/coreboot/+/81192?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0ee1abc7e9ba46665838b63a6cfe0f4aa300114c Gerrit-Change-Number: 81192 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: amdfwtool: Set the table size only for FWs
by Bao Zheng (Code Review) 14 Mar '24

14 Mar '24

Attention is currently required from: Zheng Bao. Hello Zheng Bao, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/81255?usp=email to review the following change. Change subject: amdfwtool: Set the table size only for FWs ...................................................................... amdfwtool: Set the table size only for FWs The entry in the table has two categaries, file and pointer. For the pointer, it does not take space. The ISH, PSP level 2, BIOS table are all the pointer type. So only integration function packs FWs which increase the table size. Change-Id: I5dfbbb55912c8e37243c351427a8df89c12e5da8 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M util/amdfwtool/amdfwtool.c 1 file changed, 15 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/81255/1 diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index e81059d..d025ba4 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -521,23 +521,17 @@ } static void fill_dir_header(void *directory, uint32_t count, uint32_t cookie, - context *ctx, amd_cb_config *cb_config) + uint32_t table_size, context *ctx) { psp_combo_directory *cdir = directory; psp_directory_table *dir = directory; bios_directory_table *bdir = directory; - uint32_t table_size = 0; - if (!count) - return; if (ctx == NULL || directory == NULL) { fprintf(stderr, "Calling %s with NULL pointers\n", __func__); return; } - /* The table size needs to be 0x1000 aligned. So align the end of table. */ - adjust_current_pointer(ctx, 0, TABLE_ALIGNMENT); - switch (cookie) { case PSP2_COOKIE: case BHD2_COOKIE: @@ -556,14 +550,6 @@ break; case PSP_COOKIE: case PSPL2_COOKIE: - if (cookie == PSP_COOKIE && cb_config->need_ish) - /* The ISH header can not be in the space defined by L1 table size. - * The space is allocated when the L1 header is created. */ - table_size = TABLE_ALIGNMENT; - else - /* Generally table size not just constains the header, - * but all the FWs. */ - table_size = ctx->current - ctx->current_table; if ((table_size % TABLE_ALIGNMENT) != 0) { fprintf(stderr, "The PSP table size should be 4K aligned\n"); amdfwtool_cleanup(ctx); @@ -571,7 +557,7 @@ } dir->header.cookie = cookie; dir->header.num_entries = count; - dir->header.additional_info_fields.dir_size = table_size / TABLE_ALIGNMENT; + dir->header.additional_info_fields.dir_size += table_size / TABLE_ALIGNMENT; dir->header.additional_info_fields.spi_block_size = 1; dir->header.additional_info_fields.base_addr = 0; /* checksum everything that comes after the Checksum field */ @@ -582,7 +568,6 @@ break; case BHD_COOKIE: case BHDL2_COOKIE: - table_size = ctx->current - ctx->current_table; if ((table_size % TABLE_ALIGNMENT) != 0) { fprintf(stderr, "The BIOS table size should be 4K aligned\n"); amdfwtool_cleanup(ctx); @@ -590,7 +575,7 @@ } bdir->header.cookie = cookie; bdir->header.num_entries = count; - bdir->header.additional_info_fields.dir_size = table_size / TABLE_ALIGNMENT; + bdir->header.additional_info_fields.dir_size += table_size / TABLE_ALIGNMENT; bdir->header.additional_info_fields.spi_block_size = 1; bdir->header.additional_info_fields.base_addr = 0; /* checksum everything that comes after the Checksum field */ @@ -996,6 +981,9 @@ /* This APU doesn't have this firmware. */ } } + /* The table size needs to be 0x1000 aligned. So align the end of table. */ + adjust_current_pointer(ctx, 0, TABLE_ALIGNMENT); + fill_dir_header(pspdir, count, cookie, ctx->current - ctx->current_table, ctx); if (recovery_ab && (pspdir2 != NULL)) { if (cb_config->need_ish) { /* Need ISH */ @@ -1032,7 +1020,7 @@ count++; } - fill_dir_header(pspdir, count, cookie, ctx, cb_config); + fill_dir_header(pspdir, count, cookie, 0, ctx); ctx->current_table = current_table_save; } @@ -1397,7 +1385,10 @@ count++; } - fill_dir_header(biosdir, count, cookie, ctx, cb_config); + /* The table size needs to be 0x1000 aligned. So align the end of table. */ + adjust_current_pointer(ctx, 0, TABLE_ALIGNMENT); + + fill_dir_header(biosdir, count, cookie, ctx->current - ctx->current_table, ctx); ctx->current_table = current_table_save; } @@ -1685,8 +1676,8 @@ psp_combo_dir->entries[combo_index].lvl2_addr = BUFF_TO_RUN_MODE(ctx, pspdir, AMD_ADDR_REL_BIOS); - fill_dir_header(psp_combo_dir, combo_index + 1, - PSP2_COOKIE, &ctx, &cb_config); + fill_dir_header(psp_combo_dir, combo_index + 1, 0, + PSP2_COOKIE, &ctx); } if (have_bios_tables(amd_bios_table)) { @@ -1738,8 +1729,8 @@ bhd_combo_dir->entries[combo_index].lvl2_addr = BUFF_TO_RUN_MODE(ctx, biosdir, AMD_ADDR_REL_BIOS); - fill_dir_header(bhd_combo_dir, combo_index + 1, - BHD2_COOKIE, &ctx, &cb_config); + fill_dir_header(bhd_combo_dir, combo_index + 1, 0, + BHD2_COOKIE, &ctx); } } } while (cb_config.use_combo && ++combo_index < MAX_COMBO_ENTRIES && -- To view, visit https://review.coreboot.org/c/coreboot/+/81255?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5dfbbb55912c8e37243c351427a8df89c12e5da8 Gerrit-Change-Number: 81255 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Attention: Zheng Bao Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: vendorcode/edk2-stable202302: Remove wchar_t asserts
by Ronak Kanabar (Code Review) 14 Mar '24

14 Mar '24

Attention is currently required from: Arthur Heymans, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Tarun. Ronak Kanabar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81192?usp=email ) Change subject: vendorcode/edk2-stable202302: Remove wchar_t asserts ...................................................................... Patch Set 1: Code-Review+2 (1 comment) Patchset: PS1: > @ronak, did you get chance to validate this Cl and ensure the original problem reported by you is no […] CL is working for me. -- To view, visit https://review.coreboot.org/c/coreboot/+/81192?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0ee1abc7e9ba46665838b63a6cfe0f4aa300114c Gerrit-Change-Number: 81192 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Thu, 14 Mar 2024 15:43:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: mb/google/nissa/var/glassway: Add 2nd touchscreen via SSFC config
by Felix Held (Code Review) 14 Mar '24

14 Mar '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81217?usp=email ) Change subject: mb/google/nissa/var/glassway: Add 2nd touchscreen via SSFC config ...................................................................... mb/google/nissa/var/glassway: Add 2nd touchscreen via SSFC config Define SSFC bit 0-1 in coreboot for add 2nd BOE G7500 touchscreen. BUG=b:329339069 BRANCH=firmware-nissa-15217.B TEST=Check touchscreen can detect and function work. [INFO ] input: GTCH7503:00 2A94:A804 as /devices/pci0000:00/0000:00:15.1/i2c_designware.1/i2c-10/i2c-GTCH7503:00/0014 Change-Id: I85688919864e3cac1beb2442ef3e23fe9d5f916c Signed-off-by: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81217 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <ericllai(a)google.com> --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/variants/glassway/overridetree.cb 2 files changed, 12 insertions(+), 11 deletions(-) Approvals: build bot (Jenkins): Verified Frank Chu: Looks good to me, but someone else must approve Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index a22f665..0602207 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -239,6 +239,7 @@ select BOARD_GOOGLE_BASEBOARD_NISSA select DRIVERS_GENERIC_GPIO_KEYS select DRIVERS_GENESYSLOGIC_GL9750 + select EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG config BOARD_GOOGLE_GOTHRAX select BOARD_GOOGLE_BASEBOARD_NISSA diff --git a/src/mainboard/google/brya/variants/glassway/overridetree.cb b/src/mainboard/google/brya/variants/glassway/overridetree.cb index 08d247b..15b7d7e 100644 --- a/src/mainboard/google/brya/variants/glassway/overridetree.cb +++ b/src/mainboard/google/brya/variants/glassway/overridetree.cb @@ -16,7 +16,7 @@ field TOUCHSCREEN_SOURCE 32 33 option TOUCHSCREEN_UNPROVISIONED 0 option TOUCHSCREEN_ELAN0001 1 - option TOUCHSCREEN_ELAN9008 2 + option TOUCHSCREEN_GTCH7503 2 end end @@ -336,23 +336,23 @@ probe TOUCHSCREEN_SOURCE TOUCHSCREEN_ELAN0001 end end + chip drivers/i2c/hid - register "generic.hid" = ""ELAN9008"" - register "generic.desc" = ""ELAN Touchscreen"" + register "generic.hid" = ""GTCH7503"" + register "generic.desc" = ""G2TOUCH Touchscreen"" register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" - register "generic.detect" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" - register "generic.reset_delay_ms" = "20" - register "generic.reset_off_delay_ms" = "2" + register "generic.reset_delay_ms" = "50" + register "generic.reset_off_delay_ms" = "5" register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)" - register "generic.stop_delay_ms" = "280" - register "generic.stop_off_delay_ms" = "2" + register "generic.stop_delay_ms" = "30" + register "generic.stop_off_delay_ms" = "10" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" - register "generic.enable_delay_ms" = "1" + register "generic.enable_delay_ms" = "5" register "generic.has_power_resource" = "1" register "hid_desc_reg_offset" = "0x01" - device i2c 10 on - probe TOUCHSCREEN_SOURCE TOUCHSCREEN_ELAN9008 + device i2c 40 on + probe TOUCHSCREEN_SOURCE TOUCHSCREEN_GTCH7503 end end end #I2C1 -- To view, visit https://review.coreboot.org/c/coreboot/+/81217?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I85688919864e3cac1beb2442ef3e23fe9d5f916c Gerrit-Change-Number: 81217 Gerrit-PatchSet: 5 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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