coreboot-gerrit March 2024

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Drop uncore_fill_ssdt
by Patrick Rudolph (Code Review) 14 Mar '24

14 Mar '24

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81273?usp=email ) Change subject: soc/intel/xeon_sp: Drop uncore_fill_ssdt ...................................................................... soc/intel/xeon_sp: Drop uncore_fill_ssdt Let ACPI DSDT figure out by itself if a stack is enabled. Allows to drop uncore_fill_ssdt() on all platforms. Change-Id: Ib9051d608147f2de228509ff6b13871ca3183979 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/intel/xeon_sp/cpx/soc_acpi.c M src/soc/intel/xeon_sp/include/soc/acpi.h M src/soc/intel/xeon_sp/skx/soc_acpi.c M src/soc/intel/xeon_sp/spr/acpi/cxl_resource.asl M src/soc/intel/xeon_sp/spr/acpi/iiostack.asl M src/soc/intel/xeon_sp/spr/acpi/pci_resource.asl M src/soc/intel/xeon_sp/spr/soc_acpi.c M src/soc/intel/xeon_sp/uncore.c 8 files changed, 25 insertions(+), 83 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/81273/1 diff --git a/src/soc/intel/xeon_sp/cpx/soc_acpi.c b/src/soc/intel/xeon_sp/cpx/soc_acpi.c index b2d6d79..1434fbf 100644 --- a/src/soc/intel/xeon_sp/cpx/soc_acpi.c +++ b/src/soc/intel/xeon_sp/cpx/soc_acpi.c @@ -41,10 +41,6 @@ fadt->flags &= ~(ACPI_FADT_SEALED_CASE | ACPI_FADT_S4_RTC_WAKE); } -void uncore_fill_ssdt(const struct device *device) -{ -} - /* TODO: See if we can use the common generate_p_state_entries */ void soc_power_states_generation(int core, int cores_per_package) { diff --git a/src/soc/intel/xeon_sp/include/soc/acpi.h b/src/soc/intel/xeon_sp/include/soc/acpi.h index afccfe4..882c226 100644 --- a/src/soc/intel/xeon_sp/include/soc/acpi.h +++ b/src/soc/intel/xeon_sp/include/soc/acpi.h @@ -23,7 +23,6 @@ unsigned long northbridge_write_acpi_tables(const struct device *device, unsigned long current, struct acpi_rsdp *rsdp); -void uncore_fill_ssdt(const struct device *device); unsigned long xeonsp_acpi_create_madt_lapics(unsigned long current); unsigned long acpi_fill_cedt(unsigned long current); unsigned long acpi_fill_hmat(unsigned long current); diff --git a/src/soc/intel/xeon_sp/skx/soc_acpi.c b/src/soc/intel/xeon_sp/skx/soc_acpi.c index b98e998..30e14d3 100644 --- a/src/soc/intel/xeon_sp/skx/soc_acpi.c +++ b/src/soc/intel/xeon_sp/skx/soc_acpi.c @@ -54,10 +54,6 @@ fill_fadt_extended_pm_io(fadt); } -void uncore_fill_ssdt(const struct device *device) -{ -} - void soc_power_states_generation(int core, int cores_per_package) { } diff --git a/src/soc/intel/xeon_sp/spr/acpi/cxl_resource.asl b/src/soc/intel/xeon_sp/spr/acpi/cxl_resource.asl index 80b3da2..553ca9d 100644 --- a/src/soc/intel/xeon_sp/spr/acpi/cxl_resource.asl +++ b/src/soc/intel/xeon_sp/spr/acpi/cxl_resource.asl @@ -17,10 +17,20 @@ EisaId ("PNP0A03") /* PCI Bus */ }) Name (_UID, IIO_DEVICE_UID(DEVPREFIX, SOCKET, STACK)) - External (\_SB.IIO_DEVICE_NAME(STPREFIX, SOCKET, STACK)) - Method (_STA, 0, NotSerialized) // _STA: Status + Method (_STA, 0, NotSerialized) { - Return (\_SB.IIO_DEVICE_NAME(STPREFIX, SOCKET, STACK)) + /* + * _CRS is being generated by SSDT for available stacks only and + * when missing the stack isn't available. + */ + If (CondRefOf (_CRS)) + { + Return (0xf) + } + Else + { + Return (0) + } } Method (_PRT, 0, NotSerialized) { diff --git a/src/soc/intel/xeon_sp/spr/acpi/iiostack.asl b/src/soc/intel/xeon_sp/spr/acpi/iiostack.asl index 552f4c0..5c3d7ea 100644 --- a/src/soc/intel/xeon_sp/spr/acpi/iiostack.asl +++ b/src/soc/intel/xeon_sp/spr/acpi/iiostack.asl @@ -3,8 +3,6 @@ /* ***** PCI Stacks **** */ #undef DEVPREFIX #define DEVPREFIX PC -#undef STPREFIX -#define STPREFIX ST #undef PRTID #define PRTID AR00 diff --git a/src/soc/intel/xeon_sp/spr/acpi/pci_resource.asl b/src/soc/intel/xeon_sp/spr/acpi/pci_resource.asl index c65b699..fdb599e 100644 --- a/src/soc/intel/xeon_sp/spr/acpi/pci_resource.asl +++ b/src/soc/intel/xeon_sp/spr/acpi/pci_resource.asl @@ -13,10 +13,20 @@ Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) Name (_UID, IIO_DEVICE_UID(DEVPREFIX, SOCKET, STACK)) - External (\_SB.IIO_DEVICE_NAME(STPREFIX, SOCKET, STACK)) Method (_STA, 0, NotSerialized) { - Return (\_SB.IIO_DEVICE_NAME(STPREFIX, SOCKET, STACK)) + /* + * _CRS is being generated by SSDT for available stacks only and + * when missing the stack isn't available. + */ + If (CondRefOf (_CRS)) + { + Return (0xf) + } + Else + { + Return (0) + } } Method (_PRT, 0, NotSerialized) { diff --git a/src/soc/intel/xeon_sp/spr/soc_acpi.c b/src/soc/intel/xeon_sp/spr/soc_acpi.c index 0b6e491..607ee6c 100644 --- a/src/soc/intel/xeon_sp/spr/soc_acpi.c +++ b/src/soc/intel/xeon_sp/spr/soc_acpi.c @@ -53,70 +53,6 @@ fill_fadt_extended_pm_io(fadt); } -/* - * Add a DSDT ACPI Name field for STACK enable setting. - * This is retrieved by the device _STA defined in iiostack.asl - */ -static void create_dsdt_stack_sta(uint8_t socket, uint8_t stack, bool stack_enabled) -{ - char stack_sta[16]; - snprintf(stack_sta, sizeof(stack_sta), "ST%d%X", socket, stack); - - if (!stack_enabled) - acpigen_write_name_integer(stack_sta, ACPI_STATUS_DEVICE_ALL_OFF); - else - acpigen_write_name_integer(stack_sta, ACPI_STATUS_DEVICE_ALL_ON); -} - -void uncore_fill_ssdt(const struct device *device) -{ - bool stack_enabled; - - /* Only add RTxx entries once. */ - if (device->upstream->secondary != 0) - return; - - /* - Write stack scope - this needs to match RP ACPI scopes. - Stacks 0 (TYPE_UBOX_IIO) - Scope: PC<socket><stack>, ResourceTemplate: P0RS - Stacks 1 .. 5 (TYPE_UBOX_IIO) - Scope: PC<socket><stack> & CX<socket><stack>, ResourceTemplate: RBRS - Stacks 8 .. B (TYPE_DINO) - Scope: DI<socket><stack> for DINO, ResourceTemplate: RBRS - Scope: CP<socket><stack> for CPM (i.e., QAT), ResourceTemplate: RBRS - Scope: HQ<socket><stack> for HQM (i.e., DLB), ResourceTemplate: RBRS - Stacks D .. E (TYPE_UBOX) - Scope: UC<socket><0..1> for UBOX[1-2], ResourceTemplate: UNRS - */ - - printk(BIOS_DEBUG, "%s device: %s\n", __func__, dev_path(device)); - - /* The _CSR generation must match SPR iiostack.asl. */ - const IIO_UDS *hob = get_iio_uds(); - /* Iterate over CONFIG_MAX_SOCKET to keep ASL templates and DSDT injection in sync */ - for (uint8_t socket = 0; socket < CONFIG_MAX_SOCKET; ++socket) { - for (int stack = 0; stack < MAX_LOGIC_IIO_STACK; ++stack) { - const STACK_RES *ri = - &hob->PlatformData.IIO_resource[socket].StackRes[stack]; - - stack_enabled = soc_cpu_is_enabled(socket) && - ri->Personality < TYPE_RESERVED; - - printk(BIOS_DEBUG, "%s processing socket: %d, stack: %d, type: %d\n", - __func__, socket, stack, ri->Personality); - - if (stack <= IioStack5) { // TYPE_UBOX_IIO - create_dsdt_stack_sta(socket, stack, stack_enabled); - } else if (stack >= IioStack8 && stack <= IioStack11) { // TYPE_DINO - create_dsdt_stack_sta(socket, stack, stack_enabled); - } else if (stack == IioStack13) { // TYPE_UBOX - create_dsdt_stack_sta(socket, stack, stack_enabled); - } - } - } -} - /* TODO: See if we can use the common generate_p_state_entries */ void soc_power_states_generation(int core, int cores_per_package) { diff --git a/src/soc/intel/xeon_sp/uncore.c b/src/soc/intel/xeon_sp/uncore.c index 952ca4d..0eaff06 100644 --- a/src/soc/intel/xeon_sp/uncore.c +++ b/src/soc/intel/xeon_sp/uncore.c @@ -369,9 +369,6 @@ .enable_resources = pci_dev_enable_resources, .init = mmapvtd_init, .ops_pci = &soc_pci_ops, -#if CONFIG(HAVE_ACPI_TABLES) - .acpi_fill_ssdt = uncore_fill_ssdt, -#endif }; static const unsigned short mmapvtd_ids[] = { -- To view, visit https://review.coreboot.org/c/coreboot/+/81273?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib9051d608147f2de228509ff6b13871ca3183979 Gerrit-Change-Number: 81273 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: payload/external/edk2: Explicitly define the build arch
by Lean Sheng Tan (Code Review) 14 Mar '24

14 Mar '24

Attention is currently required from: Arthur Heymans, Arthur Heymans, Benjamin Doron, Martin L Roth, Matt DeVillier, Nicholas Sudsgaard. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80883?usp=email ) Change subject: payload/external/edk2: Explicitly define the build arch ...................................................................... Patch Set 6: (1 comment) Patchset: PS6: > Done Sorry for late reply: yes in the end we should not need Shimlayer for UPL build, once edk2 is transitioned to FDT. It might take. a few weeks before it got merged, but if you want to test out it is here: https://github.com/tianocore/edk2/pull/4969 Also coreboot will need to switch from coreboot table to FDT -- To view, visit https://review.coreboot.org/c/coreboot/+/80883?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icd942d0c15a99231d09f9cbdc5eb48333b6aa6e5 Gerrit-Change-Number: 80883 Gerrit-PatchSet: 6 Gerrit-Owner: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Thu, 14 Mar 2024 12:09:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sean Rhodes <sean(a)starlabs.systems> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: payload/external/edk2: Explicitly define the build arch
by Sean Rhodes (Code Review) 14 Mar '24

14 Mar '24

Attention is currently required from: Arthur Heymans, Arthur Heymans, Benjamin Doron, Lean Sheng Tan, Martin L Roth, Matt DeVillier. Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80883?usp=email ) The change is no longer submittable: Code-Review is unsatisfied now. Change subject: payload/external/edk2: Explicitly define the build arch ...................................................................... Patch Set 6: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/80883?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icd942d0c15a99231d09f9cbdc5eb48333b6aa6e5 Gerrit-Change-Number: 80883 Gerrit-PatchSet: 6 Gerrit-Owner: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Thu, 14 Mar 2024 12:05:47 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: payload/external/edk2: Explicitly define the build arch
by Nicholas Sudsgaard (Code Review) 14 Mar '24

14 Mar '24

Attention is currently required from: Arthur Heymans, Arthur Heymans, Benjamin Doron, Lean Sheng Tan, Martin L Roth, Matt DeVillier. Nicholas Sudsgaard has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80883?usp=email ) Change subject: payload/external/edk2: Explicitly define the build arch ...................................................................... Patch Set 6: (2 comments) Patchset: PS1: > > x86 always calls payloads in 32 bit mode even if the ramstage is 64bit. […] Done Patchset: PS4: > The UniversalPayload still makes assumptions about the arch, as I'm not sure how to make it more agn […] Scrapped -- To view, visit https://review.coreboot.org/c/coreboot/+/80883?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icd942d0c15a99231d09f9cbdc5eb48333b6aa6e5 Gerrit-Change-Number: 80883 Gerrit-PatchSet: 6 Gerrit-Owner: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Thu, 14 Mar 2024 12:02:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sean Rhodes <sean(a)starlabs.systems> Comment-In-Reply-To: Benjamin Doron <benjamin.doron00(a)gmail.com> Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com> Comment-In-Reply-To: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: payload/external/edk2: Explicitly define the build arch
by Sean Rhodes (Code Review) 14 Mar '24

14 Mar '24

Attention is currently required from: Arthur Heymans, Arthur Heymans, Benjamin Doron, Lean Sheng Tan, Martin L Roth, Matt DeVillier, Nicholas Sudsgaard. Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80883?usp=email ) Change subject: payload/external/edk2: Explicitly define the build arch ...................................................................... Patch Set 6: (2 comments) Patchset: PS3: > Seems to be some back and forth here. […] Done Patchset: PS6: > @Sheng, breaks Shimlayer build - but it doesn't seem to work anyway. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/80883?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icd942d0c15a99231d09f9cbdc5eb48333b6aa6e5 Gerrit-Change-Number: 80883 Gerrit-PatchSet: 6 Gerrit-Owner: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Thu, 14 Mar 2024 10:57:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sean Rhodes <sean(a)starlabs.systems> Comment-In-Reply-To: Benjamin Doron <benjamin.doron00(a)gmail.com> Comment-In-Reply-To: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Comment-In-Reply-To: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: payload/external/edk2: Explicitly define the build arch
by Sean Rhodes (Code Review) 14 Mar '24

14 Mar '24

Attention is currently required from: Arthur Heymans, Arthur Heymans, Lean Sheng Tan, Martin L Roth, Matt DeVillier, Nicholas Sudsgaard. Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80883?usp=email ) Change subject: payload/external/edk2: Explicitly define the build arch ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/80883?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icd942d0c15a99231d09f9cbdc5eb48333b6aa6e5 Gerrit-Change-Number: 80883 Gerrit-PatchSet: 6 Gerrit-Owner: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Thu, 14 Mar 2024 10:56:05 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/google/brox: Select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS
by Ashish Kumar Mishra (Code Review) 14 Mar '24

14 Mar '24

Attention is currently required from: Karthik Ramasubramanian, Shelley Chen. Ashish Kumar Mishra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81224?usp=email ) Change subject: mb/google/brox: Select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS ...................................................................... Patch Set 2: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/81224/comment/1919626c_b3b21aa4 : PS2, Line 14: None > Is this for b:329209576? Acknowledged https://review.coreboot.org/c/coreboot/+/81224/comment/98f31f48_379e450a : PS2, Line 16: Boot image on SKU2 and check S0ix working. > Have you checked that S0ix is still working on SKU1 as well? Checking on SKU1 WIP Patchset: PS2: > also, in order for this S0ix to work on SKU2, does this require a fitimage update to land with this […] No change required. -- To view, visit https://review.coreboot.org/c/coreboot/+/81224?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iabd0b3a83aa386e09310b671632368807a4018d4 Gerrit-Change-Number: 81224 Gerrit-PatchSet: 2 Gerrit-Owner: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Thu, 14 Mar 2024 10:54:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Shelley Chen <shchen(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: soc/intel/xeon_sp: Drop IIO_UDS argument
by Shuo Liu (Code Review) 14 Mar '24

14 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, Jincheng Li, Johnny Lin, Lean Sheng Tan, Patrick Rudolph, Tim Chu. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81181?usp=email ) Change subject: soc/intel/xeon_sp: Drop IIO_UDS argument ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81181?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I05ec127f2bf84d3c242c3b0bca9709a0a7a4b52b Gerrit-Change-Number: 81181 Gerrit-PatchSet: 6 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Thu, 14 Mar 2024 10:27:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: soc/intel/xeon_sp: Drop IIO_UDS argument
by Shuo Liu (Code Review) 14 Mar '24

14 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, Jincheng Li, Johnny Lin, Lean Sheng Tan, Shuo Liu, Tim Chu. Shuo Liu has uploaded a new patch set (#6) to the change originally created by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/81181?usp=email ) Change subject: soc/intel/xeon_sp: Drop IIO_UDS argument ...................................................................... soc/intel/xeon_sp: Drop IIO_UDS argument Use CONFIG_MAX_SOCKET instead of the IIO_UDS hob. Allows to drop the argument in Xeon-SP common layer. TEST=intel/archercity CRB Change-Id: I05ec127f2bf84d3c242c3b0bca9709a0a7a4b52b Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Signed-off-by: Jincheng Li <jincheng.li(a)intel.com> --- M src/soc/intel/xeon_sp/acpi.c M src/soc/intel/xeon_sp/chip_common.c M src/soc/intel/xeon_sp/uncore_acpi.c 3 files changed, 7 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/81181/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/81181?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I05ec127f2bf84d3c242c3b0bca9709a0a7a4b52b Gerrit-Change-Number: 81181 Gerrit-PatchSet: 6 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: soc/intel/xeon_sp: Add SATC PCI segment group support
by Shuo Liu (Code Review) 14 Mar '24

14 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Lean Sheng Tan, Patrick Rudolph, Tim Chu. Shuo Liu has uploaded a new patch set (#5) to the change originally created by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/81180?usp=email ) The change is no longer submittable: Code-Review is unsatisfied now. Change subject: soc/intel/xeon_sp: Add SATC PCI segment group support ...................................................................... soc/intel/xeon_sp: Add SATC PCI segment group support For every PCI segment group generate a new SATC header. Allows to generate proper ACPI code when multiple PCI segment groups are enabled. TEST=Booted on ibm/sbp1 with multiple PCI segment groups. Properly generates multiple SATC headers. TEST=intel/archercity CRB Change-Id: I93b8ee05a7e6798e034f7a5da2c6883f0ee7a0e5 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/intel/xeon_sp/uncore_acpi.c 1 file changed, 40 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/81180/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/81180?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I93b8ee05a7e6798e034f7a5da2c6883f0ee7a0e5 Gerrit-Change-Number: 81180 Gerrit-PatchSet: 5 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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