coreboot-gerrit March 2024

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[S] Change in coreboot[main]: drivers/intel/fsp2_0: Avoid unnecessary extra CBFS access
by Shuo Liu (Code Review) 14 Mar '24

14 Mar '24

Attention is currently required from: Andrey Petrov, Jérémy Compostella, Ronak Kanabar. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81256?usp=email ) Change subject: drivers/intel/fsp2_0: Avoid unnecessary extra CBFS access ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/81256?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If355b5811a09a0b76acc8a297db719d54caedc54 Gerrit-Change-Number: 81256 Gerrit-PatchSet: 3 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Comment-Date: Fri, 15 Mar 2024 02:17:09 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: drivers/intel/fsp2_0: Avoid unnecessary extra CBFS access
by Jérémy Compostella (Code Review) 14 Mar '24

14 Mar '24

Attention is currently required from: Andrey Petrov, Ronak Kanabar. Hello Andrey Petrov, Ronak Kanabar, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81256?usp=email to look at the new patch set (#3). Change subject: drivers/intel/fsp2_0: Avoid unnecessary extra CBFS access ...................................................................... drivers/intel/fsp2_0: Avoid unnecessary extra CBFS access fsp_mrc_version() function does not need to perform a CBFS access to to get an address to the FSP-M blob as the caller, do_fsp_memory_init(), already has it loaded. In addition to make the code simpler, it avoids an unnecessary decompression of the FSP blob if `FSP_COMPRESS_FSP_M_LZ4' or `FSP_COMPRESS_FSP_M_LZMA' are set. TEST=Verified on Meteor Lake rex Change-Id: If355b5811a09a0b76acc8a297db719d54caedc54 Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- M src/drivers/intel/fsp2_0/memory_init.c 1 file changed, 3 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/81256/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/81256?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If355b5811a09a0b76acc8a297db719d54caedc54 Gerrit-Change-Number: 81256 Gerrit-PatchSet: 3 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: mb/google/brya: Create bujia variant
by Eric Lai (Code Review) 14 Mar '24

14 Mar '24

Attention is currently required from: Derek Huang, Dinesh Gehlot, Kapil Porwal, Nick Vaccaro, Shon Wang, Subrata Banik. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81198?usp=email ) Change subject: mb/google/brya: Create bujia variant ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81198?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I453a50f1aa64f8d4119bf0f860d928aa3e00a144 Gerrit-Change-Number: 81198 Gerrit-PatchSet: 7 Gerrit-Owner: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Derek Huang <derekhuang(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Fri, 15 Mar 2024 01:59:40 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/google/nissa/var/glassway: Tune I2C timings for 400 kHz
by Frank Chu (Code Review) 14 Mar '24

14 Mar '24

Attention is currently required from: Dinesh Gehlot, Kapil Porwal, Nick Vaccaro, Paul Menzel, Subrata Banik. Frank Chu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81136?usp=email ) Change subject: mb/google/nissa/var/glassway: Tune I2C timings for 400 kHz ...................................................................... Patch Set 11: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/81136?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I65fb1298f9e96ab0b63aba436f6a319f21b38925 Gerrit-Change-Number: 81136 Gerrit-PatchSet: 11 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Shawn Ku <shawnku(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Fri, 15 Mar 2024 01:59:01 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/google/nissa/var/glassway: Tune I2C timings for 400 kHz
by Frank Chu (Code Review) 14 Mar '24

14 Mar '24

Attention is currently required from: Dinesh Gehlot, Kapil Porwal, Nick Vaccaro, Paul Menzel, Subrata Banik. Frank Chu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81136?usp=email ) Change subject: mb/google/nissa/var/glassway: Tune I2C timings for 400 kHz ...................................................................... Patch Set 11: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81136?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I65fb1298f9e96ab0b63aba436f6a319f21b38925 Gerrit-Change-Number: 81136 Gerrit-PatchSet: 11 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Shawn Ku <shawnku(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Fri, 15 Mar 2024 01:58:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/google/nissa/var/glassway: Tune I2C timings for 400 kHz
by Frank Chu (Code Review) 14 Mar '24

14 Mar '24

Attention is currently required from: Dinesh Gehlot, Kapil Porwal, Nick Vaccaro, Paul Menzel, Subrata Banik. Frank Chu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81136?usp=email ) Change subject: mb/google/nissa/var/glassway: Tune I2C timings for 400 kHz ...................................................................... Patch Set 11: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/81136?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I65fb1298f9e96ab0b63aba436f6a319f21b38925 Gerrit-Change-Number: 81136 Gerrit-PatchSet: 11 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Shawn Ku <shawnku(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Fri, 15 Mar 2024 01:58:07 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: drivers/intel/fsp2_0: Avoid unnecessary extra CBFS access
by Jérémy Compostella (Code Review) 14 Mar '24

14 Mar '24

Attention is currently required from: Andrey Petrov, Ronak Kanabar. Hello Andrey Petrov, Ronak Kanabar, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81256?usp=email to look at the new patch set (#2). Change subject: drivers/intel/fsp2_0: Avoid unnecessary extra CBFS access ...................................................................... drivers/intel/fsp2_0: Avoid unnecessary extra CBFS access fsp_mrc_version() function does not need to perform a CBFS access to to get an address to the FSP-M blob as the caller, do_fsp_memory_init(), already has it loaded. In addition to make the code simpler, it avoids an unnecessary decompression of the FSP blob if `FSP_COMPRESS_FSP_M_LZ4' or `FSP_COMPRESS_FSP_M_LZMA' are set. TEST=Verified on Meteor Lake rex Change-Id: If355b5811a09a0b76acc8a297db719d54caedc54 Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- M src/drivers/intel/fsp2_0/memory_init.c 1 file changed, 2 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/81256/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81256?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If355b5811a09a0b76acc8a297db719d54caedc54 Gerrit-Change-Number: 81256 Gerrit-PatchSet: 2 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[main]: soc/intel/xeon_sp/spr: Rewrite acpi_fill_cedt
by Shuo Liu (Code Review) 14 Mar '24

14 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Lean Sheng Tan, Patrick Rudolph, Tim Chu. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81274?usp=email ) Change subject: soc/intel/xeon_sp/spr: Rewrite acpi_fill_cedt ...................................................................... Patch Set 2: Code-Review+1 (2 comments) File src/soc/intel/xeon_sp/uncore_acpi.c: https://review.coreboot.org/c/coreboot/+/81274/comment/7a50d8af_ea87c5ec : PS2, Line 599: /* FIXME: Use define for resource index */ it would be good if we could have a such patch ahead of time https://review.coreboot.org/c/coreboot/+/81274/comment/3ac63ea9_ffa32534 : PS2, Line 612: Do you have CXL card to test this? -- To view, visit https://review.coreboot.org/c/coreboot/+/81274?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1a1ad0386523862a075eec478a3d785fa7423b45 Gerrit-Change-Number: 81274 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 15 Mar 2024 01:47:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: drivers/pc80/tpm: Support Xeon-SP
by Shuo Liu (Code Review) 14 Mar '24

14 Mar '24

Attention is currently required from: Christian Walter, Patrick Rudolph. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81276?usp=email ) Change subject: drivers/pc80/tpm: Support Xeon-SP ...................................................................... Patch Set 2: Code-Review+1 (1 comment) Patchset: PS2: Windows requires the domain0 is named as PCI0 so that we might need another patch to fix in domain name generation (needs to test with Windows boot). But as a standalone solution, I think this patch should be okay. With this patch, on SPR/LinuxBoot, is there any log/function changes around TPM? -- To view, visit https://review.coreboot.org/c/coreboot/+/81276?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6130b937ec81bbde78d2619eb859ecf354fc3854 Gerrit-Change-Number: 81276 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Comment-Date: Fri, 15 Mar 2024 01:28:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: drivers/intel/fsp2_0: Avoid unnecessary extra CBFS access
by Jérémy Compostella (Code Review) 14 Mar '24

14 Mar '24

Jérémy Compostella has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81256?usp=email ) Change subject: drivers/intel/fsp2_0: Avoid unnecessary extra CBFS access ...................................................................... drivers/intel/fsp2_0: Avoid unnecessary extra CBFS access fsp_mrc_version() function does not need to perform a CBFS access to to get an address to the FSP-M blob as the caller, do_fsp_memory_init(), already has it loaded. In addition to make the code simpler, it avoids an unnecessary decompression of the FSP blob if `FSP_COMPRESS_FSP_M_LZ4' or `FSP_COMPRESS_FSP_M_LZMA' are set. TEST=Verified on Meteor Lake rex Change-Id: If355b5811a09a0b76acc8a297db719d54caedc54 Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- M src/drivers/intel/fsp2_0/memory_init.c 1 file changed, 2 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/81256/1 diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index 922bca2..53155ca 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -260,23 +260,16 @@ * MRC version is by reading the FSP_PRODUCDER_DATA_TABLES * from the FSP-M binary (by parsing the FSP header). */ -static uint32_t fsp_mrc_version(void) +static uint32_t fsp_mrc_version(void *fspm_blob_file) { uint32_t ver = 0; #if CONFIG(MRC_CACHE_USING_MRC_VERSION) - size_t fspm_blob_size; - const char *fspm_cbfs = soc_select_fsp_m_cbfs(); - void *fspm_blob_file = cbfs_map(fspm_cbfs, &fspm_blob_size); - if (!fspm_blob_file) - return 0; - FSP_PRODUCER_DATA_TABLES *ft = fspm_blob_file + FSP_HDR_OFFSET; FSP_PRODUCER_DATA_TYPE2 *table2 = &ft->FspProduceDataType2; size_t mrc_version_size = sizeof(table2->MrcVersion); for (size_t i = 0; i < mrc_version_size; i++) { ver |= (table2->MrcVersion[i] << ((mrc_version_size - 1) - i) * 8); } - cbfs_unmap(fspm_blob_file); #endif return ver; } @@ -350,7 +343,7 @@ post_code(POSTCODE_MEM_PREINIT_PREP_START); if (CONFIG(MRC_CACHE_USING_MRC_VERSION)) - version = fsp_mrc_version(); + version = fsp_mrc_version((void *)hdr->image_base); else version = fsp_memory_settings_version(hdr); -- To view, visit https://review.coreboot.org/c/coreboot/+/81256?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If355b5811a09a0b76acc8a297db719d54caedc54 Gerrit-Change-Number: 81256 Gerrit-PatchSet: 1 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-MessageType: newchange

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coreboot-gerrit March 2024