coreboot-gerrit March 2024

coreboot-gerrit@coreboot.org

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[L] Change in coreboot[main]: treewide: Move stdlib.h to commonlib
by Lean Sheng Tan (Code Review) 15 Mar '24

15 Mar '24

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/77969?usp=email ) ( 30 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: treewide: Move stdlib.h to commonlib ...................................................................... treewide: Move stdlib.h to commonlib This patch moves commonlib/stdlib.h -> commonlib/bsd/stdlib.h, since all code is BSD licensed anyway. It also moves some code from libpayloads stdlib.h to commonlib/bsd/stdlib.h so that it can be shared with coreboot. This is useful for a subsequent commit that adds devicetree.c into commonlib. Also we don't support DMA on arm platforms in coreboot (only libpayload) therefore `dma_malloc()` has been removed and `dma_coherent()` has been moved to architecture specific functions. Any architecture that tries to use `dma_coherent()` now will get a compile time error. In order to not break current platforms like mb/google/herobrine which make use of the commonlib/storage/sdhci.c controller which in turn uses `dma_coherent` a stub has been added to arch/arm64/dma.c. Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> Change-Id: I3a7ab0d1ddcc7ce9af121a61b4d4eafc9e563a8a Reviewed-on: https://review.coreboot.org/c/coreboot/+/77969 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- M Makefile.mk M payloads/external/BOOTBOOT/Makefile M payloads/libpayload/include/die.h M payloads/libpayload/include/libpayload.h M payloads/libpayload/include/stdlib.h M payloads/libpayload/libc/Makefile.mk D payloads/libpayload/libc/die.c M payloads/libpayload/libc/lib.c D payloads/libpayload/tests/mocks/die.c M src/Kconfig M src/arch/arm64/Makefile.mk A src/arch/arm64/dma.c M src/arch/ppc64/include/arch/hlt.h M src/arch/riscv/include/arch/hlt.h M src/arch/x86/Makefile.mk A src/arch/x86/dma.c A src/commonlib/bsd/include/commonlib/bsd/stdlib.h D src/commonlib/include/commonlib/stdlib.h M src/commonlib/storage/bouncebuf.c M src/commonlib/storage/sdhci.c M src/drivers/intel/fsp2_0/silicon_init.c M src/include/halt.h M src/include/stdlib.h M src/lib/device_tree.c M src/lib/fit.c M src/lib/halt.c M src/lib/libgcov.c M src/soc/intel/xeon_sp/acpi.c M src/soc/intel/xeon_sp/numa.c M src/soc/mediatek/common/pcie.c M src/soc/mediatek/mt8195/pcie.c M tests/Makefile.common 32 files changed, 127 insertions(+), 198 deletions(-) Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved diff --git a/Makefile.mk b/Makefile.mk index f7b98c7..73fb40b 100644 --- a/Makefile.mk +++ b/Makefile.mk @@ -481,6 +481,7 @@ CPPFLAGS_common += -include $(src)/commonlib/bsd/include/commonlib/bsd/compiler.h CPPFLAGS_common += -I3rdparty CPPFLAGS_common += -D__BUILD_DIR__=\"$(obj)\" +CPPFLAGS_common += -D__COREBOOT__ ifeq ($(BUILD_TIMELESS),1) CPPFLAGS_common += -D__TIMELESS__ diff --git a/payloads/external/BOOTBOOT/Makefile b/payloads/external/BOOTBOOT/Makefile index 2460c18..3bf5b54 100644 --- a/payloads/external/BOOTBOOT/Makefile +++ b/payloads/external/BOOTBOOT/Makefile @@ -1,8 +1,5 @@ project_git_repo=https://gitlab.com/bztsrc/bootboot.git project_dir=bootboot -ifeq ($(CONFIG_COREBOOT_BUILD),) -include ../../../.config -endif ifeq ($(CONFIG_ARCH_ARM64),y) loader_dir=$(project_dir)/aarch64-cb else diff --git a/payloads/libpayload/include/die.h b/payloads/libpayload/include/die.h index 01469de..fb61d4a 100644 --- a/payloads/libpayload/include/die.h +++ b/payloads/libpayload/include/die.h @@ -29,13 +29,14 @@ #ifndef __DIE_H__ #define __DIE_H__ -void die_work(const char *file, const char *func, const int line, - const char *fmt, ...) - __attribute__((format (printf, 4, 5))) - __attribute__((noreturn)); +#include <stdio.h> +#include <stdlib.h> #define die(fmt, args...) \ - do { die_work(__FILE__, __func__, __LINE__, fmt, ##args); } \ + do { \ + printf("%s:%d %s(): " fmt, __FILE__, __LINE__, __func__, ##args); \ + abort(); \ + } \ while (0) #define die_if(condition, fmt, args...) \ diff --git a/payloads/libpayload/include/libpayload.h b/payloads/libpayload/include/libpayload.h index 05164e5..c6d2fc6 100644 --- a/payloads/libpayload/include/libpayload.h +++ b/payloads/libpayload/include/libpayload.h @@ -525,4 +525,15 @@ /* Defined in arch/${ARCH}/selfboot.c */ void selfboot(void *entry); +/* Enter remote GDB mode. Will initialize connection if not already up. */ +void gdb_enter(void); +/* Disconnect existing GDB connection if one exists. */ +void gdb_exit(s8 exit_status); + +void __noreturn halt(void); +#if CONFIG(LP_REMOTEGDB) +/* Override abort()/halt() to trap into GDB if it is enabled. */ +#define halt() do { gdb_enter(); halt(); } while (0) +#endif + #endif diff --git a/payloads/libpayload/include/stdlib.h b/payloads/libpayload/include/stdlib.h index cb9addf..319e5a4 100644 --- a/payloads/libpayload/include/stdlib.h +++ b/payloads/libpayload/include/stdlib.h @@ -30,6 +30,7 @@ #ifndef _STDLIB_H #define _STDLIB_H +#include <commonlib/bsd/stdlib.h> #include <die.h> #include <stddef.h> #include <string.h> @@ -38,11 +39,7 @@ * @defgroup malloc Memory allocation functions * @{ */ -void free(void *ptr); -void *malloc(size_t size); -void *calloc(size_t nmemb, size_t size); void *realloc(void *ptr, size_t size); -void *memalign(size_t align, size_t size); void *dma_malloc(size_t size); void *dma_memalign(size_t align, size_t size); @@ -136,43 +133,8 @@ void init_dma_memory(void *start, u32 size); int dma_initialized(void); -int dma_coherent(const void *ptr); void dma_allocator_range(void **start_out, size_t *size_out); -static inline void *xmalloc_work(size_t size, const char *file, - const char *func, int line) -{ - void *ret = malloc(size); - if (!ret && size) { - die_work(file, func, line, "Failed to malloc %zu bytes.\n", - size); - } - return ret; -} -#define xmalloc(size) xmalloc_work((size), __FILE__, __func__, __LINE__) - -static inline void *xzalloc_work(size_t size, const char *file, - const char *func, int line) -{ - void *ret = xmalloc_work(size, file, func, line); - memset(ret, 0, size); - return ret; -} -#define xzalloc(size) xzalloc_work((size), __FILE__, __func__, __LINE__) - -static inline void *xmemalign_work(size_t align, size_t size, const char *file, - const char *func, int line) -{ - void *ret = memalign(align, size); - if (!ret && size) { - die_work(file, func, line, - "Failed to memalign %zu bytes with %zu alignment.\n", - size, align); - } - return ret; -} -#define xmemalign(align, size) \ - xmemalign_work((align), (size), __FILE__, __func__, __LINE__) /** @} */ /** @@ -205,22 +167,6 @@ long long int llabs(long long int j); /** @} */ -/* Enter remote GDB mode. Will initialize connection if not already up. */ -void gdb_enter(void); -/* Disconnect existing GDB connection if one exists. */ -void gdb_exit(s8 exit_status); - -/** - * Stop execution and halt the processor (this function does not return). - */ -void halt(void) __attribute__((noreturn)); -void exit(int status) __attribute__((noreturn)); -#define abort() halt() /**< Alias for the halt() function */ -#if CONFIG(LP_REMOTEGDB) -/* Override abort()/halt() to trap into GDB if it is enabled. */ -#define halt() do { gdb_enter(); halt(); } while (0) -#endif - void qsort(void *aa, size_t n, size_t es, int (*cmp)(const void *, const void *)); char *getenv(const char*); uint64_t __umoddi3(uint64_t num, uint64_t den); @@ -228,4 +174,6 @@ uint64_t __ashldi3(uint64_t num, unsigned shift); uint64_t __lshrdi3(uint64_t num, unsigned shift); +void __noreturn exit(int status); + #endif diff --git a/payloads/libpayload/libc/Makefile.mk b/payloads/libpayload/libc/Makefile.mk index 6ff1eb8..2840476 100644 --- a/payloads/libpayload/libc/Makefile.mk +++ b/payloads/libpayload/libc/Makefile.mk @@ -35,7 +35,6 @@ libc-$(CONFIG_LP_LIBC) += strlcpy.c libc-$(CONFIG_LP_LIBC) += qsort.c libc-$(CONFIG_LP_LIBC) += hexdump.c -libc-$(CONFIG_LP_LIBC) += die.c libc-$(CONFIG_LP_LIBC) += coreboot.c libc-$(CONFIG_LP_LIBC) += fmap.c libc-$(CONFIG_LP_LIBC) += fpmath.c diff --git a/payloads/libpayload/libc/die.c b/payloads/libpayload/libc/die.c deleted file mode 100644 index 0a5b97b..0000000 --- a/payloads/libpayload/libc/die.c +++ /dev/null @@ -1,41 +0,0 @@ -/* - * - * Copyright 2013 Google Inc. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#include <libpayload.h> - -void die_work(const char *file, const char *func, const int line, - const char *fmt, ...) -{ - va_list args; - - printf("%s:%d %s(): ", file, line, func); - va_start(args, fmt); - vprintf(fmt, args); - va_end(args); - abort(); -} diff --git a/payloads/libpayload/libc/lib.c b/payloads/libpayload/libc/lib.c index dc212e7..f1d8574 100644 --- a/payloads/libpayload/libc/lib.c +++ b/payloads/libpayload/libc/lib.c @@ -119,6 +119,11 @@ halt(); } +void __noreturn abort(void) +{ + halt(); +} + int errno; char *getenv(const char *name) diff --git a/payloads/libpayload/tests/mocks/die.c b/payloads/libpayload/tests/mocks/die.c deleted file mode 100644 index a67105a..0000000 --- a/payloads/libpayload/tests/mocks/die.c +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <tests/test.h> -#include <stdbool.h> - -void die_work(const char *file, const char *func, int line, const char *fmt, ...) -{ - /* Failing asserts are jumping to the user code (test) if expect_assert_failed() was - previously called. Otherwise it jumps to the cmocka code and fails the test. */ - mock_assert(false, "Mock assetion called", file, line); - - /* Should never be reached */ - print_error("%s() called...\n", __func__); - while (1) - ; -} diff --git a/src/Kconfig b/src/Kconfig index 2afb9db..c895492 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -4,10 +4,6 @@ menu "General setup" -config COREBOOT_BUILD - bool - default y - config LOCALVERSION string "Local version string" help diff --git a/src/arch/arm64/Makefile.mk b/src/arch/arm64/Makefile.mk index 538d254..2986397 100644 --- a/src/arch/arm64/Makefile.mk +++ b/src/arch/arm64/Makefile.mk @@ -119,6 +119,7 @@ ramstage-y += transition.c transition_asm.S ramstage-$(CONFIG_PAYLOAD_FIT_SUPPORT) += fit_payload.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c +ramstage-y += dma.c rmodules_arm64-y += memset.S rmodules_arm64-y += memcpy.S diff --git a/src/arch/arm64/dma.c b/src/arch/arm64/dma.c new file mode 100644 index 0000000..cdeb50f --- /dev/null +++ b/src/arch/arm64/dma.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <stdlib.h> + +int dma_coherent(const void *ptr) +{ + return 0; +} diff --git a/src/arch/ppc64/include/arch/hlt.h b/src/arch/ppc64/include/arch/hlt.h index 397b3cc..2839805 100644 --- a/src/arch/ppc64/include/arch/hlt.h +++ b/src/arch/ppc64/include/arch/hlt.h @@ -1,7 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef ARCH_HLT_H +#define ARCH_HLT_H + static __always_inline void hlt(void) { while (1) ; } + +#endif /* ARCH_HLT_H */ diff --git a/src/arch/riscv/include/arch/hlt.h b/src/arch/riscv/include/arch/hlt.h index bdefbb5..b2643fd 100644 --- a/src/arch/riscv/include/arch/hlt.h +++ b/src/arch/riscv/include/arch/hlt.h @@ -1,6 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef ARCH_HLT_H +#define ARCH_HLT_H + static __always_inline void hlt(void) { while (1); } + +#endif /* ARCH_HLT_H */ diff --git a/src/arch/x86/Makefile.mk b/src/arch/x86/Makefile.mk index 04a0e58..1994546 100644 --- a/src/arch/x86/Makefile.mk +++ b/src/arch/x86/Makefile.mk @@ -261,6 +261,7 @@ ramstage-y += exception.c ramstage-y += idt.S ramstage-$(CONFIG_IOAPIC) += ioapic.c +ramstage-y += dma.c ramstage-y += memcpy.c ramstage-$(CONFIG_ARCH_RAMSTAGE_X86_32) += memmove_32.c ramstage-$(CONFIG_ARCH_RAMSTAGE_X86_64) += memmove_64.S diff --git a/src/arch/x86/dma.c b/src/arch/x86/dma.c new file mode 100644 index 0000000..b39ac2c --- /dev/null +++ b/src/arch/x86/dma.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <stdlib.h> + +int dma_coherent(const void *ptr) +{ + return 1; +} diff --git a/src/commonlib/bsd/include/commonlib/bsd/stdlib.h b/src/commonlib/bsd/include/commonlib/bsd/stdlib.h new file mode 100644 index 0000000..c497b5c --- /dev/null +++ b/src/commonlib/bsd/include/commonlib/bsd/stdlib.h @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +#ifndef __COMMONLIB_STDLIB_H__ +#define __COMMONLIB_STDLIB_H__ + +#include <stddef.h> +#include <string.h> + +#ifdef __COREBOOT__ +#include <console/console.h> +#else +#include <stdio.h> +#define printk(level, ...) printf(__VA_ARGS__) +#endif + +void __noreturn abort(void); +void free(void *ptr); +void *malloc(size_t size); +void *calloc(size_t nitems, size_t size); +void *memalign(size_t align, size_t size); +int dma_coherent(const void *ptr); + +static inline void *xmalloc_work(size_t size, const char *file, const char *func, int line) +{ + void *ret = malloc(size); + if (!ret && size) { + printk(BIOS_ERR, "%s:%d %s(): Failed to malloc %zu bytes\n", + file, line, func, size); + abort(); + } + return ret; +} +#define xmalloc(size) xmalloc_work((size), __FILE__, __func__, __LINE__) + +static inline void *xzalloc_work(size_t size, const char *file, const char *func, int line) +{ + void *ret = xmalloc_work(size, file, func, line); + memset(ret, 0, size); + return ret; +} +#define xzalloc(size) xzalloc_work((size), __FILE__, __func__, __LINE__) + +static inline void *xmemalign_work(size_t align, size_t size, const char *file, + const char *func, int line) +{ + void *ret = memalign(align, size); + if (!ret && size) { + printk(BIOS_ERR, "%s:%d %s(): " + "Failed to memalign %zu bytes with %zu alignment.\n", + file, line, func, size, align); + abort(); + } + return ret; +} +#define xmemalign(align, size) xmemalign_work((align), (size), __FILE__, __func__, __LINE__) + +#endif /* __COMMONLIB_STDLIB_H__ */ diff --git a/src/commonlib/include/commonlib/stdlib.h b/src/commonlib/include/commonlib/stdlib.h deleted file mode 100644 index 374fe16..0000000 --- a/src/commonlib/include/commonlib/stdlib.h +++ /dev/null @@ -1,46 +0,0 @@ -/* SPDX-License-Identifier: BSD-3-Clause */ - -#ifndef __COMMONLIB_STDLIB_H__ -#define __COMMONLIB_STDLIB_H__ - -#include <stddef.h> -#include <stdlib.h> -#include <string.h> - -#if CONFIG(COREBOOT_BUILD) -#include <console/console.h> -#include <halt.h> -#define HALT(x) halt() -#else -#include <stdio.h> -#define printk(level, ...) printf(__VA_ARGS__) -#define HALT(x) abort() -#endif - -static inline void *xmalloc_work(size_t size, const char *file, - const char *func, int line) -{ - void *ret = malloc(size); - if (!ret && size) { - printk(BIOS_ERR, "%s/%s/line %d: Failed to malloc %zu bytes\n", - file, func, line, size); - while (1) - HALT(1); - } - return ret; -} -#define xmalloc(size) xmalloc_work((size), __FILE__, __func__, __LINE__) - -static inline void *xzalloc_work(size_t size, const char *file, - const char *func, int line) -{ - void *ret = xmalloc_work(size, file, func, line); - memset(ret, 0, size); - return ret; -} -#define xzalloc(size) xzalloc_work((size), __FILE__, __func__, __LINE__) - -void *dma_malloc(size_t size); -int dma_coherent(void *ptr); - -#endif /* __COMMONLIB_STDLIB_H__ */ diff --git a/src/commonlib/storage/bouncebuf.c b/src/commonlib/storage/bouncebuf.c index 9edf41a..a0a379e 100644 --- a/src/commonlib/storage/bouncebuf.c +++ b/src/commonlib/storage/bouncebuf.c @@ -7,7 +7,7 @@ #include "bouncebuf.h" #include "storage.h" #include <string.h> -#include <commonlib/stdlib.h> +#include <commonlib/bsd/stdlib.h> static int addr_aligned(struct bounce_buffer *state) { diff --git a/src/commonlib/storage/sdhci.c b/src/commonlib/storage/sdhci.c index 410d4fc..fbc6c98 100644 --- a/src/commonlib/storage/sdhci.c +++ b/src/commonlib/storage/sdhci.c @@ -6,7 +6,7 @@ #include "bouncebuf.h" #include <commonlib/sd_mmc_ctrlr.h> #include <commonlib/sdhci.h> -#include <commonlib/stdlib.h> +#include <commonlib/bsd/stdlib.h> #include <commonlib/storage.h> #include <delay.h> #include <endian.h> @@ -21,11 +21,6 @@ || (CONFIG(SDHCI_ADMA_IN_ROMSTAGE) && ENV_SEPARATE_ROMSTAGE) \ || ENV_POSTCAR || ENV_RAMSTAGE) -__weak void *dma_malloc(size_t length_in_bytes) -{ - return malloc(length_in_bytes); -} - void sdhci_reset(struct sdhci_ctrlr *sdhci_ctrlr, u8 mask) { struct stopwatch sw; diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c index ab51571..08258d3 100644 --- a/src/drivers/intel/fsp2_0/silicon_init.c +++ b/src/drivers/intel/fsp2_0/silicon_init.c @@ -5,7 +5,7 @@ #include <cbfs.h> #include <cbmem.h> #include <commonlib/fsp.h> -#include <commonlib/stdlib.h> +#include <stdlib.h> #include <console/console.h> #include <fsp/api.h> #include <fsp/util.h> diff --git a/src/include/halt.h b/src/include/halt.h index a00975b..cb691a2 100644 --- a/src/include/halt.h +++ b/src/include/halt.h @@ -3,10 +3,13 @@ #ifndef __HALT_H__ #define __HALT_H__ -/** - * halt the system reliably - */ -void __noreturn halt(void); +#include <arch/hlt.h> +#include <commonlib/bsd/stdlib.h> + +static inline __noreturn void halt(void) +{ + abort(); +} /* Power off the system. */ void poweroff(void); diff --git a/src/include/stdlib.h b/src/include/stdlib.h index 8fa5d20..8e62f27 100644 --- a/src/include/stdlib.h +++ b/src/include/stdlib.h @@ -3,11 +3,7 @@ #ifndef STDLIB_H #define STDLIB_H +#include <commonlib/bsd/stdlib.h> #include <stddef.h> -void *memalign(size_t boundary, size_t size); -void *malloc(size_t size); -void *calloc(size_t nitems, size_t size); -void free(void *ptr); - #endif /* STDLIB_H */ diff --git a/src/lib/device_tree.c b/src/lib/device_tree.c index ab9c937b..a367986 100644 --- a/src/lib/device_tree.c +++ b/src/lib/device_tree.c @@ -2,7 +2,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <assert.h> -#include <commonlib/stdlib.h> #include <console/console.h> #include <ctype.h> #include <device_tree.h> diff --git a/src/lib/fit.c b/src/lib/fit.c index 9db083e..46ac972 100644 --- a/src/lib/fit.c +++ b/src/lib/fit.c @@ -12,7 +12,7 @@ #include <memrange.h> #include <fit.h> #include <boardid.h> -#include <commonlib/stdlib.h> +#include <stdlib.h> #include <types.h> static struct list_node image_nodes; diff --git a/src/lib/halt.c b/src/lib/halt.c index 8d9e5c8..441f5bb 100644 --- a/src/lib/halt.c +++ b/src/lib/halt.c @@ -3,7 +3,7 @@ #include <arch/hlt.h> #include <halt.h> -void halt(void) +void __noreturn abort(void) { while (1) hlt(); diff --git a/src/lib/libgcov.c b/src/lib/libgcov.c index b0c8161..61304ff 100644 --- a/src/lib/libgcov.c +++ b/src/lib/libgcov.c @@ -23,7 +23,6 @@ 3.1, as published by the Free Software Foundation. */ -#define __COREBOOT__ #ifdef __COREBOOT__ #include <stdlib.h> #include <string.h> diff --git a/src/soc/intel/xeon_sp/acpi.c b/src/soc/intel/xeon_sp/acpi.c index 11913d3..de63ced 100644 --- a/src/soc/intel/xeon_sp/acpi.c +++ b/src/soc/intel/xeon_sp/acpi.c @@ -1,12 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <assert.h> -#include <commonlib/stdlib.h> #include <intelblocks/acpi.h> #include <soc/chip_common.h> #include <soc/pci_devs.h> #include <soc/util.h> #include <stdint.h> +#include <stdlib.h> #include "chip.h" diff --git a/src/soc/intel/xeon_sp/numa.c b/src/soc/intel/xeon_sp/numa.c index 23f52c6..62657dc 100644 --- a/src/soc/intel/xeon_sp/numa.c +++ b/src/soc/intel/xeon_sp/numa.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <console/console.h> -#include <commonlib/stdlib.h> #include <device/device.h> #include <device/pci_ops.h> #include <device/pci.h> diff --git a/src/soc/mediatek/common/pcie.c b/src/soc/mediatek/common/pcie.c index b3903a5..10bece9 100644 --- a/src/soc/mediatek/common/pcie.c +++ b/src/soc/mediatek/common/pcie.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <boot/coreboot_tables.h> -#include <commonlib/stdlib.h> #include <console/console.h> #include <device/device.h> #include <device/mmio.h> @@ -15,7 +14,6 @@ #include <soc/pcie.h> #include <soc/pcie_common.h> #include <soc/soc_chip.h> -#include <stdlib.h> #include <types.h> #define PCIE_SETTING_REG 0x80 diff --git a/src/soc/mediatek/mt8195/pcie.c b/src/soc/mediatek/mt8195/pcie.c index c9f8ecd..cb36f8d 100644 --- a/src/soc/mediatek/mt8195/pcie.c +++ b/src/soc/mediatek/mt8195/pcie.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only OR MIT */ -#include <commonlib/stdlib.h> #include <console/console.h> #include <device/mmio.h> #include <device/resource.h> diff --git a/tests/Makefile.common b/tests/Makefile.common index ace16d2..d6c9bd6 100644 --- a/tests/Makefile.common +++ b/tests/Makefile.common @@ -59,7 +59,7 @@ TEST_CFLAGS += -Os endif -TEST_CFLAGS += -D__TEST__ +TEST_CFLAGS += -D__TEST__ -D__COREBOOT__ ifneq ($(filter-out 0,$(TEST_PRINT)),) TEST_CFLAGS += -DTEST_PRINT=1 -- To view, visit https://review.coreboot.org/c/coreboot/+/77969?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3a7ab0d1ddcc7ce9af121a61b4d4eafc9e563a8a Gerrit-Change-Number: 77969 Gerrit-PatchSet: 32 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: arch/x86/include/arch: Add feature check macros
by Jincheng Li (Code Review) 15 Mar '24

15 Mar '24

Attention is currently required from: Arthur Heymans, Jérémy Compostella, Patrick Rudolph. Jincheng Li has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81133?usp=email ) Change subject: arch/x86/include/arch: Add feature check macros ...................................................................... Patch Set 3: (1 comment) File src/arch/x86/include/arch/cpu.h: https://review.coreboot.org/c/coreboot/+/81133/comment/57ce0f2f_30215c3b : PS1, Line 54: #define CPUID_FEATURE_HTT (1 << 28) > The typo fix should in a separate clean-up patch. […] Done in https://review.coreboot.org/c/coreboot/+/81260 -- To view, visit https://review.coreboot.org/c/coreboot/+/81133?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I014c25ced1dbe21f35486f8305b1de7669e932d0 Gerrit-Change-Number: 81133 Gerrit-PatchSet: 3 Gerrit-Owner: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Fri, 15 Mar 2024 09:39:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-MessageType: comment

1 0

[XS] Change in coreboot[main]: arch/x86/include/arch: Add feature check macros
by Shuo Liu (Code Review) 15 Mar '24

15 Mar '24

Attention is currently required from: Arthur Heymans, Jincheng Li, Jérémy Compostella, Patrick Rudolph. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81133?usp=email ) Change subject: arch/x86/include/arch: Add feature check macros ...................................................................... Patch Set 3: (1 comment) File src/arch/x86/include/arch/cpu.h: https://review.coreboot.org/c/coreboot/+/81133/comment/e3aa654b_189c9862 : PS1, Line 51: CPUID_FEATURE_MCE > It's unused. […] This is referenced in GNR codes, but not critical. We can leave this to later. -- To view, visit https://review.coreboot.org/c/coreboot/+/81133?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I014c25ced1dbe21f35486f8305b1de7669e932d0 Gerrit-Change-Number: 81133 Gerrit-PatchSet: 3 Gerrit-Owner: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Comment-Date: Fri, 15 Mar 2024 09:32:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: comment

1 0

[XS] Change in coreboot[main]: arch/x86/include/arch: Add feature check macros
by Jincheng Li (Code Review) 15 Mar '24

15 Mar '24

Attention is currently required from: Arthur Heymans, Jincheng Li, Jérémy Compostella, Shuo Liu. Hello Arthur Heymans, Jérémy Compostella, Shuo Liu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81133?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: arch/x86/include/arch: Add feature check macros ...................................................................... arch/x86/include/arch: Add feature check macros Add feature check macros for MCE (machine check exception) and MCA (machine check architecture) Change-Id: I014c25ced1dbe21f35486f8305b1de7669e932d0 Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> Signed-off-by: Jincheng Li <jincheng.li(a)intel.com> --- M src/arch/x86/include/arch/cpu.h 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/81133/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/81133?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I014c25ced1dbe21f35486f8305b1de7669e932d0 Gerrit-Change-Number: 81133 Gerrit-PatchSet: 3 Gerrit-Owner: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-MessageType: newpatchset

1 0

[XS] Change in coreboot[main]: arch/x86: Fix typo for marco CPUID_FEATURE_HTT
by Jincheng Li (Code Review) 15 Mar '24

15 Mar '24

Attention is currently required from: Jincheng Li, Jérémy Compostella, Shuo Liu. Hello Jérémy Compostella, Shuo Liu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81260?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: arch/x86: Fix typo for marco CPUID_FEATURE_HTT ...................................................................... arch/x86: Fix typo for marco CPUID_FEATURE_HTT Also use BIT marco to replace the original manual bit shift Change-Id: I9b29233e75483cda6bf7723cf79632f6b04233b0 Signed-off-by: Jincheng Li <jincheng.li(a)intel.com> --- M src/arch/x86/include/arch/cpu.h M src/cpu/intel/common/hyperthreading.c 2 files changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/81260/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81260?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9b29233e75483cda6bf7723cf79632f6b04233b0 Gerrit-Change-Number: 81260 Gerrit-PatchSet: 2 Gerrit-Owner: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-MessageType: newpatchset

1 0

[XS] Change in coreboot[main]: arch/x86: Fix typo for marco CPUID_FEATURE_HTT
by Jincheng Li (Code Review) 15 Mar '24

15 Mar '24

Attention is currently required from: Jérémy Compostella. Jincheng Li has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81260?usp=email ) Change subject: arch/x86: Fix typo for marco CPUID_FEATURE_HTT ...................................................................... arch/x86: Fix typo for marco CPUID_FEATURE_HTT Also use BIT marco to replace the original manual bit shift Change-Id: I9b29233e75483cda6bf7723cf79632f6b04233b0 Signed-off-by: Jincheng Li <jincheng.li(a)intel.com> --- M src/arch/x86/include/arch/cpu.h M src/cpu/intel/common/hyperthreading.c 2 files changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/81260/1 diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index 0c4decf..2236781 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -47,9 +47,9 @@ #define X86_VENDOR_ANY 0xfe #define X86_VENDOR_UNKNOWN 0xff -#define CPUID_FEATURE_PAE (1 << 6) -#define CPUID_FEATURE_PSE36 (1 << 17) -#define CPUID_FEAURE_HTT (1 << 28) +#define CPUID_FEATURE_PAE BIT6 +#define CPUID_FEATURE_PSE36 BIT17 +#define CPUID_FEATURE_HTT BIT28 /* Structured Extended Feature Flags */ #define CPUID_STRUCT_EXTENDED_FEATURE_FLAGS 0x7 diff --git a/src/cpu/intel/common/hyperthreading.c b/src/cpu/intel/common/hyperthreading.c index 85c4477..d034129 100644 --- a/src/cpu/intel/common/hyperthreading.c +++ b/src/cpu/intel/common/hyperthreading.c @@ -7,7 +7,7 @@ bool intel_ht_supported(void) { /* Is HyperThreading supported? */ - return !!(cpuid_edx(1) & CPUID_FEAURE_HTT); + return !!(cpuid_edx(1) & CPUID_FEATURE_HTT); } /* -- To view, visit https://review.coreboot.org/c/coreboot/+/81260?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9b29233e75483cda6bf7723cf79632f6b04233b0 Gerrit-Change-Number: 81260 Gerrit-PatchSet: 1 Gerrit-Owner: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-MessageType: newchange

1 0

[XS] Change in coreboot[main]: arch/x86/include/arch: Add feature check macros
by Jincheng Li (Code Review) 15 Mar '24

15 Mar '24

Attention is currently required from: Arthur Heymans, Jincheng Li, Jérémy Compostella. Hello Arthur Heymans, Jérémy Compostella, Shuo Liu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81133?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Code-Review+2 by Arthur Heymans, Verified+1 by build bot (Jenkins) Change subject: arch/x86/include/arch: Add feature check macros ...................................................................... arch/x86/include/arch: Add feature check macros Add feature check macros for MCE (machine check exception) and MCA (machine check architecture) Change-Id: I014c25ced1dbe21f35486f8305b1de7669e932d0 Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> Signed-off-by: Jincheng Li <jincheng.li(a)intel.com> --- M src/arch/x86/include/arch/cpu.h 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/81133/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81133?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I014c25ced1dbe21f35486f8305b1de7669e932d0 Gerrit-Change-Number: 81133 Gerrit-PatchSet: 2 Gerrit-Owner: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-MessageType: newpatchset

1 0

[XS] Change in coreboot[main]: soc/intel/xeon_sp: Drop SPI_BASE_ADDRESS from _CRS
by Patrick Rudolph (Code Review) 15 Mar '24

15 Mar '24

Patrick Rudolph has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/80795?usp=email ) Change subject: soc/intel/xeon_sp: Drop SPI_BASE_ADDRESS from _CRS ...................................................................... Abandoned Superseeded by CB:80796 -- To view, visit https://review.coreboot.org/c/coreboot/+/80795?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I150397a7ac5d60719f327f6ac6480a38fe295c32 Gerrit-Change-Number: 80795 Gerrit-PatchSet: 6 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

1 0

[XS] Change in coreboot[main]: arch/x86/include/arch: Add feature check macros
by Patrick Rudolph (Code Review) 15 Mar '24

15 Mar '24

Attention is currently required from: Jincheng Li, Jérémy Compostella. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81133?usp=email ) Change subject: arch/x86/include/arch: Add feature check macros ...................................................................... Patch Set 1: (1 comment) File src/arch/x86/include/arch/cpu.h: https://review.coreboot.org/c/coreboot/+/81133/comment/614ae3d8_64bc1297 : PS1, Line 51: CPUID_FEATURE_MCE It's unused. Where's the code that does make use of it? -- To view, visit https://review.coreboot.org/c/coreboot/+/81133?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I014c25ced1dbe21f35486f8305b1de7669e932d0 Gerrit-Change-Number: 81133 Gerrit-PatchSet: 1 Gerrit-Owner: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Comment-Date: Fri, 15 Mar 2024 08:26:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: soc/intel/xeon_sp: Unshare SMM related Kconfigs
by Patrick Rudolph (Code Review) 15 Mar '24

15 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, Jincheng Li, Johnny Lin, Lean Sheng Tan, Tim Chu. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81134?usp=email ) Change subject: soc/intel/xeon_sp: Unshare SMM related Kconfigs ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81134?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icc5f71e44f573575d599d2617a037bfd14e79dec Gerrit-Change-Number: 81134 Gerrit-PatchSet: 1 Gerrit-Owner: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 15 Mar 2024 08:25:57 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit March 2024