coreboot-gerrit March 2024

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[M] Change in coreboot[main]: amdfwtool: Set the table size only for FWs
by Bao Zheng (Code Review) 15 Mar '24

15 Mar '24

Attention is currently required from: Bao Zheng, Felix Held, Fred Reitberger, Zheng Bao. Hello Felix Held, Fred Reitberger, Zheng Bao, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81255?usp=email to look at the new patch set (#6). The following approvals got outdated and were removed: Code-Review+1 by Felix Held, Verified+1 by build bot (Jenkins) Change subject: amdfwtool: Set the table size only for FWs ...................................................................... amdfwtool: Set the table size only for FWs The entry in the table has two categaries, file and pointer. For the pointer, it does not take table space. The ISH, PSP level 2, BIOS table are all the pointer type. So integration function only packs FWs located in folder amd_blobs. And only FWs increase the table size. So the table size is only set once. Later calls only update the count and fletcher. The table has a header at least, so the size can not be 0. The fill_dir_header can take the parameter count as 0, such PSP level 1 only with ISH-A and ISH-B. It doesn't have any file type entries. This actually reverts https://review.coreboot.org/c/coreboot/+/78274 and adds other changes. TEST=Identical test on all AMD SOC platform Change-Id: I5dfbbb55912c8e37243c351427a8df89c12e5da8 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M util/amdfwtool/amdfwtool.c 1 file changed, 37 insertions(+), 35 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/81255/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/81255?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5dfbbb55912c8e37243c351427a8df89c12e5da8 Gerrit-Change-Number: 81255 Gerrit-PatchSet: 6 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: amdfwtool: Remove the dissociated combo BIOS table for recovery A/B
by Felix Held (Code Review) 15 Mar '24

15 Mar '24

Attention is currently required from: Bao Zheng, Fred Reitberger, Zheng Bao. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81137?usp=email ) Change subject: amdfwtool: Remove the dissociated combo BIOS table for recovery A/B ...................................................................... Patch Set 2: Code-Review+1 (1 comment) File util/amdfwtool/amdfwtool.c: https://review.coreboot.org/c/coreboot/+/81137/comment/3a1a8117_2d07ae3f : PS2, Line 1732: } else if (bhd_combo_dir != NULL) { i wonder if it would be better to check for !cb_config.recovery_ab here. if you prefer to check for bhd_combo_dir != NULL, please add a comment that this is the !cb_config.recovery_ab case -- To view, visit https://review.coreboot.org/c/coreboot/+/81137?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8735bd91b32bc9a0e4fc70d293e8d836d5e9c36b Gerrit-Change-Number: 81137 Gerrit-PatchSet: 2 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Fri, 15 Mar 2024 13:11:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: soc/intel/alderlake: Correctly set CNVi Reset and Clkreq pins
by Felix Held (Code Review) 15 Mar '24

15 Mar '24

Attention is currently required from: Dinesh Gehlot, Kapil Porwal, Nick Vaccaro, Sean Rhodes, Subrata Banik. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81080?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: soc/intel/alderlake: Correctly set CNVi Reset and Clkreq pins ...................................................................... Patch Set 3: (1 comment) File src/soc/intel/alderlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/81080/comment/632c8c80_f0d040ec : PS3, Line 839: if (CONFIG(SOC_ESPI)) { hmm, looks like SOC_ESPI is defined in the apollolake kconfig, but this is alderlake. also isn't espi being used the default on this newer socs? would also be good if an Intel engineer could have a look at this patch -- To view, visit https://review.coreboot.org/c/coreboot/+/81080?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib534d3cfe888c1c538267caaf324c8ae743da496 Gerrit-Change-Number: 81080 Gerrit-PatchSet: 3 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Fri, 15 Mar 2024 12:58:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[main]: amdfwtool: Set the table size only for FWs
by Felix Held (Code Review) 15 Mar '24

15 Mar '24

Attention is currently required from: Bao Zheng, Fred Reitberger, Zheng Bao. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81255?usp=email ) Change subject: amdfwtool: Set the table size only for FWs ...................................................................... Patch Set 5: Code-Review+1 (1 comment) File util/amdfwtool/amdfwtool.c: https://review.coreboot.org/c/coreboot/+/81255/comment/d98fec8c_0f58cc8f : PS5, Line 561: if (dir->header.additional_info_fields.dir_size == 0) would be good if you can add a comment here that this results in dir_size only getting updated the first time fill_dir_header gets called for a table -- To view, visit https://review.coreboot.org/c/coreboot/+/81255?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5dfbbb55912c8e37243c351427a8df89c12e5da8 Gerrit-Change-Number: 81255 Gerrit-PatchSet: 5 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Fri, 15 Mar 2024 12:47:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: 3rdparty/intel-microcode: Update submodule to upstream main
by Felix Held (Code Review) 15 Mar '24

15 Mar '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81272?usp=email ) Change subject: 3rdparty/intel-microcode: Update submodule to upstream main ...................................................................... 3rdparty/intel-microcode: Update submodule to upstream main Updating from commit id ece0d29: 2023-11-14 10:19:09 -0600 - (microcode-20231114 Release) to commit id 41af345: 2024-03-11 19:11:14 -0600 - (microcode-20240312 Release) This brings in 1 new commits: 41af345 microcode-20240312 Release Change-Id: Iaea865100661776c5331cba6c92ef51dfd410159 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81272 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> --- M 3rdparty/intel-microcode 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Lean Sheng Tan: Looks good to me, approved diff --git a/3rdparty/intel-microcode b/3rdparty/intel-microcode index ece0d29..41af345 160000 --- a/3rdparty/intel-microcode +++ b/3rdparty/intel-microcode @@ -1 +1 @@ -Subproject commit ece0d294a29a1375397941a4e6f2f7217910bc89 +Subproject commit 41af34500598418150aa298bb04e7edacc547897 -- To view, visit https://review.coreboot.org/c/coreboot/+/81272?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iaea865100661776c5331cba6c92ef51dfd410159 Gerrit-Change-Number: 81272 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: mb/google/brya/var/xol: Modify clkreq to clksrc mapping for NVMe
by Felix Held (Code Review) 15 Mar '24

15 Mar '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81230?usp=email ) Change subject: mb/google/brya/var/xol: Modify clkreq to clksrc mapping for NVMe ...................................................................... mb/google/brya/var/xol: Modify clkreq to clksrc mapping for NVMe NVMe using clk_src[0] and clk_req[1] mapping to hardware design, Due to inconsistency between PMC firmware and FSP, we need to set clk_src to clk_req number, not same as hardware mapping in coreboot. Then swap correct setting to clk_src=0,clk_req=1 in mFIT. BUG=b:328318578 TEST=build firmware and veirfy suspend function on NVMe SKU DUT. Cq-Depend: chrome-internal:7063434 Change-Id: I1777310782a0f4417bd1bb21287bec5852be966e Signed-off-by: Seunghwan Kim <sh_.kim(a)samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81230 Reviewed-by: Subrata Banik <subratabanik(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <ericllai(a)google.com> --- M src/mainboard/google/brya/variants/xol/overridetree.cb 1 file changed, 5 insertions(+), 2 deletions(-) Approvals: Subrata Banik: Looks good to me, approved Eric Lai: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/brya/variants/xol/overridetree.cb b/src/mainboard/google/brya/variants/xol/overridetree.cb index b825ddd..80d15fe 100644 --- a/src/mainboard/google/brya/variants/xol/overridetree.cb +++ b/src/mainboard/google/brya/variants/xol/overridetree.cb @@ -268,10 +268,13 @@ end end device ref pcie4_0 on - # Enable CPU PCIE RP 1 using CLK 0 + # Enable NVMe SSD using clk_src0 and clk_req1 mapping to hardware + # design. Due to inconsistency between PMC firmware and FSP, we need + # to set clk_src to clk_req number, not same as hardware mapping in + # coreboot. Then swap correct setting clksrc, clkreq in mFIT. register "cpu_pcie_rp[CPU_RP(1)]" = "{ .clk_req = 1, - .clk_src = 0, + .clk_src = 1, .flags = PCIE_RP_LTR | PCIE_RP_AER, }" probe STORAGE STORAGE_NVME -- To view, visit https://review.coreboot.org/c/coreboot/+/81230?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1777310782a0f4417bd1bb21287bec5852be966e Gerrit-Change-Number: 81230 Gerrit-PatchSet: 3 Gerrit-Owner: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: brox: ish: Add Kconfigs for ISH
by Felix Held (Code Review) 15 Mar '24

15 Mar '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81050?usp=email ) ( 6 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: brox: ish: Add Kconfigs for ISH ...................................................................... brox: ish: Add Kconfigs for ISH Modeled after the Rex Kconfigs for ISH. Change-Id: Ic670d550a9aaad64e52489d895b8aac2aee4b5ed Signed-off-by: Yuval Peress <peress(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81050 Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/brox/Kconfig M src/mainboard/google/brox/Kconfig.name 2 files changed, 11 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved diff --git a/src/mainboard/google/brox/Kconfig b/src/mainboard/google/brox/Kconfig index 660f50b..0c7a112 100644 --- a/src/mainboard/google/brox/Kconfig +++ b/src/mainboard/google/brox/Kconfig @@ -58,6 +58,11 @@ select BOARD_GOOGLE_BASEBOARD_BROX select CHROMEOS_WIFI_SAR if CHROMEOS +config BOARD_GOOGLE_BROX_EC_ISH + select BOARD_GOOGLE_BASEBOARD_BROX + select CHROMEOS_WIFI_SAR if CHROMEOS + select SOC_INTEL_STORE_ISH_FW_VERSION + if BOARD_GOOGLE_BROX_COMMON config BASEBOARD_DIR @@ -82,7 +87,7 @@ config DRIVER_TPM_I2C_BUS hex - default 0x4 if BOARD_GOOGLE_BROX + default 0x4 if BOARD_GOOGLE_BASEBOARD_BROX config DRIVER_TPM_I2C_ADDR hex @@ -106,10 +111,11 @@ default "Google_Brox" if BOARD_GOOGLE_BASEBOARD_BROX config MAINBOARD_PART_NUMBER + default "Brox_Ec_Ish" if BOARD_GOOGLE_BROX_EC_ISH default "Brox" if BOARD_GOOGLE_BROX config VARIANT_DIR - default "brox" if BOARD_GOOGLE_BROX + default "brox" if BOARD_GOOGLE_BROX || BOARD_GOOGLE_BROX_EC_ISH config VBOOT select VBOOT_LID_SWITCH diff --git a/src/mainboard/google/brox/Kconfig.name b/src/mainboard/google/brox/Kconfig.name index ad5ab77..2ad3457 100644 --- a/src/mainboard/google/brox/Kconfig.name +++ b/src/mainboard/google/brox/Kconfig.name @@ -4,3 +4,6 @@ config BOARD_GOOGLE_BROX bool "-> Brox" + +config BOARD_GOOGLE_BROX_EC_ISH + bool "-> Brox EC ISH" -- To view, visit https://review.coreboot.org/c/coreboot/+/81050?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic670d550a9aaad64e52489d895b8aac2aee4b5ed Gerrit-Change-Number: 81050 Gerrit-PatchSet: 8 Gerrit-Owner: Yuval Peress <peress(a)google.com> Gerrit-Reviewer: Bob Moragues <moragues(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Li1 Feng <li1.feng(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Tanu Malhotra <tanu.malhotra(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: soc/intel/xeon_sp/spr: Enable x86_64 support
by Arthur Heymans (Code Review) 15 Mar '24

15 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Lean Sheng Tan, Patrick Rudolph, Shuo Liu, Tim Chu. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81280?usp=email ) Change subject: soc/intel/xeon_sp/spr: Enable x86_64 support ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81280?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2c5ed0339a9c2e9b088b16dbb4c19df98e796d65 Gerrit-Change-Number: 81280 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 15 Mar 2024 11:37:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: drivers/intel/fsp2_0: Support FSP-T in long mode
by Patrick Rudolph (Code Review) 15 Mar '24

15 Mar '24

Attention is currently required from: Andrey Petrov, Arthur Heymans, Ronak Kanabar. Hello Arthur Heymans, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/81281?usp=email to review the following change. Change subject: drivers/intel/fsp2_0: Support FSP-T in long mode ...................................................................... drivers/intel/fsp2_0: Support FSP-T in long mode Call into FSP-T using the protected mode wrapper and enter long mode in FSP-T support assembly code. TEST: Booted on ibm/sbp1 in long mode. Change-Id: Id6b9780b06b4bfbb952e32091ffbf3d0014f2090 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/drivers/intel/fsp2_0/temp_ram_exit.c M src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S 2 files changed, 20 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/81281/1 diff --git a/src/drivers/intel/fsp2_0/temp_ram_exit.c b/src/drivers/intel/fsp2_0/temp_ram_exit.c index 87b77bc..193c143 100644 --- a/src/drivers/intel/fsp2_0/temp_ram_exit.c +++ b/src/drivers/intel/fsp2_0/temp_ram_exit.c @@ -1,10 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <arch/romstage.h> +#include <cbfs.h> #include <console/console.h> #include <fsp/api.h> #include <fsp/util.h> -#include <cbfs.h> +#include <mode_switch.h> +#include <stdint.h> #include <types.h> static void fsp_temp_ram_exit(void) @@ -25,9 +27,12 @@ if (fsp_validate_component(&hdr, mapping, size) != CB_SUCCESS) die("Invalid FSPM header!\n"); - temp_ram_exit = (void *)(hdr.image_base + hdr.temp_ram_exit_entry_offset); + temp_ram_exit = (void *)(uintptr_t)(hdr.image_base + hdr.temp_ram_exit_entry_offset); printk(BIOS_DEBUG, "Calling TempRamExit: %p\n", temp_ram_exit); - status = temp_ram_exit(NULL); + if (ENV_X86_64 && CONFIG(PLATFORM_USES_FSP2_X86_32)) + status = protected_mode_call_1arg(temp_ram_exit, (uintptr_t)NULL); + else + status = temp_ram_exit(NULL); if (status != FSP_SUCCESS) die("TempRamExit returned with error 0x%08x!\n", status); diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S index 238a57e..5e6c408 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S @@ -4,6 +4,7 @@ #include <cpu/x86/cr.h> #include <cpu/x86/post_code.h> #include <intelblocks/post_codes.h> +#include <cpu/x86/64bit/entry64.inc> #define CBFS_FILE_MAGIC 0 #define CBFS_FILE_LEN (CBFS_FILE_MAGIC + 8) @@ -15,6 +16,8 @@ .extern temp_ram_init_params +.code32 + .global bootblock_pre_c_entry bootblock_pre_c_entry: @@ -88,10 +91,19 @@ pop %ecx movl %ecx, temp_memory_start +#if ENV_X86_64 + setup_longmode $(CONFIG_ARCH_X86_64_PGTBL_LOC) + movl %ebp, %edi + shlq $32, %rdi + movd %mm1, %rsi + or %rsi, %rdi + andl $0xfffffff0, %esp +#else /* Restore the timestamp from bootblock_crt0.S (ebp:mm1) */ push %ebp movd %mm1, %eax push %eax +#endif /* Copy .data section content to Cache-As-Ram */ #include <cpu/x86/copy_data_section.inc> -- To view, visit https://review.coreboot.org/c/coreboot/+/81281?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id6b9780b06b4bfbb952e32091ffbf3d0014f2090 Gerrit-Change-Number: 81281 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: soc/intel/xeon_sp/spr: Enable x86_64 support
by Patrick Rudolph (Code Review) 15 Mar '24

15 Mar '24

Attention is currently required from: Arthur Heymans. Hello Arthur Heymans, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/81280?usp=email to review the following change. Change subject: soc/intel/xeon_sp/spr: Enable x86_64 support ...................................................................... soc/intel/xeon_sp/spr: Enable x86_64 support Fix compilation errors when compiled for x86_64. Test: Booted on ibm/sbp1 to linux payload. Change-Id: I2c5ed0339a9c2e9b088b16dbb4c19df98e796d65 Signed-off-by: Arthur Heymans <arthur.heymans(a)9elements.com> --- M src/soc/intel/xeon_sp/spr/Kconfig M src/soc/intel/xeon_sp/spr/romstage.c M src/soc/intel/xeon_sp/spr/upd_display.c M src/soc/intel/xeon_sp/uncore_acpi.c 4 files changed, 14 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/81280/1 diff --git a/src/soc/intel/xeon_sp/spr/Kconfig b/src/soc/intel/xeon_sp/spr/Kconfig index 6b8a106..646c66a 100644 --- a/src/soc/intel/xeon_sp/spr/Kconfig +++ b/src/soc/intel/xeon_sp/spr/Kconfig @@ -17,6 +17,7 @@ select UDK_202005_BINDING select SOC_INTEL_HAS_CXL select USE_COREBOOT_COMPLEMENTARY_FSP_HEADERS + select HAVE_EXP_X86_64_SUPPORT help Intel Sapphire Rapids-SP support diff --git a/src/soc/intel/xeon_sp/spr/romstage.c b/src/soc/intel/xeon_sp/spr/romstage.c index af86f71..e1284ac 100644 --- a/src/soc/intel/xeon_sp/spr/romstage.c +++ b/src/soc/intel/xeon_sp/spr/romstage.c @@ -119,7 +119,7 @@ { unsigned int port, socket; - mupd->FspmConfig.IioPcieConfigTablePtr = (UINT32)spr_iio_bifur_table; + mupd->FspmConfig.IioPcieConfigTablePtr = (uintptr_t)spr_iio_bifur_table; /* MAX_SOCKET is the maximal number defined by FSP, currently is 4. */ mupd->FspmConfig.IioPcieConfigTableNumber = MAX_SOCKET; UPD_IIO_PCIE_PORT_CONFIG *PciePortConfig = @@ -135,7 +135,7 @@ PciePortConfig[socket].PcieMaxReadRequestSize = 0x5; } - mupd->FspmConfig.DeEmphasisPtr = (UINT32)deemphasis_list; + mupd->FspmConfig.DeEmphasisPtr = (uintptr_t)deemphasis_list; mupd->FspmConfig.DeEmphasisNumber = MAX_SOCKET * MAX_IIO_PORTS_PER_SOCKET; UINT8 *DeEmphasisConfig = (UINT8 *)deemphasis_list; @@ -280,7 +280,7 @@ UPD_IIO_PCIE_PORT_CONFIG *iio_pcie_cfg; int socket; - iio_pcie_cfg = (UPD_IIO_PCIE_PORT_CONFIG *)mupd->FspmConfig.IioPcieConfigTablePtr; + iio_pcie_cfg = (UPD_IIO_PCIE_PORT_CONFIG *)(uintptr_t)mupd->FspmConfig.IioPcieConfigTablePtr; for (socket = 0; socket < MAX_SOCKET; socket++) iio_pcie_cfg[socket].PcieGlobalAspm = 0; diff --git a/src/soc/intel/xeon_sp/spr/upd_display.c b/src/soc/intel/xeon_sp/spr/upd_display.c index c69a9a0..b3c0c7c 100644 --- a/src/soc/intel/xeon_sp/spr/upd_display.c +++ b/src/soc/intel/xeon_sp/spr/upd_display.c @@ -12,7 +12,7 @@ int port, socket; UPD_IIO_PCIE_PORT_CONFIG *PciePortConfig = - (UPD_IIO_PCIE_PORT_CONFIG *)mupd->FspmConfig.IioPcieConfigTablePtr; + (UPD_IIO_PCIE_PORT_CONFIG *)(uintptr_t)mupd->FspmConfig.IioPcieConfigTablePtr; printk(BIOS_SPEW, "UPD values for IIO:\n"); for (socket = 0; socket < mupd->FspmConfig.IioPcieConfigTableNumber; socket++) { @@ -94,7 +94,7 @@ PciePortConfig[socket].PcieMaxReadRequestSize); } - UINT8 *DeEmphasisConfig = (UINT8 *)mupd->FspmConfig.DeEmphasisPtr; + UINT8 *DeEmphasisConfig = (UINT8 *)(uintptr_t)mupd->FspmConfig.DeEmphasisPtr; for (port = 0; port < mupd->FspmConfig.DeEmphasisNumber; port++) { printk(BIOS_SPEW, "port: %d, DeEmphasisConfig: 0x%x\n", port, DeEmphasisConfig[port]); diff --git a/src/soc/intel/xeon_sp/uncore_acpi.c b/src/soc/intel/xeon_sp/uncore_acpi.c index 12d99da..b441f0e 100644 --- a/src/soc/intel/xeon_sp/uncore_acpi.c +++ b/src/soc/intel/xeon_sp/uncore_acpi.c @@ -20,6 +20,9 @@ #include <soc/soc_util.h> #include <soc/util.h> #include <intelblocks/p2sb.h> +#include <stddef.h> +#include <stdint.h> + #include "chip.h" /* NUMA related ACPI table generation. SRAT, SLIT, etc */ @@ -452,11 +455,11 @@ } unsigned long tmp = current; - printk(BIOS_DEBUG, "[Reserved Memory Region] PCI Segment Number: 0x%x, Base Address: 0x%x, " - "End Address (limit): 0x%x\n", - 0, (uint32_t)ptr, (uint32_t)((uint32_t)ptr + size - 1)); - current += acpi_create_dmar_rmrr(current, 0, (uint32_t)ptr, - (uint32_t)((uint32_t)ptr + size - 1)); + printk(BIOS_DEBUG, "[Reserved Memory Region] PCI Segment Number: 0x%x, Base Address: 0x%lx, " + "End Address (limit): 0x%lx\n", + 0, (uintptr_t) ptr, (size_t)((uintptr_t)ptr + size - 1)); + current += acpi_create_dmar_rmrr(current, 0, (uintptr_t) ptr, + (size_t) ((uintptr_t)ptr + size - 1)); printk(BIOS_DEBUG, " [PCI Endpoint Device] PCI Bus Number: 0x%x, " "PCI Path: 0x%x, 0x%x\n", -- To view, visit https://review.coreboot.org/c/coreboot/+/81280?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2c5ed0339a9c2e9b088b16dbb4c19df98e796d65 Gerrit-Change-Number: 81280 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-MessageType: newchange

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coreboot-gerrit March 2024