coreboot-gerrit March 2024

coreboot-gerrit@coreboot.org

1 participants
3668 discussions

[M] Change in coreboot[main]: arch/riscv: Reformat C files with clang-format v16
by ron minnich (Code Review) 15 Mar '24

15 Mar '24

Attention is currently required from: Martin L Roth. ron minnich has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80011?usp=email ) Change subject: arch/riscv: Reformat C files with clang-format v16 ...................................................................... Patch Set 1: (7 comments) File src/arch/riscv/fit_payload.c: https://review.coreboot.org/c/coreboot/+/80011/comment/d1411909_3c727011 : PS1, Line 31: printk(BIOS_INFO, "FIT: Leaving additional %u MiB of free space after kernel.\n", > this improvement in readability could be further improved if we allowed reasonable line lengths <duc […] Done File src/arch/riscv/opensbi.c: https://review.coreboot.org/c/coreboot/+/80011/comment/712ea309_94d933b9 : PS1, Line 12: void run_opensbi(const int hart_id, const void *fdt, const void *opensbi, const void *payload, > this is yuck, but, it's the line length we have, so ... Done File src/arch/riscv/pmp.c: https://review.coreboot.org/c/coreboot/+/80011/comment/eb18e8bc_222fd259 : PS1, Line 67: old = read_csr(pmpcfg0); > YAY! Done https://review.coreboot.org/c/coreboot/+/80011/comment/9ce055f3_856f8ccc : PS1, Line 204: static pmpcfg_t generate_pmp_napot(uintptr_t base, uintptr_t size, uintptr_t flags) > I'm in heaven here. […] Done https://review.coreboot.org/c/coreboot/+/80011/comment/0a2cec25_5ef1c48d : PS1, Line 274: die("Some PMP configurations are locked " > yuck. Done File src/arch/riscv/tables.c: https://review.coreboot.org/c/coreboot/+/80011/comment/3957e19f_b8fdb38e : PS1, Line 15: bootmem_add_range((uintptr_t)_opensbi, REGION_SIZE(opensbi), BM_MEM_OPENSBI); > nice. Done File src/arch/riscv/trap_handler.c: https://review.coreboot.org/c/coreboot/+/80011/comment/0208557a_48b0077e : PS1, Line 36: case 0x00000000: > meh. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/80011?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic863ec7e56f86da7f1967ac4c566bb988071d127 Gerrit-Change-Number: 80011 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Comment-Date: Fri, 15 Mar 2024 18:35:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: comment

1 0

[M] Change in coreboot[main]: arch/riscv: Reformat C files with clang-format v16
by ron minnich (Code Review) 15 Mar '24

15 Mar '24

Attention is currently required from: Martin L Roth. ron minnich has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80011?usp=email ) Change subject: arch/riscv: Reformat C files with clang-format v16 ...................................................................... Patch Set 1: Code-Review+2 (9 comments) File src/arch/riscv/fit_payload.c: https://review.coreboot.org/c/coreboot/+/80011/comment/af7d959b_1fcecc70 : PS1, Line 31: printk(BIOS_INFO, "FIT: Leaving additional %u MiB of free space after kernel.\n", this improvement in readability could be further improved if we allowed reasonable line lengths <ducks> File src/arch/riscv/misaligned.c: https://review.coreboot.org/c/coreboot/+/80011/comment/c01e9d0e_2911d233 : PS1, Line 150: if ((EXTRACT_FIELD(ins, 0x3) == 3) && (EXTRACT_FIELD(ins, 0x1c) != 0x7)) { this is great :-) File src/arch/riscv/opensbi.c: https://review.coreboot.org/c/coreboot/+/80011/comment/8fedef19_3514f179 : PS1, Line 12: void run_opensbi(const int hart_id, const void *fdt, const void *opensbi, const void *payload, this is yuck, but, it's the line length we have, so ... File src/arch/riscv/pmp.c: https://review.coreboot.org/c/coreboot/+/80011/comment/6bcfa2ac_095cedbb : PS1, Line 67: old = read_csr(pmpcfg0); YAY! https://review.coreboot.org/c/coreboot/+/80011/comment/954b070f_ff9bf7a5 : PS1, Line 204: static pmpcfg_t generate_pmp_napot(uintptr_t base, uintptr_t size, uintptr_t flags) I'm in heaven here. Readable declarations! https://review.coreboot.org/c/coreboot/+/80011/comment/f7519fc9_cad520aa : PS1, Line 274: die("Some PMP configurations are locked " yuck. File src/arch/riscv/tables.c: https://review.coreboot.org/c/coreboot/+/80011/comment/3c3ca6eb_f3b0c25b : PS1, Line 15: bootmem_add_range((uintptr_t)_opensbi, REGION_SIZE(opensbi), BM_MEM_OPENSBI); nice. File src/arch/riscv/trap_handler.c: https://review.coreboot.org/c/coreboot/+/80011/comment/4191be29_c2785383 : PS1, Line 36: case 0x00000000: meh. File src/arch/riscv/virtual_memory.c: https://review.coreboot.org/c/coreboot/+/80011/comment/4e445722_55478d26 : PS1, Line 16: static int delegate = 0 | (1 << CAUSE_MISALIGNED_FETCH) | (1 << CAUSE_FETCH_ACCESS) | this is a rare time that I'll confess to disliking the results of clangfmt. If you look on the left, it's super easy when debugging to comment out one mdeleg at a time. One the right, it's a real pain. But, I still feel that clangfmt is the right way to go, so I'll hold my nose and +2. -- To view, visit https://review.coreboot.org/c/coreboot/+/80011?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic863ec7e56f86da7f1967ac4c566bb988071d127 Gerrit-Change-Number: 80011 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Comment-Date: Fri, 15 Mar 2024 18:34:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[XS] Change in coreboot[main]: arch/riscv: reset the pmp on startup
by ron minnich (Code Review) 15 Mar '24

15 Mar '24

Attention is currently required from: Arthur Heymans, Maximilian Brune, Philipp Hug. ron minnich has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81282?usp=email ) Change subject: arch/riscv: reset the pmp on startup ...................................................................... Patch Set 1: (1 comment) File src/arch/riscv/virtual_memory.c: https://review.coreboot.org/c/coreboot/+/81282/comment/756d48db_2de7e230 : PS1, Line 50: reset_pmp(); > I'm thinking, if we should move mstatus_init to be invoked much later (e.g. […] This particular function is safe to run very early. It barely needs to be a function, certainly not this complex, since the four pmpcfg registers are WARL. I wonder about just running the 2 or 4 CSR writes in early assembly and calling it good. I'd be inclined to take this as a TODO for now? The current code has a bitmask for used PMPs, and I don't like seeing that lying around. There is further optimization we might make to get rid of that bitmask. We could write the pattern 0x11111111 to the pmpcfg, and all pmpcfg that are implemented would then have the X bit set, but not be enabled. Then it's a simple test to find the next avaailable correctly implement pmpcfg: if A == 0, and X is 1, then it's a valid, unused pmpcfg. This pattern, again, could be written in very early assembly, with 32- or 64-bit writes, and we'd then have a far simpler pmp reset situation then we do today. WDYT? -- To view, visit https://review.coreboot.org/c/coreboot/+/81282?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id356ea66100582d6750ffa9fc01f031a16835e4f Gerrit-Change-Number: 81282 Gerrit-PatchSet: 1 Gerrit-Owner: ron minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Comment-Date: Fri, 15 Mar 2024 18:28:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Philipp Hug <philipp(a)hug.cx> Gerrit-MessageType: comment

1 0

[XS] Change in coreboot[main]: drivers/intel/fsp2_0: Use DECLARE_REGION for FSP-M heap
by Jérémy Compostella (Code Review) 15 Mar '24

15 Mar '24

Attention is currently required from: Andrey Petrov, Arthur Heymans, Chen, Gang C, Felix Held, Julius Werner, Patrick Rudolph, Ronak Kanabar, Shuo Liu, Subrata Banik, Werner Zeh. Jérémy Compostella has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81097?usp=email ) The change is no longer submittable: Code-Review is unsatisfied now. Change subject: drivers/intel/fsp2_0: Use DECLARE_REGION for FSP-M heap ...................................................................... Patch Set 3: -Code-Review (1 comment) Patchset: PS3: Actually, I like that you reference the original patch but I don't think that "fixes" is appropriate here. This is not broken. This is a code enhancement in my opinion. Could you reword that in a "nicer" way ? -- To view, visit https://review.coreboot.org/c/coreboot/+/81097?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5f7d7855592d99b074f7ef49c285a13f8105f089 Gerrit-Change-Number: 81097 Gerrit-PatchSet: 3 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 15 Mar 2024 17:00:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[XS] Change in coreboot[main]: arch/riscv: reset the pmp on startup
by Philipp Hug (Code Review) 15 Mar '24

15 Mar '24

Attention is currently required from: Arthur Heymans, Maximilian Brune, ron minnich. Philipp Hug has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81282?usp=email ) Change subject: arch/riscv: reset the pmp on startup ...................................................................... Patch Set 1: (1 comment) File src/arch/riscv/virtual_memory.c: https://review.coreboot.org/c/coreboot/+/81282/comment/61861aeb_be760473 : PS1, Line 50: reset_pmp(); I'm thinking, if we should move mstatus_init to be invoked much later (e.g. just before the payload is loaded) or split up the function in what is needed early. Adding more code here before we have any console output can cause frustrating debugging sessions. -- To view, visit https://review.coreboot.org/c/coreboot/+/81282?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id356ea66100582d6750ffa9fc01f031a16835e4f Gerrit-Change-Number: 81282 Gerrit-PatchSet: 1 Gerrit-Owner: ron minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Fri, 15 Mar 2024 16:57:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[XS] Change in coreboot[main]: drivers/intel/fsp2_0: Use DECLARE_REGION for FSP-M heap
by Jérémy Compostella (Code Review) 15 Mar '24

15 Mar '24

Attention is currently required from: Andrey Petrov, Arthur Heymans, Chen, Gang C, Felix Held, Julius Werner, Patrick Rudolph, Ronak Kanabar, Shuo Liu, Subrata Banik, Werner Zeh. Jérémy Compostella has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81097?usp=email ) Change subject: drivers/intel/fsp2_0: Use DECLARE_REGION for FSP-M heap ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81097?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5f7d7855592d99b074f7ef49c285a13f8105f089 Gerrit-Change-Number: 81097 Gerrit-PatchSet: 3 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 15 Mar 2024 16:51:21 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[main]: soc/intel/xeon_sp: Initial support for PCI multi segment groups
by Patrick Rudolph (Code Review) 15 Mar '24

15 Mar '24

Attention is currently required from: Annie Chen, Arthur Heymans, Arthur Heymans, Chen, Gang C, Christian Walter, David Hendricks, Felix Held, Jincheng Li, Johnny Lin, Naresh Solanki, Nico Huber, Nill Ge, TangYiwei, Tim Chu. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79878?usp=email ) Change subject: soc/intel/xeon_sp: Initial support for PCI multi segment groups ...................................................................... Patch Set 12: (1 comment) File src/soc/intel/xeon_sp/chip_common.c: https://review.coreboot.org/c/coreboot/+/79878/comment/28561c2e_519220c3 : PS12, Line 411: soc_create_ioat_domains(dn, root_bus, ri, seg); > Why no do the same with the other create functions above? Then we wouldn't […] Looks like a good idea. The code evolved a bit and the rebase doesn't account for that. -- To view, visit https://review.coreboot.org/c/coreboot/+/79878?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0ba5e426123234979d746d3bdfc1ddfbd71c3447 Gerrit-Change-Number: 79878 Gerrit-PatchSet: 12 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Annie Chen <chen.annieet(a)inventec.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nill Ge <geshijian(a)bytedance.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Annie Chen <chen.annieet(a)inventec.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Nill Ge <geshijian(a)bytedance.com> Gerrit-Attention: TangYiwei Gerrit-Attention: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 15 Mar 2024 16:43:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

1 0

[XS] Change in coreboot[main]: arch/riscv: reset the pmp on startup
by ron minnich (Code Review) 15 Mar '24

15 Mar '24

ron minnich has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81282?usp=email ) Change subject: arch/riscv: reset the pmp on startup ...................................................................... arch/riscv: reset the pmp on startup All RISC-V used today support the PMP. There is no requirement that the PMP registers be cleared on power-on/reset. Always clear them as part of HART initialization. Change-Id: Id356ea66100582d6750ffa9fc01f031a16835e4f Signed-off-by: Ronald G Minnich <rminnich(a)gmail.com> --- M src/arch/riscv/virtual_memory.c 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/81282/1 diff --git a/src/arch/riscv/virtual_memory.c b/src/arch/riscv/virtual_memory.c index 43e3d70..79a0985 100644 --- a/src/arch/riscv/virtual_memory.c +++ b/src/arch/riscv/virtual_memory.c @@ -5,6 +5,7 @@ #include <arch/cpu.h> #include <arch/encoding.h> +#include <arch/pmp.h> #include <vm.h> /* Delegate controls which traps are delegated to the payload. If you @@ -44,4 +45,7 @@ // Enable all user/supervisor-mode counters write_csr(mcounteren, 7); + + // Every CPU we care about has pmp. + reset_pmp(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/81282?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id356ea66100582d6750ffa9fc01f031a16835e4f Gerrit-Change-Number: 81282 Gerrit-PatchSet: 1 Gerrit-Owner: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: newchange

1 0

[XS] Change in coreboot[main]: soc/intel/xeon_sp: Unshare SMM related Kconfigs
by Benjamin Doron (Code Review) 15 Mar '24

15 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, Jincheng Li, Johnny Lin, Lean Sheng Tan, Martin L Roth, Nico Huber, Patrick Georgi, Tim Chu. Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81134?usp=email ) Change subject: soc/intel/xeon_sp: Unshare SMM related Kconfigs ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > Sheng, you know that we're working on something that could address this. […] Also, I looked at the FSP EAS v2.4 to find out when FSP-I wants to be called, and I couldn't get any information Currently, I'm assuming it's pretty early in silicon init, because SMM should be set-up early for security purposes (I believe). If FSP didn't own SMM, are their other limitations for when it wants its SMI handlers to be installed? For instance, before the lockdown performed at any of the FSP-S notify phases -- To view, visit https://review.coreboot.org/c/coreboot/+/81134?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icc5f71e44f573575d599d2617a037bfd14e79dec Gerrit-Change-Number: 81134 Gerrit-PatchSet: 1 Gerrit-Owner: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 15 Mar 2024 16:36:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Benjamin Doron <benjamin.doron00(a)gmail.com> Comment-In-Reply-To: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-MessageType: comment

1 0

[XS] Change in coreboot[main]: soc/intel/xeon_sp: Unshare SMM related Kconfigs
by Benjamin Doron (Code Review) 15 Mar '24

15 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, Jincheng Li, Johnny Lin, Lean Sheng Tan, Martin L Roth, Nico Huber, Patrick Georgi, Tim Chu. Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81134?usp=email ) Change subject: soc/intel/xeon_sp: Unshare SMM related Kconfigs ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > Good question. I think this needs much more context. What is an FSP-based […] Sheng, you know that we're working on something that could address this. We're still finalising documentation and such before we open it up though. In discussions about our project, we can discuss this sort of use-case too However, it would require changes to SMM init in the FSP -- To view, visit https://review.coreboot.org/c/coreboot/+/81134?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icc5f71e44f573575d599d2617a037bfd14e79dec Gerrit-Change-Number: 81134 Gerrit-PatchSet: 1 Gerrit-Owner: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 15 Mar 2024 16:32:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-MessageType: comment

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit March 2024