coreboot-gerrit March 2024

coreboot-gerrit@coreboot.org

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[XS] Change in coreboot[main]: arch/riscv: reset the pmp on startup
by Maximilian Brune (Code Review) 15 Mar '24

15 Mar '24

Attention is currently required from: Arthur Heymans, Philipp Hug, ron minnich. Maximilian Brune has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81282?usp=email ) Change subject: arch/riscv: reset the pmp on startup ...................................................................... Patch Set 1: (1 comment) File src/arch/riscv/virtual_memory.c: https://review.coreboot.org/c/coreboot/+/81282/comment/e0f7c3d7_2598cb31 : PS1, Line 50: reset_pmp(); > This particular function is safe to run very early. […] Why don't we clear them directly before setting them (like Philipp suggested). I don't think any function is safe to be called before console output. You never know what the hardware vendor screwed up when initially porting a mainboard. So I don't think we should call this so early if we don't have to. -- To view, visit https://review.coreboot.org/c/coreboot/+/81282?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id356ea66100582d6750ffa9fc01f031a16835e4f Gerrit-Change-Number: 81282 Gerrit-PatchSet: 1 Gerrit-Owner: ron minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Fri, 15 Mar 2024 22:28:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Philipp Hug <philipp(a)hug.cx> Comment-In-Reply-To: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: comment

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[XL] Change in coreboot[main]: lib/device_tree: Add some FDT helper functions
by Maximilian Brune (Code Review) 15 Mar '24

15 Mar '24

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[XL] Change in coreboot[main]: lib/device_tree: Add some FDT helper functions
by Maximilian Brune (Code Review) 15 Mar '24

15 Mar '24

Attention is currently required from: Jakub Czapiga, Julius Werner, Martin L Roth. Maximilian Brune has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81081?usp=email ) Change subject: lib/device_tree: Add some FDT helper functions ...................................................................... Patch Set 14: (11 comments) Patchset: PS13: > BTW can you please fix all the checkpatch errors? I usually reserve the checkpatch errors for last. You never what have to change in between during the review. File src/include/device_tree.h: https://review.coreboot.org/c/coreboot/+/81081/comment/e866936d_a36cdaff : PS13, Line 210: fdt_find_nodes_by_prefix > nit: I would choose a different name because all the other `fdt_find_... […] Done File src/lib/device_tree.c: https://review.coreboot.org/c/coreboot/+/81081/comment/d2641846_7f4b1feb : PS12, Line 200: if (!strncmp(*path, node_name, path_sub_len)) { > Okay, then why not use the stack? These path strings aren't gonna be very long. […] Isn't that the same as creating variable length arrays? I thought we don't do that anymore in coreboot. https://review.coreboot.org/c/coreboot/+/81081/comment/43e62c6a_fae74294 : PS12, Line 214: ince address-cells and size-cells are not inherited > I think I will investigate a bit on how other projects handle that. […] I asked in this thread: https://github.com/devicetree-org/devicetree-specification/issues/72 https://review.coreboot.org/c/coreboot/+/81081/comment/59f5305f_cd4832c5 : PS12, Line 234: (offset - size) > How about calling it `prop_offset` (because that's where the properties start) and the other one `no […] Done https://review.coreboot.org/c/coreboot/+/81081/comment/aa909f52_f0d05203 : PS12, Line 235: } while (be32dec(blob + offset) != FDT_TOKEN_END_NODE); > I don't really see how your code does anything different? You're still calling `fdt_next_node_name() […] Well `fdt_next_node_name` expects a `FDT_TOKEN_BEGIN_NODE`. The current implementation expects a `FDT_TOKEN_END_NODE`. Imagine at the offset where `fdt_next_node_name` checks is something different than both tokens. In the current implementation it will loop one over (since no `FDT_TOKEN_END_NODE` was read) reach `fdt_next_node_name` and then notices there is also no `FDT_TOKEN_BEGIN_NODE`. At this point we know there is something seriously wrong with the FDT and could potentially print it out (which I currently do not do ^^). If we only use `fdt_next_node_name()` we just leave the loop, but don't know if that is because of an error in the FDT or because we just reached the last node. (I think) Personally I think we should catch the errors that we can and accept those that we cannot. But I can't really be very objective about the readabillity since I am the one that wrote it. So if you think it is really more readable to just use `fdt_next_node_name` and it is worth the tradeoff, I will happily change it. https://review.coreboot.org/c/coreboot/+/81081/comment/4a88b806_ec52f25c : PS12, Line 337: results[(*count_results)++] = offset; > Maybe make it return the actual count of entries, but only fill as much as fits in the array? Then t […] Maybe do both? count the results that are actually found and print a warning if there are more than fits the array. But return only the amount of entries written in the results array? On the other hand maybe someone actually wants to find the first nth nodes matching a given prefix instead of all of them. Hmm... I think I will just return the number of entries actually written into results. Seems the easiest option and less error prone option. File src/lib/device_tree.c: https://review.coreboot.org/c/coreboot/+/81081/comment/675af2d7_a7d3c962 : PS13, Line 169: return offset; // return offset to reg property > Should this maybe return `count` instead? Otherwise how does the caller know how many addresses it g […] right https://review.coreboot.org/c/coreboot/+/81081/comment/e654ea4e_a27b33e7 : PS13, Line 333: && count_results < results_len > Shouldn't this be an `if (... […] I was just lazy. Changed it. https://review.coreboot.org/c/coreboot/+/81081/comment/ed22bfb1_632ad9a0 : PS13, Line 342: if (count_results == 0) > nit: This case seems to be redundant with the main return path below. Done File tests/lib/device_tree-test.c: https://review.coreboot.org/c/coreboot/+/81081/comment/15e86d3c_14e49ae4 : PS7, Line 13: // regular FDT from RISC-V QEMU virt target > Yes, of course, in a separate file. […] I will add separate commit to create the common code. The current patch is already big enough. -- To view, visit https://review.coreboot.org/c/coreboot/+/81081?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2fb1d93c5b3e1cb2f7d9584db52bbce3767b63d8 Gerrit-Change-Number: 81081 Gerrit-PatchSet: 14 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Fri, 15 Mar 2024 22:13:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-MessageType: comment

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[XL] Change in coreboot[main]: lib/device_tree: Add some FDT helper functions
by Maximilian Brune (Code Review) 15 Mar '24

15 Mar '24

Attention is currently required from: Jakub Czapiga, Martin L Roth, Maximilian Brune. Hello Jakub Czapiga, Julius Werner, Martin L Roth, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81081?usp=email to look at the new patch set (#14). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: lib/device_tree: Add some FDT helper functions ...................................................................... lib/device_tree: Add some FDT helper functions This adds some helper functions for FDT, since more and more mainboards seem to need FDT nowadays. For example our QEMU boards need it in order to know how much RAM is available. Also all RISC-V boards in our tree need FDT. This also adds some tests in order to test said functions. Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> Change-Id: I2fb1d93c5b3e1cb2f7d9584db52bbce3767b63d8 --- M src/include/device_tree.h M src/lib/device_tree.c M tests/lib/Makefile.mk A tests/lib/device_tree-test.c A tests/lib/tegra30-ouya.dtb.xxd A tests/lib/virt.dtb.xxd 6 files changed, 14,246 insertions(+), 47 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/81081/14 -- To view, visit https://review.coreboot.org/c/coreboot/+/81081?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2fb1d93c5b3e1cb2f7d9584db52bbce3767b63d8 Gerrit-Change-Number: 81081 Gerrit-PatchSet: 14 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: mb/google/brox: support ISH
by Li1 Feng (Code Review) 15 Mar '24

15 Mar '24

Attention is currently required from: Ashish Kumar Mishra, Ashish Kumar Mishra, Bernardo Perez Priego, Karthik Ramasubramanian, Li1 Feng, Shelley Chen, Yuval Peress. Hello Ashish Kumar Mishra, Ashish Kumar Mishra, Bernardo Perez Priego, Shelley Chen, Tanu Malhotra, Yuval Peress, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/80773?usp=email to look at the new patch set (#7). The following approvals got outdated and were removed: Code-Review+1 by Ashish Kumar Mishra, Code-Review+1 by Yuval Peress, Verified+1 by build bot (Jenkins) Change subject: mb/google/brox: support ISH ...................................................................... mb/google/brox: support ISH Set FW_CONFIG bit 21 to enable ISH PCI device and define ISH main firmware name so ISH shim loader can load firmware from file system. ISH also need to be enabled if STORAGE_UFS is set. BUG=b:280329972 TEST= Set bit CBI FW_CONFIG bit 21 Boot Brox board, check that ISH is enabled and loaded lspci shows: 00:12.0 Serial controller: Intel Corporation Alder Lake-P Integrated Sensor Hub (rev 01). Change-Id: Iadc5108c62737d27642a6948c00b5c122541aaba Signed-off-by: Li Feng <li1.feng(a)intel.com> --- M src/mainboard/google/brox/variants/baseboard/brox/gpio.c M src/mainboard/google/brox/variants/brox/fw_config.c M src/mainboard/google/brox/variants/brox/overridetree.cb 3 files changed, 39 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/80773/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/80773?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iadc5108c62737d27642a6948c00b5c122541aaba Gerrit-Change-Number: 80773 Gerrit-PatchSet: 7 Gerrit-Owner: Li1 Feng <li1.feng(a)intel.com> Gerrit-Reviewer: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Reviewer: Ashish Kumar Mishra <ashish.k.mishra(a)intel.corp-partner.google.com> Gerrit-Reviewer: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Tanu Malhotra <tanu.malhotra(a)intel.com> Gerrit-Reviewer: Yuval Peress <peress(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Yuval Peress <peress(a)google.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Attention: Li1 Feng <li1.feng(a)intel.com> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.corp-partner.google.com> Gerrit-Attention: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: acpi/acpi: mark CTBL coreboot table device as hidden
by Felix Held (Code Review) 15 Mar '24

15 Mar '24

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81264?usp=email ) Change subject: acpi/acpi: mark CTBL coreboot table device as hidden ...................................................................... acpi/acpi: mark CTBL coreboot table device as hidden TEST=Unknown device disappears in the device manager in Windows 10 on Mandolin Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ifaefeb662da33323460333d9ca9c0e8340720fd1 --- M src/acpi/acpi.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/81264/1 diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index 98c8ecd..ce9444d 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -302,7 +302,7 @@ acpigen_write_device("CTBL"); acpigen_write_coreboot_hid(COREBOOT_ACPI_ID_CBTABLE); acpigen_write_name_integer("_UID", 0); - acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_ON); + acpigen_write_STA(ACPI_STATUS_DEVICE_HIDDEN_ON); acpigen_write_name("_CRS"); acpigen_write_resourcetemplate_header(); acpigen_resource_consumer_mmio(base, base + size - 1, -- To view, visit https://review.coreboot.org/c/coreboot/+/81264?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifaefeb662da33323460333d9ca9c0e8340720fd1 Gerrit-Change-Number: 81264 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: soc/intel/alderlake: Correctly set CNVi Reset and Clkreq pins
by Felix Held (Code Review) 15 Mar '24

15 Mar '24

Attention is currently required from: Dinesh Gehlot, Kapil Porwal, Nick Vaccaro, Sean Rhodes, Subrata Banik. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81080?usp=email ) Change subject: soc/intel/alderlake: Correctly set CNVi Reset and Clkreq pins ...................................................................... Patch Set 3: (1 comment) File src/soc/intel/alderlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/81080/comment/70dd0b83_26c9a120 : PS3, Line 839: if (CONFIG(SOC_ESPI)) { > Oh, good point. Could tie it do 1f. […] i'd guess that 1f.0 always needs to be enabled, since it's the primary function of that pci device. no idea about the external interface though. would probably be good if an Intel engineer can help looking into this -- To view, visit https://review.coreboot.org/c/coreboot/+/81080?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib534d3cfe888c1c538267caaf324c8ae743da496 Gerrit-Change-Number: 81080 Gerrit-PatchSet: 3 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Fri, 15 Mar 2024 21:40:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sean Rhodes <sean(a)starlabs.systems> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: 3rdparty/amd_blobs: update submodule pointer
by Felix Held (Code Review) 15 Mar '24

15 Mar '24

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81263?usp=email ) Change subject: 3rdparty/amd_blobs: update submodule pointer ...................................................................... 3rdparty/amd_blobs: update submodule pointer Update the amd_blobs submodule pointer to now include the following commit: picasso: Update PSP fw to version 00.08.14.7B TEST=Mandolin boots to the Windows 10 desktop and the GPU driver works Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: If1bd0b37bebcdd600465dbd48162792e2c32bfb7 --- M 3rdparty/amd_blobs 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/81263/1 diff --git a/3rdparty/amd_blobs b/3rdparty/amd_blobs index 64cdd7c..ae5fc7d 160000 --- a/3rdparty/amd_blobs +++ b/3rdparty/amd_blobs @@ -1 +1 @@ -Subproject commit 64cdd7c8ef199f5d79be14e7972fb7316f41beed +Subproject commit ae5fc7d27720267ceb2ccf2fbef0ab76b023ea26 -- To view, visit https://review.coreboot.org/c/coreboot/+/81263?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If1bd0b37bebcdd600465dbd48162792e2c32bfb7 Gerrit-Change-Number: 81263 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: libpayload: Make GPL commonlib includes available to payloads and tests
by Julius Werner (Code Review) 15 Mar '24

15 Mar '24

Julius Werner has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/81287?usp=email ) Change subject: libpayload: Make GPL commonlib includes available to payloads and tests ...................................................................... libpayload: Make GPL commonlib includes available to payloads and tests CB:77968 made some non-BSD commonlib files part of libpayload when CONFIG_LP_GPL is set. This patch exports those headers to the payload (again only when CONFIG_LP_GPL is set) so that payloads can also call the functions in them directly. Also make those includes available to tests so that their functions can be tested. There's no menuconfig for unit tests, so they are included unconditionally, but this should be fine since the tests are standalone and won't have to link with any proprietary third-party code. Change-Id: Ifc3e52ee5c3e51520f7b7d44b483bfcb0e8380f8 Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- M payloads/libpayload/Makefile.mk M payloads/libpayload/bin/lpgcc M payloads/libpayload/tests/Makefile.mk 3 files changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/81287/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81287?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifc3e52ee5c3e51520f7b7d44b483bfcb0e8380f8 Gerrit-Change-Number: 81287 Gerrit-PatchSet: 2 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: libpayload: Make GPL commonlib includes available to payloads
by Julius Werner (Code Review) 15 Mar '24

15 Mar '24

Julius Werner has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81287?usp=email ) Change subject: libpayload: Make GPL commonlib includes available to payloads ...................................................................... libpayload: Make GPL commonlib includes available to payloads CB:77968 made some non-BSD commonlib files part of libpayload when CONFIG_LP_GPL is set. This patch exports those headers to the payload (again only when CONFIG_LP_GPL is set) so that payloads can also call the functions in them directly. Change-Id: Ifc3e52ee5c3e51520f7b7d44b483bfcb0e8380f8 Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- M payloads/libpayload/Makefile.mk M payloads/libpayload/bin/lpgcc 2 files changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/81287/1 diff --git a/payloads/libpayload/Makefile.mk b/payloads/libpayload/Makefile.mk index e000868..afaa06d 100644 --- a/payloads/libpayload/Makefile.mk +++ b/payloads/libpayload/Makefile.mk @@ -133,6 +133,10 @@ find include -type f -exec install -m644 {} $(DESTDIR)/libpayload/{} \; cd $(coreboottop)/src/commonlib/bsd && find include -type d -exec install -m755 -d $(abspath $(DESTDIR))/libpayload/{} \; cd $(coreboottop)/src/commonlib/bsd && find include -type f -exec install -m644 {} $(abspath $(DESTDIR))/libpayload/{} \; +ifeq ($(CONFIG_LP_GPL),y) + cd $(coreboottop)/src/commonlib && find include -type d -exec install -m755 -d $(abspath $(DESTDIR))/libpayload/{} \; + cd $(coreboottop)/src/commonlib && find include -type f -exec install -m644 {} $(abspath $(DESTDIR))/libpayload/{} \; +endif install -m 644 $(obj)/libpayload-config.h $(DESTDIR)/libpayload/include $(foreach item,$(includes), \ install -m 755 -d $(DESTDIR)/libpayload/include/$(call extract_nth,2,$(item)); \ diff --git a/payloads/libpayload/bin/lpgcc b/payloads/libpayload/bin/lpgcc index 35fa558..bdc1518 100755 --- a/payloads/libpayload/bin/lpgcc +++ b/payloads/libpayload/bin/lpgcc @@ -170,6 +170,9 @@ _CFLAGS="$_CFLAGS -include $BASE/../../../src/commonlib/bsd/include/commonlib/bsd/compiler.h" _CFLAGS="$_CFLAGS -I$BASE/../../../src/commonlib/bsd/include" + if [ "$CONFIG_LP_GPL" = y ]; then + _CFLAGS="$_CFLAGS -I$BASE/../../../src/commonlib/include" + fi _CFLAGS="$_CFLAGS -I$BASE/../../../3rdparty/vboot/firmware/include" else _CFLAGS="$_CFLAGS -include $BASE/../include/commonlib/bsd/compiler.h" -- To view, visit https://review.coreboot.org/c/coreboot/+/81287?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifc3e52ee5c3e51520f7b7d44b483bfcb0e8380f8 Gerrit-Change-Number: 81287 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

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coreboot-gerrit March 2024