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Change subject: drivers/mipi: Add support for KD_KD101NE3_40TI panel
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/81583/comment/8f30c99d_54341acc :
PS2, Line 9: Add KD_KD101NE3_40TI serializable data to CBFS.
Mention K&D Technology?
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Change subject: mb/google/corsola: Enable the MIPI panel KD_KD101NE3_40TI for Wugtrio
......................................................................
Patch Set 1:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/81585/comment/c67cf7d3_f8bdf18e :
PS1, Line 7: for Wugtrio
Please put it into the prefix.
File src/mainboard/google/corsola/panel_wugtrio.c:
https://review.coreboot.org/c/coreboot/+/81585/comment/85e65ec2_9e62774c :
PS1, Line 23: mdelay(15);
Is that mentioned in the spec?
https://review.coreboot.org/c/coreboot/+/81585/comment/42794887_0d551b93 :
PS1, Line 30: KingDisplay
Kingtech Display?
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Change subject: mb/lenovo: Add ThinkCentre M920q (Cannon Lake)
......................................................................
Patch Set 6: Code-Review+1
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/80609/comment/9d24c760_24b70e65 :
PS6, Line 9: It may come with 8th or 9th Gen CPUs.
: i5-8500T has been tested here.
Please do not break lines just because a sentence ends.
https://review.coreboot.org/c/coreboot/+/80609/comment/a3cb3037_17a236e4 :
PS6, Line 24: - front audio jacks
Any idea why yet?
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Change subject: Update opensbi submodule to upstream master branch
......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS4:
it's hanging here
000000008002dbca T sbi_hart_hang
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Change subject: intel/common/pch: Add Kconfig SOC_INTEL_COMMON_IBL_BASE
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Patch Set 25: Code-Review+2
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Change subject: vc/intel/fsp/fsp2_0: Add GNR N-1 FSP headers
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Patch Set 26: Code-Review+2
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Change subject: soc/intel/xeon_sp: Redefine data types for 6th Gen adoption
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Patch Set 26: Code-Review+2
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Change subject: soc/intel/xeon_sp: Unshare Xeon-SP chip common codes
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Patch Set 26: Code-Review+2
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Hello Andrey Petrov, Arthur Heymans, Bora Guvendik, Christian Walter, Felix Held, Fred Reitberger, Jason Glenesk, Johnny Lin, Lean Sheng Tan, Matt DeVillier, Patrick Rudolph, Ronak Kanabar, Shuo Liu, Tim Chu, Wonkyu Kim, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#30).
Change subject: drivers/intel/fsp2_0: Support FSP 2.4 64-bits
......................................................................
drivers/intel/fsp2_0: Support FSP 2.4 64-bits
FSP 2.4 brings FSP 64-bits support which requires some adjustments in
coreboot:
- Stack alignment:
1. FSP functions must be called with the stack 16-bytes aligned.
This is already setup properly with the default value of the
`mpreferred-stack-boundary' compiler option (4).
2. The FSP stack buffer supplied by coreboot through the `StackBase'
UPD must be 16-bytes aligned.
- The EDK2 EFIAPI macro definition relies on compiler flags such as
__GNUC__ which is not working well when included by coreboot. While it
has no side-effect on i386 because the C calling convention used by
coreboot and FSP are the same, it breaks on x86_64 because FSP/UEFI
uses the Microsoft x64 calling convention while coreboot uses the
System V AMD64 ABI.
Fortunately, EDK2 header allows to override the EFIAPI
definition.
This appropriate attribute has to be set to all functions calling or
called by the FSP.
- Add FSP 2 Multi Processor Platform Initialization module a function
indirection to ensure that efi_ap_procedure functions are called with
the appropriate C calling convention.
- Add fsp print helper macros to print `efi_return_status_t' with the
appropriate format
- This commit adds a function indirection in MP PPI implementation to
ensure FSP callbacks are invoked using the appropriate C calling
convention.
BUG=b:329034258
TEST=verified on Lunar Lake RVP board (lnlrvp)
Change-Id: If0397f5cc8d0f4f1872bd37a001fe42e0c37ec99
Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com>
---
M 3rdparty/vboot
M src/drivers/intel/fsp2_0/debug.c
M src/drivers/intel/fsp2_0/fsp_debug_event.c
M src/drivers/intel/fsp2_0/include/fsp/debug.h
M src/drivers/intel/fsp2_0/include/fsp/fsp_debug_event.h
M src/drivers/intel/fsp2_0/include/fsp/info_header.h
M src/drivers/intel/fsp2_0/include/fsp/soc_binding.h
M src/drivers/intel/fsp2_0/include/fsp/util.h
M src/drivers/intel/fsp2_0/memory_init.c
M src/drivers/intel/fsp2_0/ppi/mp_service1.c
M src/drivers/intel/fsp2_0/ppi/mp_service2.c
M src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c
M src/drivers/intel/fsp2_0/silicon_init.c
M src/drivers/intel/fsp2_0/util.c
M src/include/efi/efi_datatype.h
M src/soc/amd/common/fsp/fsp_reset.c
M src/soc/intel/common/fsp_reset.c
17 files changed, 124 insertions(+), 70 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/80277/30
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