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Change subject: Support for creating hybrid vboot images
......................................................................
Patch Set 5:
(1 comment)
Patchset:
PS5:
> I disagree about lack of value of using updates. […]
The problem with trying to reuse the updates ChromeOS ships is not with where you switch for dual-booting, but with incompatibilites between vastly different coreboot versions. This goes back to the comments I made in CB:81505, that your solution of trying to get ToT coreboot to work fine with an older RW just doesn't scale. Yes, maybe you debugged this for Volteer and tested and prodded around enough until you got it kinda working, but that doesn't mean it will work for any other board and it doesn't mean it will keep working for Volteer.
So if you really insist on having a firmware that can run the official ChromeOS firmware updates and can also dual-boot into Windows, then again, I think the right solution for that is to take the ChromeOS firmware-volteer branch of coreboot and implement you Windows dual-booting stuff on top of that. But you can't really do it with coreboot ToT, and I don't think coreboot should take patches that try to do that because it's going to be incredibly brittle and it's only going to work on the handful of boards that people have time to debug it on and it's gonna stick us with a ton of extra code and cruft just to maintain backwards-compatibility to things that were removed or changed for good reason. There's a reason ChromeOS is cutting a firmware branch for every board rather than trying to ship RW updates from coreboot ToT to all of them, because keeping things in sync across the RO/RW interface just doesn't really work.
That's why I'm trying to suggest alternative solutions that don't require reusing the official ChromeOS firmware update, because then you can have your whole firmware built from ToT and have a solution that actually works reliably across all boards and will continue to work as more development happens in coreboot.
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Change subject: Update opensbi submodule to upstream master branch
......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS4:
dying here:
745 if (scratch->fw_rw_offset == 0 ||
746 (scratch->fw_rw_offset & (scratch->fw_rw_offset - 1)) != 0) {
747 sbi_printf("%s: fw_rw_offset is not a power of 2 (0x%lx)\n",
748 __func__, scratch->fw_rw_offset);
749 return SBI_EINVAL;
because
(gdb) print/x scratch->fw_rw_offset
$11 = 0x60000
(gdb) print/x (scratch->fw_rw_offset & (scratch->fw_rw_offset - 1))
$12 = 0x40000
fragile code.
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Change subject: Update opensbi submodule to upstream master branch
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Patch Set 4:
(1 comment)
Patchset:
PS4:
it's hanging at this
589 /*
590 * Do platform specific nascent (very early) initialization so
591 * that platform can initialize platform specific per-HART CSRs
592 * or per-HART devices.
593 */
594 if (sbi_platform_nascent_init(plat))
(gdb)
595 sbi_hart_hang();
This opensbi code makes me scream.
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Change subject: superio/ite: Add special fan vectors
......................................................................
Patch Set 7: Code-Review+1
(1 comment)
Patchset:
PS6:
> Although it would currently set the registers to their defaults if there is nothing set in the devic […]
Acknowledged
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Change subject: superio/ite: Add special fan vectors
......................................................................
Patch Set 7:
(1 comment)
Patchset:
PS6:
> currently, these fan vectors are being programmed even if they are unset in the mainboard devicetree […]
Although it would currently set the registers to their defaults if there is nothing set in the devicetree, this might make sense.
But I think it can be done more elegantly without leaking "devicetree-like" configuration into the mb's Kconfig.
We check `tmp_start==0` anyways to overwrite the default of 0xFF for the `CTL_LIMIT_START` register. I think it's elegant to return there and don't set any vector registers. `tmp_start` needs to be configured if one wants to use the vector functionality since the default temperature of 0xFF will effectively disable any effect the other registers have.
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Hello Matt DeVillier, Nico Huber, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/81426?usp=email
to look at the new patch set (#7).
The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: superio/ite: Add special fan vectors
......................................................................
superio/ite: Add special fan vectors
A number of ITE SIOs support "special fan control vectors", which
effectively allow non-linear fan speed control. This is for example used
by the vendor firmware of the "HP Pro 3500 Series".
The special vector registers won't be written to until the mb's
devicetree configures `FAN_VECX.tmp_start != 0`.
Change-Id: I93df2b5652fc3fde775b6161fa5bebc4a34d5e94
Signed-off-by: Joel Linn <jl(a)conductive.de>
---
M src/superio/ite/common/Kconfig
M src/superio/ite/common/env_ctrl.c
M src/superio/ite/common/env_ctrl.h
M src/superio/ite/common/env_ctrl_chip.h
M src/superio/ite/it8728f/Kconfig
M src/superio/ite/it8772f/Kconfig
6 files changed, 95 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/81426/7
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Change subject: mb/google/brya/var/bujia: Add VBT data files for bujia
......................................................................
Patch Set 5:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/81553/comment/ebcc5db5_d593741b :
PS5, Line 7: for bujia
Redundant as it’s in the prefix.
https://review.coreboot.org/c/coreboot/+/81553/comment/07fc93fb_a981f028 :
PS5, Line 11:
How did you create the VBT? What does it contain?
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Change subject: soc/intel/xeon_sp: Redefine data types for 6th Gen adoption
......................................................................
Patch Set 26:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/81040/comment/c87d7267_568ef58c :
PS26, Line 7: 6th Gen adoption
Add (GRP) at the end?
https://review.coreboot.org/c/coreboot/+/81040/comment/f1024965_2f17e36e :
PS26, Line 9: GraniteRapids
Granite Rapids
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Change subject: superio/ite: Add full-speed config option
......................................................................
Patch Set 2: Code-Review+1
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