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Hello Andrey Petrov, Arthur Heymans, Bora Guvendik, Christian Walter, Felix Held, Fred Reitberger, Jason Glenesk, Johnny Lin, Lean Sheng Tan, Matt DeVillier, Patrick Rudolph, Ronak Kanabar, Shuo Liu, Tim Chu, Wonkyu Kim, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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The following approvals got outdated and were removed:
Code-Review+1 by Bora Guvendik
Change subject: drivers/intel/fsp2_0: Support FSP 2.4 64-bits
......................................................................
drivers/intel/fsp2_0: Support FSP 2.4 64-bits
FSP 2.4 brings FSP 64-bits support which requires some adjustments in
coreboot:
- Stack alignment:
1. FSP functions must be called with the stack 16-bytes aligned.
This is already setup properly with the default value of the
`mpreferred-stack-boundary' compiler option (4).
2. The FSP stack buffer supplied by coreboot through the `StackBase'
UPD must be 16-bytes aligned.
- The EDK2 EFIAPI macro definition relies on compiler flags such as
__GNUC__ which is not working well when included by coreboot. While it
has no side-effect on i386 because the C calling convention used by
coreboot and FSP are the same, it breaks on x86_64 because FSP/UEFI
uses the Microsoft x64 calling convention while coreboot uses the
System V AMD64 ABI.
Fortunately, EDK2 header allows to override the EFIAPI
definition.
This appropriate attribute has to be set to all functions calling or
called by the FSP.
- Add FSP 2 Multi Processor Platform Initialization module a function
indirection to ensure that efi_ap_procedure functions are called with
the appropriate C calling convention.
- Add fsp print helper macros to print `efi_return_status_t' with the
appropriate format
- This commit adds a function indirection in MP PPI implementation to
ensure FSP callbacks are invoked using the appropriate C calling
convention.
BUG=b:329034258
TEST=verified on Lunar Lake RVP board (lnlrvp)
Change-Id: If0397f5cc8d0f4f1872bd37a001fe42e0c37ec99
Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com>
---
M src/drivers/intel/fsp2_0/debug.c
M src/drivers/intel/fsp2_0/fsp_debug_event.c
M src/drivers/intel/fsp2_0/include/fsp/debug.h
M src/drivers/intel/fsp2_0/include/fsp/fsp_debug_event.h
M src/drivers/intel/fsp2_0/include/fsp/info_header.h
M src/drivers/intel/fsp2_0/include/fsp/soc_binding.h
M src/drivers/intel/fsp2_0/include/fsp/util.h
M src/drivers/intel/fsp2_0/memory_init.c
M src/drivers/intel/fsp2_0/ppi/mp_service1.c
M src/drivers/intel/fsp2_0/ppi/mp_service2.c
M src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c
M src/drivers/intel/fsp2_0/silicon_init.c
M src/drivers/intel/fsp2_0/util.c
M src/include/efi/efi_datatype.h
M src/soc/amd/common/fsp/fsp_reset.c
M src/soc/intel/common/fsp_reset.c
16 files changed, 122 insertions(+), 69 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/80277/29
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Change subject: drivers/intel/fsp2_0: Support FSP 2.4 64-bits
......................................................................
Patch Set 28:
(1 comment)
File src/drivers/intel/fsp2_0/include/fsp/fsp_debug_event.h:
https://review.coreboot.org/c/coreboot/+/80277/comment/bed191c2_bd7e9fcf :
PS2, Line 13: #include <efi/efi_datatype.h>
> Hey Subrata, I've been thinking about this inclusion order issue. […]
Done
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Bora Guvendik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80277?usp=email )
Change subject: drivers/intel/fsp2_0: Support FSP 2.4 64-bits
......................................................................
Patch Set 28: Code-Review+1
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Hello Andrey Petrov, Arthur Heymans, Bora Guvendik, Christian Walter, Felix Held, Fred Reitberger, Jason Glenesk, Johnny Lin, Lean Sheng Tan, Matt DeVillier, Patrick Rudolph, Ronak Kanabar, Shuo Liu, Tim Chu, Wonkyu Kim, build bot (Jenkins),
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Change subject: drivers/intel/fsp2_0: Support FSP 2.4 64-bits
......................................................................
drivers/intel/fsp2_0: Support FSP 2.4 64-bits
FSP 2.4 brings FSP 64-bits support which requires some adjustments in
coreboot:
- Stack alignment:
1. FSP functions must be called with the stack 16-bytes aligned.
This is already setup properly with the default value of the
`mpreferred-stack-boundary' compiler option (4).
2. The FSP stack buffer supplied by coreboot through the `StackBase'
UPD must be 16-bytes aligned.
- The EDK2 EFIAPI macro definition relies on compiler flags such as
__GNUC__ which is not working well when included by coreboot. While it
has no side-effect on i386 because the C calling convention used by
coreboot and FSP are the same, it breaks on x86_64 because FSP/UEFI
uses the Microsoft x64 calling convention while coreboot uses the
System V AMD64 ABI.
Fortunately, EDK2 header allows to override the EFIAPI
definition.
This appropriate attribute has to be set to all functions calling or
called by the FSP.
- Add FSP 2 Multi Processor Platform Initialization module a function
indirection to ensure that efi_ap_procedure functions are called with
the appropriate C calling convention.
- Add fsp print helper macros to print `efi_return_status_t' with the
appropriate format
- This commit adds a function indirection in MP PPI implementation to
ensure FSP callbacks are invoked using the appropriate C calling
convention.
BUG=b:329034258
TEST=verified on Lunar Lake RVP board (lnlrvp)
Change-Id: If0397f5cc8d0f4f1872bd37a001fe42e0c37ec99
Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com>
---
M src/drivers/intel/fsp2_0/debug.c
M src/drivers/intel/fsp2_0/fsp_debug_event.c
M src/drivers/intel/fsp2_0/include/fsp/debug.h
M src/drivers/intel/fsp2_0/include/fsp/fsp_debug_event.h
M src/drivers/intel/fsp2_0/include/fsp/info_header.h
M src/drivers/intel/fsp2_0/include/fsp/soc_binding.h
M src/drivers/intel/fsp2_0/include/fsp/util.h
M src/drivers/intel/fsp2_0/memory_init.c
M src/drivers/intel/fsp2_0/ppi/mp_service1.c
M src/drivers/intel/fsp2_0/ppi/mp_service2.c
M src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c
M src/drivers/intel/fsp2_0/silicon_init.c
M src/drivers/intel/fsp2_0/util.c
M src/include/efi/efi_datatype.h
M src/soc/amd/common/fsp/fsp_reset.c
M src/soc/intel/common/fsp_reset.c
16 files changed, 121 insertions(+), 68 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/80277/28
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ron minnich has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81543?usp=email )
Change subject: Update opensbi submodule to upstream master branch
......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS3:
> damn. I gave resizing the opensbi area a try, still doesn't work. […]
by "doesn't work" -- it builds fine with my memlayout.ld change for qemu, but opensbi prints no info.
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Change subject: Update opensbi submodule to upstream master branch
......................................................................
Patch Set 3:
(2 comments)
Patchset:
PS2:
> mention the coreboot code changes in the commit message?
done.
Patchset:
PS3:
> This breaks QEMU-RISCV for me. […]
damn. I gave resizing the opensbi area a try, still doesn't work.
ironically, the coreboot sbi builds and boots a kernel just fine.
Can you look at my qemu memlayout change and see what I got wrong.
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Attention is currently required from: Martin L Roth, Maximilian Brune, Philipp Hug, ron minnich.
Hello Martin L Roth, Maximilian Brune, Philipp Hug, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/81543?usp=email
to look at the new patch set (#4).
The following approvals got outdated and were removed:
Code-Review+2 by Martin L Roth, Code-Review-1 by Maximilian Brune, Verified+1 by build bot (Jenkins)
Change subject: Update opensbi submodule to upstream master branch
......................................................................
Update opensbi submodule to upstream master branch
Updating from commit id 5019fd124b4c (2022-09-01):
include: sbi: Reduce includes in sbi_pmu.h
to commit id 5186da687deb (2024-03-20):
platform: generic: allwinner: sun20i-d1: Remove duplicated CSR definitions
This brings in 465 new commits.
Tested on the SiFive unmatched.
Fails on qemu, it now builds, but fails to boot.
The changes to src/mainboard/emulation/qemu-riscv/memlayout.ld
make it easier to read, although our line length rules reduce
the readability a good bit.
Because the coreboot opensbi shim uses include files from opensbi,
it was necessary to do this:
because coreboot also defines __always_inline in
src/commonlib/bsd/include/commonlib/bsd/compiler.h
and opensbi does not have a guard around their definition.
Change-Id: I50ce0ba3b6409247a94b49565cc04454903e88d0
Signed-off-by: Martin Roth <gaumless(a)gmail.com>
Signed-off-by: Ronald G Minnich <rminnich(a)gmail.com>
---
M 3rdparty/opensbi
M src/arch/riscv/opensbi.c
M src/mainboard/emulation/qemu-riscv/memlayout.ld
M src/soc/sifive/fu540/memlayout.ld
M src/soc/sifive/fu740/memlayout.ld
5 files changed, 31 insertions(+), 16 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/81543/4
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Emilie Roberts has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81354?usp=email )
Change subject: mb/google/brya: Fix mux_conn index used by ec/google/chromeec
......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS4:
> @hadrosaur@google.com to test on Felwinter. […]
Will do, have been unable to confirm on remote hardware. Will try to locate a physical felwinter device.
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Change subject: superio/ite: Add function to disable PME# output
......................................................................
Patch Set 1: Code-Review+2
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Change subject: superio/ite: Add function to disable 3VSBSW# signal
......................................................................
Patch Set 1: Code-Review+2
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