coreboot-gerrit March 2024

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[XL] Change in coreboot[main]: mb/lenovo: Add ThinkCentre M920q (Cannon Lake)
by Michał Kopeć (Code Review) 29 Mar '24

29 Mar '24

Attention is currently required from: Alexander Couzens, Maciej Pijanowski, Paul Menzel. Michał Kopeć has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80609?usp=email ) Change subject: mb/lenovo: Add ThinkCentre M920q (Cannon Lake) ...................................................................... Patch Set 6: (3 comments) File src/mainboard/lenovo/m920q/devicetree.cb: https://review.coreboot.org/c/coreboot/+/80609/comment/3e147e99_32e30d78 : PS6, Line 58: # not populated. Probably enabled on some variants only. Seems to be populated on the M920x variant. File src/mainboard/lenovo/m920q/romstage.c: https://review.coreboot.org/c/coreboot/+/80609/comment/77151dc4_b5abb8a9 : PS6, Line 13: .spd[0] = { Platform only has 2 DIMMs https://review.coreboot.org/c/coreboot/+/80609/comment/3271581c_7d6c1d68 : PS6, Line 33: /* Rcomp target values for CFL-S, DDR4 and 2 DIMMs per channel */ There's 1 DIMM per channel here -- To view, visit https://review.coreboot.org/c/coreboot/+/80609?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iea1dc5745c0ecf687fa18b793f0aab4b0855d6d4 Gerrit-Change-Number: 80609 Gerrit-PatchSet: 6 Gerrit-Owner: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Comment-Date: Fri, 29 Mar 2024 11:36:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/google/corsola: Add new board 'Wugtrio'
by Yang Wu (Code Review) 29 Mar '24

29 Mar '24

Attention is currently required from: Hung-Te Lin, Ruihai Zhou, Xuxin Xiong, Yidi Lin, Yu-Ping Wu. Yang Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81584?usp=email ) Change subject: mb/google/corsola: Add new board 'Wugtrio' ...................................................................... Patch Set 2: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/81584/comment/4164fcee_fce3d898 : PS1, Line 7: Add new board 'Wugtrio' and enable mipi panel > split to two commit: […] Done File src/mainboard/google/corsola/Kconfig: https://review.coreboot.org/c/coreboot/+/81584/comment/cff01186_83578028 : PS1, Line 23: select MIPI_PANEL_STA_HIMAX83102_J02 : select MIPI_PANEL_STA_ILI9882T : select MIPI_PANEL_KD_KD101NE3_40TI > Move to BOARD_SPECIFIC_OPTIONS, and suggest to change: […] Done https://review.coreboot.org/c/coreboot/+/81584/comment/829f3010_602a4ac7 : PS1, Line 88: > remove Done -- To view, visit https://review.coreboot.org/c/coreboot/+/81584?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I84cb86bf4eb2762b3072cb030b3c34a08c6b869d Gerrit-Change-Number: 81584 Gerrit-PatchSet: 2 Gerrit-Owner: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Xuxin Xiong <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Attention: Xuxin Xiong <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Fri, 29 Mar 2024 10:44:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: drivers/mipi: Add support for KD_KD101NE3_40TI panel
by Yang Wu (Code Review) 29 Mar '24

29 Mar '24

Attention is currently required from: Ruihai Zhou, Xuxin Xiong, Yu-Ping Wu. Yang Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81583?usp=email ) Change subject: drivers/mipi: Add support for KD_KD101NE3_40TI panel ...................................................................... Patch Set 2: (1 comment) File src/drivers/mipi/Makefile.mk: https://review.coreboot.org/c/coreboot/+/81583/comment/2b321045_dce47380 : PS1, Line 24: panel-params-$(CONFIG_MIPI_PANEL_KD_KD101NE3_40TI) += panel-KD_KD101NE3_40TI > Sort alphabetically Done -- To view, visit https://review.coreboot.org/c/coreboot/+/81583?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibed67d2f3321fef332ab1e80f06225e27d205f71 Gerrit-Change-Number: 81583 Gerrit-PatchSet: 2 Gerrit-Owner: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Xuxin Xiong <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Attention: Xuxin Xiong <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Fri, 29 Mar 2024 10:43:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: mb/google/corsola: Enable the MIPI panel KD_KD101NE3_40TI for Wugtrio
by Yang Wu (Code Review) 29 Mar '24

29 Mar '24

Attention is currently required from: Hung-Te Lin, Yidi Lin, Yu-Ping Wu. Yang Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81585?usp=email ) Change subject: mb/google/corsola: Enable the MIPI panel KD_KD101NE3_40TI for Wugtrio ...................................................................... mb/google/corsola: Enable the MIPI panel KD_KD101NE3_40TI for Wugtrio Enable the MIPI panel KD_KD101NE3_40TI for Wugtrio. BUG=b:331870701 TEST=emerge-staryu coreboot chromeos-bootimage and display normally BRANCH=Corsola Change-Id: I586de68da4d0ee2dd5b7baea92ebb06db9fcfe8b Signed-off-by: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/corsola/Kconfig M src/mainboard/google/corsola/Makefile.mk A src/mainboard/google/corsola/panel_wugtrio.c 3 files changed, 56 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/81585/1 diff --git a/src/mainboard/google/corsola/Kconfig b/src/mainboard/google/corsola/Kconfig index d5386ae..fb2e0e7 100644 --- a/src/mainboard/google/corsola/Kconfig +++ b/src/mainboard/google/corsola/Kconfig @@ -18,16 +18,16 @@ BOARD_GOOGLE_TENTACRUEL config BOARD_GOOGLE_STARYU_COMMON - def_bool BOARD_GOOGLE_STARMIE - select MIPI_PANEL_STA_HIMAX83102_J02 - select MIPI_PANEL_STA_ILI9882T + def_bool BOARD_GOOGLE_STARMIE || \ + BOARD_GOOGLE_WUGTRIO if BOARD_GOOGLE_CORSOLA_COMMON config CORSOLA_SDCARD_INIT def_bool BOARD_GOOGLE_MAGIKARP || \ BOARD_GOOGLE_TENTACRUEL || \ - BOARD_GOOGLE_KINGLER_COMMON + BOARD_GOOGLE_KINGLER_COMMON || \ + BOARD_GOOGLE_WUGTRIO config BOARD_SPECIFIC_OPTIONS def_bool y @@ -61,6 +61,9 @@ select RTC select FW_CONFIG select FW_CONFIG_SOURCE_CHROMEEC_CBI + select MIPI_PANEL_KD_KD101NE3_40TI if BOARD_GOOGLE_WUGTRIO + select MIPI_PANEL_STA_HIMAX83102_J02 if BOARD_GOOGLE_STARMIE + select MIPI_PANEL_STA_ILI9882T if BOARD_GOOGLE_STARMIE config VBOOT select EC_GOOGLE_CHROMEEC_SWITCHES diff --git a/src/mainboard/google/corsola/Makefile.mk b/src/mainboard/google/corsola/Makefile.mk index 1442f33..818065a 100644 --- a/src/mainboard/google/corsola/Makefile.mk +++ b/src/mainboard/google/corsola/Makefile.mk @@ -26,3 +26,5 @@ ramstage-y += reset.c ramstage-$(CONFIG_BOARD_GOOGLE_STARMIE) += panel_starmie.c + +ramstage-$(CONFIG_BOARD_GOOGLE_WUGTRIO) += panel_wugtrio.c diff --git a/src/mainboard/google/corsola/panel_wugtrio.c b/src/mainboard/google/corsola/panel_wugtrio.c new file mode 100644 index 0000000..bd0fe9f --- /dev/null +++ b/src/mainboard/google/corsola/panel_wugtrio.c @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <delay.h> +#include <gpio.h> +#include <soc/regulator.h> + +#include "gpio.h" +#include "panel.h" + +static void mipi_panel_power_on(void) +{ + mainboard_set_regulator_voltage(MTK_REGULATOR_VIO18, 1800000); + udelay(100); + + mainboard_set_regulator_voltage(MTK_REGULATOR_VCN33, 3300000); + + gpio_output(GPIO_EN_PP3300_DISP_X, 1); + mdelay(5); + + /* DISP_RST_1V8_L */ + gpio_output(GPIO_EDPBRDG_RST_L, 1); + mdelay(15); + gpio_output(GPIO_EDPBRDG_RST_L, 0); + udelay(20); + gpio_output(GPIO_EDPBRDG_RST_L, 1); +} + +static struct panel_description wugtrio_panels[] = { + /* KingDisplay panel with bias IC on it */ + [4] = { + .configure_backlight = backlight_control, + .power_on = mipi_panel_power_on, + .name = "KD_KD101NE3_40TI", + .disp_path = DISP_PATH_MIPI, + .orientation = LB_FB_ORIENTATION_LEFT_UP, + }, +}; + +struct panel_description *get_panel_description(void) +{ + uint32_t id = panel_id() & 0xF; + if (id >= ARRAY_SIZE(wugtrio_panels)) + return NULL; + + return &wugtrio_panels[id]; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/81585?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I586de68da4d0ee2dd5b7baea92ebb06db9fcfe8b Gerrit-Change-Number: 81585 Gerrit-PatchSet: 1 Gerrit-Owner: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: mb/google/corsola: Add new board 'Wugtrio'
by Yang Wu (Code Review) 29 Mar '24

29 Mar '24

Attention is currently required from: Hung-Te Lin, Xuxin Xiong, Yang Wu, Yidi Lin, Yu-Ping Wu. Hello Hung-Te Lin, Ruihai Zhou, Xuxin Xiong, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81584?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/google/corsola: Add new board 'Wugtrio' ...................................................................... mb/google/corsola: Add new board 'Wugtrio' Add a new Staryu follower 'Wugtrio'. BUG=b:331870701 TEST=emerge-staryu coreboot chromeos-bootimage BRANCH=Corsola Change-Id: I84cb86bf4eb2762b3072cb030b3c34a08c6b869d Signed-off-by: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/corsola/Kconfig M src/mainboard/google/corsola/Kconfig.name 2 files changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/81584/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81584?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I84cb86bf4eb2762b3072cb030b3c34a08c6b869d Gerrit-Change-Number: 81584 Gerrit-PatchSet: 2 Gerrit-Owner: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Xuxin Xiong <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Xuxin Xiong <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[main]: drivers/mipi: Add support for KD_KD101NE3_40TI panel
by Yang Wu (Code Review) 29 Mar '24

29 Mar '24

Attention is currently required from: Xuxin Xiong, Yang Wu, Yu-Ping Wu. Hello Ruihai Zhou, Xuxin Xiong, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81583?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: drivers/mipi: Add support for KD_KD101NE3_40TI panel ...................................................................... drivers/mipi: Add support for KD_KD101NE3_40TI panel Add KD_KD101NE3_40TI serializable data to CBFS. Datasheet: KD101NE3-40TI-A003 _Pre SPEC_20231218.pdf BUG=b:331870701 TEST=build and check the CBFS include the panel BRANCH=None Change-Id: Ibed67d2f3321fef332ab1e80f06225e27d205f71 Signed-off-by: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> --- M src/drivers/mipi/Kconfig M src/drivers/mipi/Makefile.mk A src/drivers/mipi/panel-KD_KD101NE3_40TI.c 3 files changed, 225 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/81583/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81583?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibed67d2f3321fef332ab1e80f06225e27d205f71 Gerrit-Change-Number: 81583 Gerrit-PatchSet: 2 Gerrit-Owner: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Xuxin Xiong <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Xuxin Xiong <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[main]: mb/google/brya/var/nova: Initial GPIO configurations
by Kenneth Chan (Code Review) 29 Mar '24

29 Mar '24

Kenneth Chan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81561?usp=email ) Change subject: mb/google/brya/var/nova: Initial GPIO configurations ...................................................................... mb/google/brya/var/nova: Initial GPIO configurations Upload initial GPIO configuration for nova based on proto schematics. BUG=b: TEST=FW_NAME=nova emerge-constitution coreboot chromeos-bootimage Change-Id: I75de510bf9d372e8cc3c7480b4b2e408cf41601c Signed-off-by: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> --- A src/mainboard/google/brya/variants/nova/Makefile.mk A src/mainboard/google/brya/variants/nova/gpio.c 2 files changed, 198 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/81561/1 diff --git a/src/mainboard/google/brya/variants/nova/Makefile.mk b/src/mainboard/google/brya/variants/nova/Makefile.mk new file mode 100644 index 0000000..d38141c --- /dev/null +++ b/src/mainboard/google/brya/variants/nova/Makefile.mk @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0-only +bootblock-y += gpio.c + +romstage-y += gpio.c + +ramstage-y += gpio.c diff --git a/src/mainboard/google/brya/variants/nova/gpio.c b/src/mainboard/google/brya/variants/nova/gpio.c new file mode 100644 index 0000000..48a1baa --- /dev/null +++ b/src/mainboard/google/brya/variants/nova/gpio.c @@ -0,0 +1,192 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/helpers.h> +#include <soc/gpio.h> + +/* Pad configuration in ramstage */ +static const struct pad_config override_gpio_table[] = { + /* A14 : USB_OC1# ==> NC */ + PAD_NC(GPP_A14, NONE), + /* A15 : USB_OC2# ==> NC */ + PAD_NC(GPP_A15, NONE), + /* A19 : DDSP_HPD1 ==> NC */ + PAD_NC(GPP_A19, NONE), + /* A20 : DDSP_HPD2 ==> NC */ + PAD_NC(GPP_A20, NONE), + /* A21 : DDPC_CTRCLK ==> NC */ + PAD_NC(GPP_A21, NONE), + /* A22 : DDPC_CTRLDATA ==> NC */ + PAD_NC(GPP_A22, NONE), + + /* B7 : ISH_12C1_SDA ==> PCH_I2C_MISCB_SDA */ + PAD_CFG_NF_LOCK(GPP_B7, NONE, NF2, LOCK_CONFIG), + /* B8 : ISH_I2C1_SCL ==> PCH_I2C_MISCB_SCL */ + PAD_CFG_NF_LOCK(GPP_B8, NONE, NF2, LOCK_CONFIG), + + /* B15 : TIME_SYNC0 ==> HP_INT_L */ + PAD_CFG_GPI_INT(GPP_B15, NONE, PLTRST, EDGE_BOTH), + /* B16 : I2C5_SDA ==> PCH_I2C_TPU_SDA */ + PAD_CFG_NF_LOCK(GPP_B16, NONE, NF2, LOCK_CONFIG), + /* B17 : I2C5_SCL ==> PCH_I2C_TPU_SCL */ + PAD_CFG_NF_LOCK(GPP_B17, NONE, NF2, LOCK_CONFIG), + + /* C0 : SMBCLK ==> NC */ + PAD_NC(GPP_C0, NONE), + /* C1 : SMBDATA ==> NC */ + PAD_NC(GPP_C1, NONE), + /* C3 : SML0CLK ==> NC */ + PAD_NC(GPP_C3, NONE), + /* C4 : SML0DATA ==> SMBUS_ISP_SCALAR */ + PAD_CFG_GPO(GPP_C4, 0, DEEP), + + /* D0 : ISH_GP0 ==> BOOT_SEL_N */ + PAD_CFG_GPO(GPP_D0, 1, DEEP), + /* D1 : ISH_GP1 ==> REC_MODE */ + PAD_CFG_GPO(GPP_D1, 1, DEEP), + /* D2 : ISH_GP2 ==> DEV_MODE_CTRL */ + PAD_CFG_GPO(GPP_D2, 1, DEEP), + /* D3 : ISH_GP3 ==> BOOT_IND */ + PAD_CFG_GPO(GPP_D3, 1, DEEP), + /* D9 : ISH_SPI_CS# ==> NC */ + PAD_NC_LOCK(GPP_D9, NONE, LOCK_CONFIG), + /* D13 : ISH_UART0_RXD ==> NC */ + PAD_NC_LOCK(GPP_D13, NONE, LOCK_CONFIG), + /* D14 : ISH_UART0_TXD ==> QSPI_MR_N */ + PAD_CFG_GPO(GPP_D14, 1, DEEP), + /* D15 : ISH_UART0_RTS# ==> USI_RST_L */ + PAD_CFG_GPO(GPP_D15, 1, DEEP), + /* D16 : ISH_UART0_CTS# ==> USI_INT */ + PAD_CFG_GPI_APIC(GPP_D16, NONE, PLTRST, LEVEL, NONE), + /* D17 : UART1_RXD ==> PCH_RX_TSUM_UART_TX */ + PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), + /* D18 : UART1_TXD ==> PCH_TX_TSUM_UART_RX */ + PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), + + /* E4 : SATA_DEVSLP0 ==> M2_SSD_PE_WAKE_ODL */ + PAD_CFG_GPI(GPP_E4, NONE, DEEP), + /* E5 : SATA_DEVSLP1 ==> M2_SSD_DEVSLP_OD */ + PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF1), + /* E9 : USB_OC0# ==> USB_C0_OC_ODL */ + PAD_NC_LOCK(GPP_E9, NONE, LOCK_CONFIG), + /* E18 : DDP1_CTRLCLK ==> NC */ + PAD_NC(GPP_E18, NONE), + /* E19 : DDP1_CTRLDATA ==> GPP_E19_STRAP */ + PAD_CFG_GPI(GPP_E19, NONE, DEEP), + /* E20 : DDP2_CTRLCLK ==> NC */ + PAD_NC(GPP_E20, NONE), + /* E21 : DDP2_CTRLDATA ==> GPP_E21_STRAP */ + PAD_CFG_GPI(GPP_E21, NONE, DEEP), + + /* H12 : I2C7_SDA ==> NC */ + PAD_NC_LOCK(GPP_H12, NONE, LOCK_CONFIG), + /* H13 : I2C7_SCL ==> NC */ + PAD_NC_LOCK(GPP_H13, NONE, LOCK_CONFIG), + /* H15 : DDPB_CTRLCLK ==> NC */ + PAD_NC(GPP_H15, NONE), + /* H17 : DDPB_CTRLDATA ==> NC */ + PAD_NC(GPP_H17, NONE), + + /* F11 : THC1_SPI2_CLK ==> NC */ + PAD_NC_LOCK(GPP_F11, NONE, LOCK_CONFIG), + /* F12 : GSXDOUT ==> NC */ + PAD_NC_LOCK(GPP_F12, NONE, LOCK_CONFIG), + /* F13 : GSXDOUT ==> NC */ + PAD_NC_LOCK(GPP_F13, NONE, LOCK_CONFIG), + /* F15 : GSXSRESET# ==> NC */ + PAD_NC_LOCK(GPP_F15, NONE, LOCK_CONFIG), + /* F16 : GSXCLK ==> NC */ + PAD_NC_LOCK(GPP_F16, NONE, LOCK_CONFIG), + + /* R1 : HDA_SYNC ==> I2S_PCH_TX_HP_RX_STRAP */ + PAD_CFG_GPI(GPP_R1, NONE, DEEP), + /* R2 : HDA_SDO ==> NC */ + PAD_NC(GPP_R2, NONE), + /* R3 : HDA_SDIO ==> NC */ + PAD_NC(GPP_R3, NONE), + /* R4 : HDA_RST# ==> NC */ + PAD_NC(GPP_R4, NONE), + /* R5 : HDA_SDI1 ==> NC */ + PAD_NC(GPP_R5, NONE), + /* R6 : I2S2_TXD ==> NC */ + PAD_NC(GPP_R6, NONE), + /* R7 : I2S2_RXD ==> NC */ + PAD_NC(GPP_R7, NONE), + + /* S0 : SNDW0_CLK ==> PCH_I2S_SCLK_MX8M */ + PAD_CFG_NF(GPP_S0, NONE, DEEP, NF4), + /* S1 : SNDW0_DATA ==> PCH_I2S_SFRM_MX8M */ + PAD_CFG_NF(GPP_S1, NONE, DEEP, NF4), + /* S2 : SNDW1_CLK ==> PCH_I2S_TX_MX8M_RX */ + PAD_CFG_NF(GPP_S2, NONE, DEEP, NF4), + /* S3 : SNDW1_DATA ==> PCH_I2S_RX_MX8M_TX */ + PAD_CFG_NF(GPP_S3, NONE, DEEP, NF4), +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), + /* B4 : PROC_GP3 ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_B4, 0, DEEP), + /* E15 : RSVD_TP ==> PCH_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), + /* F14 : GSXDIN ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_F14, 1, DEEP), + /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_F18, NONE, DEEP), + /* H6 : I2C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + /* H7 : I2C1_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), + /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), + /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), + + /* CPU PCIe VGPIO for PEG60 */ + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, PLTRST, NF1), +}; + +static const struct pad_config romstage_gpio_table[] = { + /* B4 : PROC_GP3 ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_B4, 1, DEEP), +}; + +const struct pad_config *variant_gpio_override_table(size_t *num) +{ + *num = ARRAY_SIZE(override_gpio_table); + return override_gpio_table; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +const struct pad_config *variant_romstage_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(romstage_gpio_table); + return romstage_gpio_table; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/81561?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I75de510bf9d372e8cc3c7480b4b2e408cf41601c Gerrit-Change-Number: 81561 Gerrit-PatchSet: 1 Gerrit-Owner: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[main]: drivers/mipi: Add support for KD_KD101NE3_40TI panel
by Ruihai Zhou (Code Review) 29 Mar '24

29 Mar '24

Attention is currently required from: Xuxin Xiong, Yang Wu. Ruihai Zhou has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81583?usp=email ) Change subject: drivers/mipi: Add support for KD_KD101NE3_40TI panel ...................................................................... Patch Set 1: (1 comment) File src/drivers/mipi/Makefile.mk: https://review.coreboot.org/c/coreboot/+/81583/comment/823a10e4_5d7d7472 : PS1, Line 24: panel-params-$(CONFIG_MIPI_PANEL_KD_KD101NE3_40TI) += panel-KD_KD101NE3_40TI Sort alphabetically -- To view, visit https://review.coreboot.org/c/coreboot/+/81583?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibed67d2f3321fef332ab1e80f06225e27d205f71 Gerrit-Change-Number: 81583 Gerrit-PatchSet: 1 Gerrit-Owner: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Xuxin Xiong <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Attention: Xuxin Xiong <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Fri, 29 Mar 2024 09:29:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[main]: mb/google/corsola: Add new board 'Wugtrio' and enable mipi panel
by Ruihai Zhou (Code Review) 29 Mar '24

29 Mar '24

Attention is currently required from: Hung-Te Lin, Xuxin Xiong, Yang Wu, Yidi Lin, Yu-Ping Wu. Ruihai Zhou has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81584?usp=email ) Change subject: mb/google/corsola: Add new board 'Wugtrio' and enable mipi panel ...................................................................... Patch Set 1: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/81584/comment/61fa7be0_ad5b30e2 : PS1, Line 7: Add new board 'Wugtrio' and enable mipi panel split to two commit: 1. Add new board 'Wugtrio' 2. Enable KD_KD101NE3_40TI MIPI panel for Wugtrio File src/mainboard/google/corsola/Kconfig: https://review.coreboot.org/c/coreboot/+/81584/comment/8d6dccce_2794f197 : PS1, Line 23: select MIPI_PANEL_STA_HIMAX83102_J02 : select MIPI_PANEL_STA_ILI9882T : select MIPI_PANEL_KD_KD101NE3_40TI Move to BOARD_SPECIFIC_OPTIONS, and suggest to change: ``` select MIPI_PANEL_KD_KD101NE3_40TI if BOARD_GOOGLE_WUGTRIO select MIPI_PANEL_STA_HIMAX83102_J02 if BOARD_GOOGLE_STARMIE select MIPI_PANEL_STA_ILI9882T if BOARD_GOOGLE_STARMIE ``` https://review.coreboot.org/c/coreboot/+/81584/comment/9152ca44_48ee5e1b : PS1, Line 88: remove -- To view, visit https://review.coreboot.org/c/coreboot/+/81584?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I84cb86bf4eb2762b3072cb030b3c34a08c6b869d Gerrit-Change-Number: 81584 Gerrit-PatchSet: 1 Gerrit-Owner: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Xuxin Xiong <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Xuxin Xiong <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Fri, 29 Mar 2024 09:27:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[main]: Update opensbi submodule to upstream master branch
by Maximilian Brune (Code Review) 29 Mar '24

29 Mar '24

Attention is currently required from: Philipp Hug, ron minnich. Maximilian Brune has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81543?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: Update opensbi submodule to upstream master branch ...................................................................... Patch Set 3: Code-Review-1 (1 comment) Patchset: PS3: This breaks QEMU-RISCV for me. I think it is because OpenSBI recently changed its requirements regarding where in memory to place it (for PMP regions). We probably need to change the memlayout.ld file for that. -- To view, visit https://review.coreboot.org/c/coreboot/+/81543?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I50ce0ba3b6409247a94b49565cc04454903e88d0 Gerrit-Change-Number: 81543 Gerrit-PatchSet: 3 Gerrit-Owner: ron minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Fri, 29 Mar 2024 09:16:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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