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Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81554?usp=email )
Change subject: device/device_util: Rename dev_get_pci_domain
......................................................................
Patch Set 5:
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/81554/comment/bf79eb36_450c2c3a :
PS4, Line 9: In coreboot, domain indicates hardware units that functions as PCIe
: host bridges.
> No, they basically provide/group resource windows. It's not about PCI. […]
Done
File src/device/device_util.c:
https://review.coreboot.org/c/coreboot/+/81554/comment/9a80b3b2_a0552eda :
PS4, Line 253: /* Returns the PCI domain for the given PCI device */
> Drop "PCI" please.
Done
https://review.coreboot.org/c/coreboot/+/81554/comment/38c9c86a_6a93c272 :
PS4, Line 256: assert(is_pci(dev));
> Missed this.
Done
https://review.coreboot.org/c/coreboot/+/81554/comment/c56e99c1_2d9ba8ed :
PS4, Line 258: PCI
> Same.
Done
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Change subject: mb/intel/beechnutcity_crb: Add GNR/SRF-SP 2S server board Beechnut City
......................................................................
mb/intel/beechnutcity_crb: Add GNR/SRF-SP 2S server board Beechnut City
Beechnut City CRB is the 2 socket reference board for 6th Gen Xeon-SP
SP SoCs (Granite Rapids SP and Sierra Forest SP).
This patch initially sets the code set up as a compilation target with
GNR N-1 FSP, and with basic feature supports (Integrated IO Controller
(IIO) configuration, BMC, UART, HPET).
Change-Id: I3f6a0fb97b62baadb438fb9f11fdd78fccb3f89a
Signed-off-by: Shuo Liu <shuo.liu(a)intel.com>
Signed-off-by: Gang Chen <gang.c.chen(a)intel.com>
---
A configs/builder/config.intel.crb.bnc
A src/mainboard/intel/beechnutcity_crb/Kconfig
A src/mainboard/intel/beechnutcity_crb/Kconfig.name
A src/mainboard/intel/beechnutcity_crb/Makefile.mk
A src/mainboard/intel/beechnutcity_crb/board.fmd
A src/mainboard/intel/beechnutcity_crb/board_info.txt
A src/mainboard/intel/beechnutcity_crb/bootblock.c
A src/mainboard/intel/beechnutcity_crb/devicetree.cb
A src/mainboard/intel/beechnutcity_crb/dsdt.asl
A src/mainboard/intel/beechnutcity_crb/include/config/iio.h
A src/mainboard/intel/beechnutcity_crb/ramstage.c
A src/mainboard/intel/beechnutcity_crb/romstage.c
12 files changed, 288 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/81322/9
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Change subject: device/device_util: Rename dev_get_pci_domain
......................................................................
device/device_util: Rename dev_get_pci_domain
In coreboot, domain indicates hardware units that provide/group
resource windows, For Xeon-SP, domains are PCIe compatible and
further function in many aspects, e.g. PCIe, CXL, IOAT, UBOX.
Rename dev_get_pci_domain to dev_get_domain to align with coreboot
concept and distinguish from Xeon-SP concept.
Change-Id: I51b18b30fb41038869ea1384b01091da31a895b9
Signed-off-by: Shuo Liu <shuo.liu(a)intel.com>
---
M src/device/device_util.c
M src/drivers/pc80/tpm/tis.c
M src/include/device/device.h
M src/soc/intel/xeon_sp/chip_common.c
M src/soc/intel/xeon_sp/include/soc/chip_common.h
M src/soc/intel/xeon_sp/uncore_acpi.c
6 files changed, 15 insertions(+), 15 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/81554/5
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Change subject: device/device_util: Use const qualifier
......................................................................
device/device_util: Use const qualifier
Allows to use the function in more places that expect the
struct device to be readonly.
Change-Id: Iac04fe6931a43070f6638b399adbff2ce64829c9
Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
Signed-off-by: Shuo Liu <shuo.liu(a)intel.com>
---
M src/device/device_util.c
M src/include/device/device.h
M src/soc/intel/xeon_sp/chip_common.c
M src/soc/intel/xeon_sp/include/soc/chip_common.h
M src/soc/intel/xeon_sp/uncore_acpi.c
5 files changed, 22 insertions(+), 20 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/81275/17
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Change subject: mb/intel/avenuecity_crb: Add 2S GNR/SRF-AP server board Avenue City
......................................................................
mb/intel/avenuecity_crb: Add 2S GNR/SRF-AP server board Avenue City
Avenue City CRB is the 2 socket reference board for 6th Gen Xeon-SP
AP SoCs (Granite Rapids AP and Sierra Forest AP).
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Change-Id: I64fdd5388aadf7732f6d3daa600c1455d3672a46
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Signed-off-by: Jincheng Li <jincheng.li(a)intel.com>
---
A configs/builder/config.intel.crb.avc
A src/mainboard/intel/avenuecity_crb/Kconfig
A src/mainboard/intel/avenuecity_crb/Kconfig.name
A src/mainboard/intel/avenuecity_crb/Makefile.mk
A src/mainboard/intel/avenuecity_crb/board.fmd
A src/mainboard/intel/avenuecity_crb/board_info.txt
A src/mainboard/intel/avenuecity_crb/bootblock.c
A src/mainboard/intel/avenuecity_crb/devicetree.cb
A src/mainboard/intel/avenuecity_crb/dsdt.asl
A src/mainboard/intel/avenuecity_crb/include/config/iio.h
A src/mainboard/intel/avenuecity_crb/ramstage.c
A src/mainboard/intel/avenuecity_crb/romstage.c
12 files changed, 291 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/81319/28
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Change subject: intel/common/pch: Add Kconfig SOC_INTEL_COMMON_IBL_BASE
......................................................................
intel/common/pch: Add Kconfig SOC_INTEL_COMMON_IBL_BASE
IBL (Integrated Boot Logic) provides a subset of server
PCH logics for no-PCH solution. IBL is with limited features
and registers exposed, PCIe root ports/USB/SATA/LAN support are
removed.
Change-Id: I8f3d64a2dd3b79ec5a9e4306f40b012b00387259
Signed-off-by: Shuo Liu <shuo.liu(a)intel.com>
---
M src/soc/intel/common/pch/Kconfig
M src/soc/intel/common/pch/Makefile.mk
M src/soc/intel/xeon_sp/Kconfig
3 files changed, 44 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/81314/25
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Change subject: soc/intel/xeon_sp: Redefine data types for 6th Gen adoption
......................................................................
soc/intel/xeon_sp: Redefine data types for 6th Gen adoption
GraniteRapids (6th Gen Xeon-SP) FSP introduces UDS_STACK_RES/
UDS_SOCKET_RES and retires the usages of STACK_RES/
IIO_RESOURCE_INSTANCE. Make redinitions to make Xeon-SP common
codes to work for both 6th Gen before and later.
Change-Id: I28c948525cd6d7ac4b9c3fa67e3c99ec637ed38f
Signed-off-by: Shuo Liu <shuo.liu(a)intel.com>
---
M src/soc/intel/xeon_sp/chip_common.c
M src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h
M src/soc/intel/xeon_sp/include/soc/chip_common.h
M src/soc/intel/xeon_sp/include/soc/util.h
M src/soc/intel/xeon_sp/skx/include/soc/soc_util.h
M src/soc/intel/xeon_sp/spr/include/soc/soc_util.h
6 files changed, 23 insertions(+), 13 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/81040/26
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Change subject: soc/intel/xeon_sp: Unshare Xeon-SP chip common codes
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Patch Set 26:
(1 comment)
File src/soc/intel/xeon_sp/chip_gen1.c:
https://review.coreboot.org/c/coreboot/+/81312/comment/0feb33cb_1f0ad19f :
PS16, Line 192: #if CONFIG(SOC_INTEL_HAS_CXL)
> There are plenty of options, you could also do this: […]
Sure, I move the create_cxl_domains declaration into chip_gen1.c. Updated.
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Change subject: mb/google/nissa/var/glassway: Add 2nd Synaptics touchpad
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Patch Set 4: Code-Review+1
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/81552/comment/fc47bcd9_eedfa735 :
PS2, Line 9: Add Synaptics touchpad for glassway.
> I’d mention the interface and bus.
Done
https://review.coreboot.org/c/coreboot/+/81552/comment/f7388e89_9a2109fa :
PS2, Line 13: TEST=emerge-brya coreboot and check touchpad function work.
> Please list the test you run. […]
Done
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