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Change subject: mb/google/brya/var/bujia: Add VBT data files for bujia
......................................................................
Patch Set 5:
(1 comment)
File src/mainboard/google/brya/Kconfig:
https://review.coreboot.org/c/coreboot/+/81553/comment/1d26f99d_767f7811 :
PS2, Line 170: select INTEL_GMA_HAVE_VBT
> please pay attention towards order ?
Done
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Change subject: mb/google/brya/var/bujia: Add VBT data files for bujia
......................................................................
mb/google/brya/var/bujia: Add VBT data files for bujia
Add data.vbt files for bujia supported by brask recovery images.
Select INTEL_GMA_HAVE_VBT for bujia which currently have a VBT file.
BUG=b:327549688
TEST=build/boot various brya variants
Change-Id: Id56461708250eaedd288ddbf788d686153df0b96
Signed-off-by: Shon Wang <shon.wang(a)quanta.corp-partner.google.com>
---
M src/mainboard/google/brya/Kconfig
A src/mainboard/google/brya/variants/bujia/data.vbt
2 files changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/81553/5
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I'd like you to reexamine a change. Please visit
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Change subject: mb/google/brya/var/bujia: Add VBT data files for bujia
......................................................................
mb/google/brya/var/bujia: Add VBT data files for bujia
Add data.vbt files for bujia supported by brask recovery images.
Select INTEL_GMA_HAVE_VBT for bujia which currently have a VBT file.
BUG=b:327549688
TEST=build/boot various brya variants
Change-Id: Id56461708250eaedd288ddbf788d686153df0b96
Signed-off-by: Shon Wang <shon.wang(a)quanta.corp-partner.google.com>
---
M src/mainboard/google/brya/Kconfig
A src/mainboard/google/brya/variants/bujia/data.vbt
2 files changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/81553/3
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Change subject: mb/google/{brya,hades}: use soc index for variant_update_power_limits()
......................................................................
Patch Set 9: Code-Review+2
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Change subject: soc/intel/xeon_sp: Add Granite Rapids initial codes
......................................................................
soc/intel/xeon_sp: Add Granite Rapids initial codes
coreboot GNR (Granite Rapids) is a FSP 2.4 based, no-PCH, single
IO-APIC Xeon-SP platform. The same set of codes is also used
for SRF (Sierra Forest) SoC.
This patch initially sets the code set up.
1. All register definitions are forked from SPR (Sapphire Rapids)
and EBG (Emmisburg PCH)'s codes are reused.
2. src/soc/intel/xeon_sp/chip_gen6.c is newly added as chip
common codes for 6th Gen Xeon-SP SoC (Granite Rapids) and later.
Change-Id: I3084e1b5abf25d8d9504bebeaed2a15b916ed56b
Signed-off-by: Shuo Liu <shuo.liu(a)intel.com>
Signed-off-by: Gang Chen <gang.c.chen(a)intel.com>
Signed-off-by: Jincheng Li <jincheng.li(a)intel.com>
---
M MAINTAINERS
M src/soc/intel/xeon_sp/Makefile.mk
M src/soc/intel/xeon_sp/acpi.c
M src/soc/intel/xeon_sp/chip_gen1.c
A src/soc/intel/xeon_sp/chip_gen6.c
A src/soc/intel/xeon_sp/gnr/Kconfig
A src/soc/intel/xeon_sp/gnr/Makefile.inc
A src/soc/intel/xeon_sp/gnr/acpi/gpe.asl
A src/soc/intel/xeon_sp/gnr/acpi/platform.asl
A src/soc/intel/xeon_sp/gnr/chip.c
A src/soc/intel/xeon_sp/gnr/chip.h
A src/soc/intel/xeon_sp/gnr/cpu.c
A src/soc/intel/xeon_sp/gnr/include/soc/cpu.h
A src/soc/intel/xeon_sp/gnr/include/soc/pci_devs.h
A src/soc/intel/xeon_sp/gnr/include/soc/soc_msr.h
A src/soc/intel/xeon_sp/gnr/include/soc/soc_util.h
A src/soc/intel/xeon_sp/gnr/include/soc/vpd.h
A src/soc/intel/xeon_sp/gnr/ramstage.c
A src/soc/intel/xeon_sp/gnr/romstage.c
A src/soc/intel/xeon_sp/gnr/soc_acpi.c
A src/soc/intel/xeon_sp/gnr/soc_util.c
M src/soc/intel/xeon_sp/include/soc/chip_common.h
M src/soc/intel/xeon_sp/include/soc/fsp_upd.h
M src/soc/intel/xeon_sp/lockdown.c
M src/soc/intel/xeon_sp/uncore.c
25 files changed, 1,328 insertions(+), 62 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/81316/31
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Change subject: mb/google/{brya,hades}: use soc index for variant_update_power_limits()
......................................................................
Patch Set 9:
(1 comment)
File src/mainboard/google/brya/variants/baseboard/brya/ramstage.c:
https://review.coreboot.org/c/coreboot/+/81436/comment/f7451223_053fb46d :
PS8, Line 69:
> oh one tab miss. Do we have style check tool in coreboot? auto correct the format.
Done
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Change subject: mb/google/{brya,hades}: use soc index for variant_update_power_limits()
......................................................................
Patch Set 8: -Code-Review
(1 comment)
File src/mainboard/google/brya/variants/baseboard/brya/ramstage.c:
https://review.coreboot.org/c/coreboot/+/81436/comment/44e157c3_5912b08d :
PS8, Line 69:
> https://review.coreboot. […]
oh one tab miss. Do we have style check tool in coreboot? auto correct the format.
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Change subject: mb/google/{brya,hades}: use soc index for variant_update_power_limits()
......................................................................
Patch Set 8: Code-Review+2
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