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Change subject: mb/google/brya/var/xol: Update GPIO settings for speaker and DMIC
......................................................................
Patch Set 3: Code-Review+1
(1 comment)
Patchset:
PS3:
Let's merge this CL.
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Change subject: mb/google/brya/var/xol: Update GPIO settings for speaker and DMIC
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Change subject: mb/google/brya/var/bujia: Add VBT data files for bujia
......................................................................
mb/google/brya/var/bujia: Add VBT data files for bujia
Add data.vbt files for gladios supported by brask recovery images.
Select INTEL_GMA_HAVE_VBT for bujia which currently have a VBT file.
BUG=b:327549688
TEST=build/boot various brya variants
Change-Id: Id56461708250eaedd288ddbf788d686153df0b96
Signed-off-by: Shon Wang <shon.wang(a)quanta.corp-partner.google.com>
---
M src/mainboard/google/brya/Kconfig
A src/mainboard/google/brya/variants/bujia/data.vbt
2 files changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/81553/2
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Change subject: soc/intel/xeon_sp: Unshare Xeon-SP chip common codes
......................................................................
soc/intel/xeon_sp: Unshare Xeon-SP chip common codes
GraniteRapids (6th Gen Xeon-SP) FSP contains changes in IIO stack
descriptors impacting the way of coreboot's creation of domains.
Separates the codes as preparation for 6th Gen and later platforms.
Change-Id: Iab6acaa5e5c090c8d821bd7c2d3e0e0ad7486bdc
Signed-off-by: Shuo Liu <shuo.liu(a)intel.com>
---
M src/soc/intel/xeon_sp/chip_common.c
A src/soc/intel/xeon_sp/chip_gen1.c
M src/soc/intel/xeon_sp/cpx/Makefile.mk
M src/soc/intel/xeon_sp/include/soc/chip_common.h
M src/soc/intel/xeon_sp/skx/Makefile.mk
M src/soc/intel/xeon_sp/spr/Makefile.mk
M src/soc/intel/xeon_sp/spr/ioat.c
7 files changed, 221 insertions(+), 194 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/81312/26
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Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80609?usp=email )
Change subject: mb/lenovo: Add ThinkCentre M920q (Cannon Lake)
......................................................................
Patch Set 6:
(2 comments)
File src/mainboard/lenovo/m920q/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/80609/comment/bb082514_eb22109b :
PS4, Line 9: # PL2 override 65W
> Seems superfluous.
Done
https://review.coreboot.org/c/coreboot/+/80609/comment/70673204_970adb78 :
PS4, Line 16: device ref system_agent on end
> Remove, enabled by default.
Done
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Change subject: mb/lenovo: Add ThinkCentre M920q (Cannon Lake)
......................................................................
Patch Set 6:
(10 comments)
File src/mainboard/lenovo/m920q/Kconfig:
https://review.coreboot.org/c/coreboot/+/80609/comment/b747e165_e2e9c0ac :
PS4, Line 30: hex
> Avoid type redefinitions, remove.
Done
https://review.coreboot.org/c/coreboot/+/80609/comment/263d4f8b_ce675667 :
PS4, Line 33: config DIMM_SPD_SIZE
: default 512 #DDR4
> Remove, that's the default for Cannon Lake based SoCs.
Done
File src/mainboard/lenovo/m920q/acpi/ec.asl:
PS4:
> ``` […]
Done
File src/mainboard/lenovo/m920q/acpi/mainboard.asl:
PS4:
> ``` […]
Done
File src/mainboard/lenovo/m920q/board.fmd:
PS4:
> Is that really needed? What's different from the one that is generated during the build process?
Done
File src/mainboard/lenovo/m920q/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/80609/comment/5a0cd3a3_657d6660 :
PS4, Line 52: # SATA
> Remove superfluous comment.
Done
https://review.coreboot.org/c/coreboot/+/80609/comment/f2457cf7_ad7d21fe :
PS4, Line 56: [1] = 0,
: [2] = 0,
: [3] = 0,
: [4] = 0,
: [5] = 0,
: [6] = 0,
: [7] = 0,
> Remove, they are disabled. […]
Done
https://review.coreboot.org/c/coreboot/+/80609/comment/687eac3f_4db3c6bc :
PS4, Line 117: # eSPI controller
> Remove superfluous comment.
Done
https://review.coreboot.org/c/coreboot/+/80609/comment/0a2de6e8_c337175b :
PS4, Line 118: device ref p2sb on end
:
> Remove, they are hidden by the FSP and marked as hidden in chipset devicetree.
Done
https://review.coreboot.org/c/coreboot/+/80609/comment/c3a21e63_67f0f54c :
PS4, Line 121: register "PchHdaDspEnable" = "0"
> Remove, set to 0.
Done
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Change subject: soc/intel/xeon_sp: Unshare Xeon-SP chip common codes
......................................................................
soc/intel/xeon_sp: Unshare Xeon-SP chip common codes
GraniteRapids (6th Gen Xeon-SP) FSP contains changes in IIO stack
descriptors impacting the way of coreboot's creation of domains.
Separates the codes as preparation for 6th Gen and later platforms.
Change-Id: Iab6acaa5e5c090c8d821bd7c2d3e0e0ad7486bdc
Signed-off-by: Shuo Liu <shuo.liu(a)intel.com>
---
M src/soc/intel/xeon_sp/chip_common.c
A src/soc/intel/xeon_sp/chip_gen1.c
M src/soc/intel/xeon_sp/cpx/Makefile.mk
M src/soc/intel/xeon_sp/include/soc/chip_common.h
M src/soc/intel/xeon_sp/skx/Makefile.mk
M src/soc/intel/xeon_sp/spr/Makefile.mk
M src/soc/intel/xeon_sp/spr/ioat.c
7 files changed, 221 insertions(+), 194 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/81312/25
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