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Change subject: Support for creating hybrid vboot images
......................................................................
Patch Set 5:
(1 comment)
Patchset:
PS5:
> Okay, so you want to dual-boot, and you want ChromeOS to keep updating at the same time? That is ind […]
I disagree about lack of value of using updates. Even though this config is not fully supported it will share most of security vulnerabilities and relevant fixes with normal ChromeOS firmware. I don't believe that possibility of skipping firmware update will be better than having "dual-coreboot" setup but could be useful for someone else. I think part of the problem is because bootblock has increased its scope beyond a simple switch, otherwise it would be way simpler. I see following places to do dual-boot:
1) Boot Block, 16-bit part. Would mean having 2 bootblocks
2) Boot Block, before CAR. Again, 2 bootblocks
3) Boot Block, right after CAR init. 2 bb as well
4) Between bootblock and romstage. This is what this patch proposes. Exact placement of the code is subject to the debate
5) A special payload which loads either depth charge from RW or alternative payload from RO
6) bootloader (payload or otherwise) loading ChromeOS kernel from disk
Options 1-3 require patching inside existing bootblock or a way to relocate it. Both are feasible but feels ugly
Option 6 requires a whole other bootloader to understand ChromeOS layout. I actually planned to do it at some point in GRUB. I believe it's a good option for ChromeOS Flex but it adds a heavy amount of security-relevant code outside of ChromeOS review
This leaves options 4 and 5. I heavily prefer 4 for its better compatibility and security with ChromeOS as it makes minimum modifications in ChromeOS boot path
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The change is no longer submittable: All-Comments-Resolved is unsatisfied now.
Change subject: mb/google/nissa/var/glassway: Add 2nd Synaptics touchpad
......................................................................
Patch Set 2:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/81552/comment/0a5903ba_c1fa9766 :
PS2, Line 9: Add Synaptics touchpad for glassway.
I’d mention the interface and bus.
https://review.coreboot.org/c/coreboot/+/81552/comment/ef90afa2_16fb6901 :
PS2, Line 13: TEST=emerge-brya coreboot and check touchpad function work.
Please list the test you run. `libinput`? Look at Linux messages?
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Change subject: mb/intel/avenuecity_crb: Add Avenue City CRB
......................................................................
Patch Set 27:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/81319/comment/3ddc60c9_1a219c9d :
PS27, Line 7: Add Avenue City CRB
:
Please add the socket number and “chipset name abbreviation“ into the summary.
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Change subject: mb/intel/avenuecity_crb: Add Beechnut City CRB
......................................................................
Patch Set 8:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/81322/comment/d6735c12_93b00f99 :
PS5, Line 7: Add Beechnut City CRB initial support
> Done
Please follow the “template”.
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Change subject: arch/x86: Remove blank lines before '}' and after '{'
......................................................................
Patch Set 1: Code-Review+1
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Change subject: drivers/intel/fsp2_0: Support FSP-T in long mode
......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS4:
I am not submitting as the relation chain indicates some potential dependencies on the previous patches.
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Change subject: drivers/intel/fsp2_0: Support FSP-T in long mode
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Patch Set 4: Code-Review+2
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Hello Andrey Petrov, Arthur Heymans, Bora Guvendik, Chen, Gang C, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Paul Menzel, Ronak Kanabar, Shuo Liu, Subrata Banik, Tarun, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/81212?usp=email
to look at the new patch set (#10).
The following approvals got outdated and were removed:
Verified-1 by build bot (Jenkins)
Change subject: drivers/intel/fsp2_0: Support FSP-M execution from CBFS cache
......................................................................
drivers/intel/fsp2_0: Support FSP-M execution from CBFS cache
If SPINOR space is limited and Cache-As-RAM (CAR) is large enough, FSP
can be stored compressed, loaded in CBFS cache and executed from
there. It allows to reduce the FSP-M SPINOR footprint with a limited
boot time penalty. `FSP_M_EXECUTE_FROM_CBFS_CACHE' Kconfig can be set
to turn on this feature.
We performed some measurements on a Meteor Lake Rex board with a 2 MB
Cache-As-RAM (`DCACHE_RAM_SIZE' at 0x200000 and `DCACHE_RAM_BASE'
0xea000000) and a few adjustments in the FSP to enable CAR to RAM
PEIM (Pre-EFI Initialization Module) drivers migration.
1. Time impact
| Compression algorithm | LZ4 | LZMA |
|--------------------------+----------+----------|
| Decompress duration | 1.9 ms | 75.6 ms |
| Overall boot time impact | +15.9 ms | +77.4 ms |
The overall boot time impact increase is explained by FSP-M loading
being a bit faster (-18 ms) undermined by a longer Cache-As-RAM
setup (32 ms).
2. SPINOR impact
| CBFS file / Compression | LZ4 | LZMA |
|----------------------------+----------------+-----------------|
| romstage size | +4 KB (+3%) | +10 KB (+8%) |
| fspm.bin size | -313 KB (-37%) | -456 KB (-54%) |
|----------------------------+----------------+-----------------|
| Total Per slot | -309 KB | -446 KB |
| Total for SPINOR (3 slots) | -926 KB | -1339 KB |
BUG=b:329237541
TEST=Verified on rex with Cache-AS-RAM size of 2 MB
Change-Id: I8d42d765eb0ecf2e7a8fc6d8d15eb2df8975f6f2
Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com>
---
M src/drivers/intel/fsp2_0/Kconfig
M src/drivers/intel/fsp2_0/Makefile.mk
M src/drivers/intel/fsp2_0/memory_init.c
M src/soc/intel/meteorlake/Kconfig
4 files changed, 40 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/81212/10
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Change subject: drivers/intel/fsp2_0: Support FSP-M execution from CBFS cache
......................................................................
Patch Set 9:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/81212/comment/b54464bd_399eb56c :
PS6, Line 42: 2 MB
> I think this is a step in the right direction. Both AMD FSP code and Intel APL/GLK code uses a static addr for FSP-M. They should be moved to this solution if possible?
I do think this is good idea. However I do not have access to any of those board currently and I am going to be out for about 2 month (April 1st - June 14th) so it will have to wait. But this is not urgent.
File src/drivers/intel/fsp2_0/Kconfig:
https://review.coreboot.org/c/coreboot/+/81212/comment/2bbf9669_fef39c80 :
PS3, Line 221: FSP_EXECUTE_FROM_CBFS_CACHE
> > Having an assertion can avoid the device to run into the actual issue but I don't see an option a […]
Done
File src/drivers/intel/fsp2_0/Kconfig:
https://review.coreboot.org/c/coreboot/+/81212/comment/57533ef0_5af787bc :
PS8, Line 229: It requires the PRERAM_CBFS_CACHE_SIZE to be large enough to
: accommodate the entire FSP-M binary and therefore the SoC to
: support a large enough Cache-As-RAM (DCACHE_RAM_SIZE).
:
> The commit message says something about needing adjustments for this to work. […]
Done
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