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Change subject: cpu/x86/topology: Add node ID parser
......................................................................
Patch Set 5:
(1 comment)
File src/cpu/x86/topology.c:
https://review.coreboot.org/c/coreboot/+/81515/comment/da2105c3_5425efb8 :
PS5, Line 158: package_id = apicid >> (thread_bits + core_bits);
> I haven't use it before. […]
In src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c:mp_get_processor_info
processor_info_buffer->Location.Package = dev->path.apic.package_id;
Here, the path.apic.package_id is used as the physical package_id
While, for path.apic.node_id, before this patch, there is no usage as of now.
Maybe it is not late to clarify their usage at the moment.
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Change subject: cpu/x86/topology: Add node ID parser
......................................................................
Patch Set 5:
(1 comment)
File src/cpu/x86/topology.c:
https://review.coreboot.org/c/coreboot/+/81515/comment/dcbfdc1e_006233d4 :
PS5, Line 158: package_id = apicid >> (thread_bits + core_bits);
> Can the SOCKET_ID MSR be used instead of CPUID lead 0x1f?
I haven't use it before. MSR is usually model-specific and maybe it would be not so suitable to be used in generic codes.
But it would be helpful if we could have clear definition what node_id means to different archs (even we define node_id as the physical package id, there is another field named package_id as discussed is confusing).
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Hello Martin L Roth, Maximilian Brune, Philipp Hug, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: Update opensbi submodule to upstream master branch
......................................................................
Update opensbi submodule to upstream master branch
Updating from commit id 5019fd124b4c (2022-09-01):
include: sbi: Reduce includes in sbi_pmu.h
to commit id 5186da687deb (2024-03-20):
platform: generic: allwinner: sun20i-d1: Remove duplicated CSR definitions
This brings in 465 new commits.
Tested on the SiFive unmatched.
Because the coreboot opensbi shim uses include files from opensbi,
it was necessary to do this:
#undef __always_inline
because coreboot also defines __always_inline in
src/commonlib/bsd/include/commonlib/bsd/compiler.h
and opensbi does not have a guard around their definition.
Change-Id: I50ce0ba3b6409247a94b49565cc04454903e88d0
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---
M 3rdparty/opensbi
M src/arch/riscv/opensbi.c
M src/soc/sifive/fu540/memlayout.ld
M src/soc/sifive/fu740/memlayout.ld
4 files changed, 9 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/81543/3
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Change subject: Kconfig: Make GBD_STUB and long mode mutually exclusive
......................................................................
Patch Set 8:
(1 comment)
File src/Kconfig:
https://review.coreboot.org/c/coreboot/+/81379/comment/13be3506_966110cf :
PS7, Line 1019: #
> that comment won't cut it :-p
Done
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Change subject: soc/amd/noncar: Use romstage MEM in bootblock if !SEPARATE_ROMSTAGE
......................................................................
Patch Set 34:
(1 comment)
File src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld:
https://review.coreboot.org/c/coreboot/+/64950/comment/b24e8ec3_f83282bf :
PS27, Line 102: BOOTBLOCK(CONFIG_ROMSTAGE_ADDR, CONFIG_ROMSTAGE_SIZE)
> > > hmm, this ends up doing the right thing, but i found it confusing when looking at it at first. maybe a comment would help? would also be good if that was somehow integrated into the diagram above to have that cover both cases. might also be good to add a comment to the ROMSTAGE_SIZE Kconfig that this will be used as bootblock size in the combined bootblock and romstage case.
> > >
> > > a probably better option might be to have different C_ENV_BOOTBLOCK_SIZE sizes dependent on whether SEPARATE_ROMSTAGE is selected in the Kconfig and make ROMSTAGE_SIZE 0 in the !SEPARATE_ROMSTAGE case. not sure if we'd need to put the ROMSATGE macro in here in a #if CONFIG(SEPARATE_ROMSTAGE) block. the calculation of BOOTBLOCK_END and BOOTBLOCK_ADDR would also need to be reworked for that
> >
> > Currently the base of bootblock gets computed from ROMSTAGE_BASE. If one just increase C_ENV_BOOTBLOCK_SIZE it might overextend downwards overlapping the PSP_SHAREDMEM_SIZE. It does reduce the amount of the amount of DRAM used as ROMSTAGE has an arbitrarily large value which you could tune if using C_ENV_BOOTBLOCK_SIZE. A better way would be to set BOOTBLOCK_BASE in Kconfig and compute romstage base based on that.
>
> A computed bootblock and romstage base/size separatly to make it more clear. Maybe a follow-up can tune sizes better but this should basically work?
I added a comment clarifying the computation. That should do for now?
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Change subject: soc/amd/noncar: Use romstage MEM in bootblock if !SEPARATE_ROMSTAGE
......................................................................
soc/amd/noncar: Use romstage MEM in bootblock if !SEPARATE_ROMSTAGE
Use the memory that would be used by the romstage in the bootblock in
case that there is no separate romstage.
Change-Id: I7bd5affdb7f40cbd3bd4e599c3a5cb79984fea68
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld
1 file changed, 12 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/64950/35
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Change subject: drivers/intel/fsp2_0: Support FSP-T in long mode
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Patch Set 4: Code-Review+2
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Change subject: mb/{bd/bd_egs, iventec/transformers}: Fix building with x86_64
......................................................................
mb/{bd/bd_egs, iventec/transformers}: Fix building with x86_64
This fixes a warning about casting an integer to a pointer, where the
integer has a different size than the pointer (UINT32).
Change-Id: Iceb7cb1dbdc6f5397823a1737e3baeac96966a78
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/mainboard/bytedance/bd_egs/romstage.c
M src/mainboard/inventec/transformers/romstage.c
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git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/81559/3
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Change subject: mb/[bd/bd_egs, iventec/transformers}: Fix building with x86_64
......................................................................
Patch Set 1:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/81559/comment/466107ad_456380fb :
PS1, Line 7: [
> {
Done
https://review.coreboot.org/c/coreboot/+/81559/comment/d477b4ed_5210da32 :
PS1, Line 8:
> It’d be great if you listed the errors, or the problems.
Done
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