coreboot-gerrit March 2024

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[XS] Change in coreboot[main]: mb/[bd/bd_egs, iventec/transformers}: Fix building with x86_64
by Arthur Heymans (Code Review) 28 Mar '24

28 Mar '24

Attention is currently required from: Arthur Heymans. Arthur Heymans has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/81559?usp=email ) Change subject: mb/[bd/bd_egs, iventec/transformers}: Fix building with x86_64 ...................................................................... mb/[bd/bd_egs, iventec/transformers}: Fix building with x86_64 This fixes a warning about casting an integer to a pointer, where the integer has a different size than the pointer (UINT32). Change-Id: Iceb7cb1dbdc6f5397823a1737e3baeac96966a78 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/bytedance/bd_egs/romstage.c M src/mainboard/inventec/transformers/romstage.c 2 files changed, 4 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/81559/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81559?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iceb7cb1dbdc6f5397823a1737e3baeac96966a78 Gerrit-Change-Number: 81559 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: Update opensbi submodule to upstream master branch
by Martin L Roth (Code Review) 28 Mar '24

28 Mar '24

Attention is currently required from: Maximilian Brune, Philipp Hug, ron minnich. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81543?usp=email ) Change subject: Update opensbi submodule to upstream master branch ...................................................................... Patch Set 2: Code-Review+2 (1 comment) Patchset: PS2: mention the coreboot code changes in the commit message? -- To view, visit https://review.coreboot.org/c/coreboot/+/81543?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I50ce0ba3b6409247a94b49565cc04454903e88d0 Gerrit-Change-Number: 81543 Gerrit-PatchSet: 2 Gerrit-Owner: ron minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Thu, 28 Mar 2024 13:59:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/[bd/bd_egs, iventec/transformers}: Fix building with x86_64
by Paul Menzel (Code Review) 28 Mar '24

28 Mar '24

Attention is currently required from: Arthur Heymans. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81559?usp=email ) Change subject: mb/[bd/bd_egs, iventec/transformers}: Fix building with x86_64 ...................................................................... Patch Set 1: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/81559/comment/bb84bc65_8c65040f : PS1, Line 7: [ { https://review.coreboot.org/c/coreboot/+/81559/comment/fb13e594_76408c4b : PS1, Line 8: It’d be great if you listed the errors, or the problems. -- To view, visit https://review.coreboot.org/c/coreboot/+/81559?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iceb7cb1dbdc6f5397823a1737e3baeac96966a78 Gerrit-Change-Number: 81559 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Thu, 28 Mar 2024 13:56:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/[bd/bd_egs, iventec/transformers}: Fix building with x86_64
by Arthur Heymans (Code Review) 28 Mar '24

28 Mar '24

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81559?usp=email ) Change subject: mb/[bd/bd_egs, iventec/transformers}: Fix building with x86_64 ...................................................................... mb/[bd/bd_egs, iventec/transformers}: Fix building with x86_64 Change-Id: Iceb7cb1dbdc6f5397823a1737e3baeac96966a78 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/bytedance/bd_egs/romstage.c M src/mainboard/inventec/transformers/romstage.c 2 files changed, 4 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/81559/1 diff --git a/src/mainboard/bytedance/bd_egs/romstage.c b/src/mainboard/bytedance/bd_egs/romstage.c index e010867..f33e74e 100644 --- a/src/mainboard/bytedance/bd_egs/romstage.c +++ b/src/mainboard/bytedance/bd_egs/romstage.c @@ -5,13 +5,14 @@ #include <defs_cxl.h> #include <defs_iio.h> #include <sprsp_bd_iio.h> +#include <stdint.h> static void mainboard_config_iio(FSPM_UPD *mupd) { int port; UPD_IIO_PCIE_PORT_CONFIG *PciePortConfig = - (UPD_IIO_PCIE_PORT_CONFIG *)mupd->FspmConfig.IioPcieConfigTablePtr; + (UPD_IIO_PCIE_PORT_CONFIG *)(uintptr_t)mupd->FspmConfig.IioPcieConfigTablePtr; /* Socket0: Array bd_iio_pci_port_skt0 only configures DMI, IOU0 ~ IOU4, the rest will be left zero */ for (port = 0; port < ARRAY_SIZE(bd_iio_pci_port_skt0); port++) { diff --git a/src/mainboard/inventec/transformers/romstage.c b/src/mainboard/inventec/transformers/romstage.c index c04720a..9299c7d 100644 --- a/src/mainboard/inventec/transformers/romstage.c +++ b/src/mainboard/inventec/transformers/romstage.c @@ -10,6 +10,7 @@ #include <defs_cxl.h> #include <defs_iio.h> #include <sprsp_ac_iio.h> +#include <stdint.h> #include "ipmi.h" @@ -24,7 +25,7 @@ int port; UPD_IIO_PCIE_PORT_CONFIG *PciePortConfig = - (UPD_IIO_PCIE_PORT_CONFIG *)mupd->FspmConfig.IioPcieConfigTablePtr; + (UPD_IIO_PCIE_PORT_CONFIG *)(uintptr_t)mupd->FspmConfig.IioPcieConfigTablePtr; /* Socket0: Array ac_iio_pci_port_skt0 only configures DMI, IOU0 ~ IOU4, the rest will be left zero */ for (port = 0; port < ARRAY_SIZE(ac_iio_pci_port_skt0); port++) { -- To view, visit https://review.coreboot.org/c/coreboot/+/81559?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iceb7cb1dbdc6f5397823a1737e3baeac96966a78 Gerrit-Change-Number: 81559 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: soc/intel/cache_as_ram_fsp.S: Drop unused preprocessor
by Arthur Heymans (Code Review) 28 Mar '24

28 Mar '24

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81558?usp=email ) Change subject: soc/intel/cache_as_ram_fsp.S: Drop unused preprocessor ...................................................................... soc/intel/cache_as_ram_fsp.S: Drop unused preprocessor Change-Id: I42bb15b8534d16401cd06ff803a8425221c5f3c1 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S 1 file changed, 0 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/81558/1 diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S index c6d2a9c..4e057f0 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S @@ -1,16 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <cpu/x86/64bit/entry64.inc> -#include <cpu/x86/cr.h> #include <cpu/x86/post_code.h> -#include <device/pci_def.h> -#include <intelblocks/post_codes.h> - -#define CBFS_FILE_MAGIC 0 -#define CBFS_FILE_LEN (CBFS_FILE_MAGIC + 8) -#define CBFS_FILE_TYPE (CBFS_FILE_LEN + 4) -#define CBFS_FILE_CHECKSUM (CBFS_FILE_TYPE + 4) -#define CBFS_FILE_OFFSET (CBFS_FILE_CHECKSUM + 4) .section .init, "ax", @progbits -- To view, visit https://review.coreboot.org/c/coreboot/+/81558?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I42bb15b8534d16401cd06ff803a8425221c5f3c1 Gerrit-Change-Number: 81558 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: drivers/intel/fsp2_0: Support FSP-T in long mode
by Arthur Heymans (Code Review) 28 Mar '24

28 Mar '24

Attention is currently required from: Andrey Petrov, Arthur Heymans, Jérémy Compostella, Patrick Rudolph, Ronak Kanabar. Arthur Heymans has uploaded a new patch set (#3) to the change originally created by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/81281?usp=email ) The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: drivers/intel/fsp2_0: Support FSP-T in long mode ...................................................................... drivers/intel/fsp2_0: Support FSP-T in long mode Call into FSP-T using the protected mode wrapper and enter long mode in FSP-T support assembly code. TEST: Booted on ibm/sbp1 in long mode. Change-Id: Id6b9780b06b4bfbb952e32091ffbf3d0014f2090 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/drivers/intel/fsp2_0/temp_ram_exit.c M src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S 2 files changed, 21 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/81281/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/81281?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id6b9780b06b4bfbb952e32091ffbf3d0014f2090 Gerrit-Change-Number: 81281 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: Kconfig: Make GBD_STUB and long mode mutually exclusive
by Arthur Heymans (Code Review) 28 Mar '24

28 Mar '24

Attention is currently required from: Arthur Heymans, Jérémy Compostella, Martin L Roth. Hello Jérémy Compostella, Martin L Roth, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81379?usp=email to look at the new patch set (#8). The following approvals got outdated and were removed: Code-Review+2 by Martin L Roth, Code-Review-1 by Arthur Heymans, Verified+1 by build bot (Jenkins) Change subject: Kconfig: Make GBD_STUB and long mode mutually exclusive ...................................................................... Kconfig: Make GBD_STUB and long mode mutually exclusive GDB debugging is not implemented with x86 long mode. Change-Id: Icaf7d0763829d5badf73d38bb8fc3d36cfe18964 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/Kconfig M src/arch/x86/c_start.S M src/arch/x86/exception.c 3 files changed, 6 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/81379/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/81379?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icaf7d0763829d5badf73d38bb8fc3d36cfe18964 Gerrit-Change-Number: 81379 Gerrit-PatchSet: 8 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: drivers/intel/fsp2_0: Support FSP-T in long mode
by Arthur Heymans (Code Review) 28 Mar '24

28 Mar '24

Attention is currently required from: Andrey Petrov, Jérémy Compostella, Patrick Rudolph, Ronak Kanabar. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81281?usp=email ) Change subject: drivers/intel/fsp2_0: Support FSP-T in long mode ...................................................................... Patch Set 2: (2 comments) File src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S: https://review.coreboot.org/c/coreboot/+/81281/comment/7932391d_3aeb36d7 : PS2, Line 7: #include <cpu/x86/64bit/entry64.inc> > Alphabetical order ? Done https://review.coreboot.org/c/coreboot/+/81281/comment/b48d9b58_90bf4d76 : PS2, Line 95: CONFIG_ARCH_X86_64_PGTBL_LOC > Make sure it is aligned with https://review.coreboot. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/81281?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id6b9780b06b4bfbb952e32091ffbf3d0014f2090 Gerrit-Change-Number: 81281 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Comment-Date: Thu, 28 Mar 2024 13:44:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-MessageType: comment

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[L] Change in coreboot[main]: soc/intel/xeon_sp: Unshare Xeon-SP chip common codes
by Shuo Liu (Code Review) 28 Mar '24

28 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, David Hendricks, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Martin L Roth, Nico Huber, Patrick Rudolph, Paul Menzel, TangYiwei, Tim Chu. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81312?usp=email ) Change subject: soc/intel/xeon_sp: Unshare Xeon-SP chip common codes ...................................................................... Patch Set 23: (1 comment) File src/soc/intel/xeon_sp/chip_gen1.c: https://review.coreboot.org/c/coreboot/+/81312/comment/ca688017_86f2facb : PS16, Line 192: #if CONFIG(SOC_INTEL_HAS_CXL) > I tried this change and it works, but for me seems a bit confusing, since create_cxl_domains is rega […] Updated. I keep the create_cxl_domain as non-static, thus it could cover all cases. -- To view, visit https://review.coreboot.org/c/coreboot/+/81312?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iab6acaa5e5c090c8d821bd7c2d3e0e0ad7486bdc Gerrit-Change-Number: 81312 Gerrit-PatchSet: 23 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: TangYiwei Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Thu, 28 Mar 2024 13:42:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: mb/google/brox: Enable PMC pins to work with PD
by Deepti Deshatty (Code Review) 28 Mar '24

28 Mar '24

Attention is currently required from: Ashish Kumar Mishra, Shelley Chen, Vijay P Hiremath. Deepti Deshatty has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81207?usp=email ) Change subject: mb/google/brox: Enable PMC pins to work with PD ...................................................................... Patch Set 4: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/81207?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia678d291e7a14aefe09026e70478fea3f68c8e10 Gerrit-Change-Number: 81207 Gerrit-PatchSet: 4 Gerrit-Owner: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Reviewer: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Vijay P Hiremath <vijay.p.hiremath(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <ericllai(a)google.com> Gerrit-CC: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Attention: Vijay P Hiremath <vijay.p.hiremath(a)intel.com> Gerrit-Comment-Date: Thu, 28 Mar 2024 13:41:13 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit March 2024