coreboot-gerrit March 2024

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[XS] Change in coreboot[main]: mb/google/corsola: Add new board variant 'Kyogre'
by Kei Hiroyoshi (Code Review) 28 Mar '24

28 Mar '24

Attention is currently required from: Hung-Te Lin, Kei Hiroyoshi, Kenny Pan, Knox Chiou, Paul Menzel, Yidi Lin. Hello Eric Lai, Hung-Te Lin, Varshit Pandya, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81218?usp=email to look at the new patch set (#9). Change subject: mb/google/corsola: Add new board variant 'Kyogre' ...................................................................... mb/google/corsola: Add new board variant 'Kyogre' Add a new Kingler follower device 'Kyogre' BUG=b:318614302 TEST=emerge-corsola coreboot Change-Id: Iae3857a9f8edadcc2eee3500fda2e76c0334221c Signed-off-by: Kei Hiroyoshi <hiroyoshi.kei(a)fujitsu.corp-partner.google.com> --- M src/mainboard/google/corsola/Kconfig M src/mainboard/google/corsola/Kconfig.name 2 files changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/81218/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/81218?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iae3857a9f8edadcc2eee3500fda2e76c0334221c Gerrit-Change-Number: 81218 Gerrit-PatchSet: 9 Gerrit-Owner: Kei Hiroyoshi <hiroyoshi.kei(a)fujitsu.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kenny Pan <kennypan(a)google.com> Gerrit-CC: Knox Chiou <knoxchiou(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Knox Chiou <knoxchiou(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kei Hiroyoshi <hiroyoshi.kei(a)fujitsu.corp-partner.google.com> Gerrit-Attention: Kenny Pan <kennypan(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: soc/mediatek: Remove blank lines before '}' and after '{'
by Yu-Ping Wu (Code Review) 28 Mar '24

28 Mar '24

Yu-Ping Wu has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81462?usp=email ) Change subject: soc/mediatek: Remove blank lines before '}' and after '{' ...................................................................... soc/mediatek: Remove blank lines before '}' and after '{' Change-Id: I0ce2b61329efede1ba8a02446610e3eb635ceedc Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81462 Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yidi Lin <yidilin(a)google.com> Reviewed-by: Eric Lai <ericllai(a)google.com> --- M src/soc/mediatek/common/ddp.c M src/soc/mediatek/common/display.c M src/soc/mediatek/common/dp/dptx_hal.c M src/soc/mediatek/common/i2c.c M src/soc/mediatek/common/msdc.c M src/soc/mediatek/common/uart.c M src/soc/mediatek/mt8173/da9212.c M src/soc/mediatek/mt8173/dramc_pi_basic_api.c M src/soc/mediatek/mt8173/dramc_pi_calibration_api.c M src/soc/mediatek/mt8173/mt6391.c M src/soc/mediatek/mt8183/dramc_pi_basic_api.c M src/soc/mediatek/mt8183/emi.c M src/soc/mediatek/mt8186/devapc.c M src/soc/mediatek/mt8188/devapc.c M src/soc/mediatek/mt8188/include/soc/gpio.h M src/soc/mediatek/mt8192/devapc.c M src/soc/mediatek/mt8195/include/soc/gpio.h M src/soc/mediatek/mt8195/spm.c 18 files changed, 0 insertions(+), 31 deletions(-) Approvals: Eric Lai: Looks good to me, approved Yu-Ping Wu: Looks good to me, approved Yidi Lin: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/mediatek/common/ddp.c b/src/soc/mediatek/common/ddp.c index 67e2fbf..7e2d373 100644 --- a/src/soc/mediatek/common/ddp.c +++ b/src/soc/mediatek/common/ddp.c @@ -46,7 +46,6 @@ void color_start(u32 width, u32 height) { - write32(&disp_color0->width, width); write32(&disp_color0->height, height); write32(&disp_color0->cfg_main, COLOR_BYPASS_ALL | COLOR_SEQ_SEL); diff --git a/src/soc/mediatek/common/display.c b/src/soc/mediatek/common/display.c index a5b0e6b..0dea58c 100644 --- a/src/soc/mediatek/common/display.c +++ b/src/soc/mediatek/common/display.c @@ -81,7 +81,6 @@ return -1; } } else { - struct panel_serializable_data *mipi_data = NULL; if (panel->get_edid) { diff --git a/src/soc/mediatek/common/dp/dptx_hal.c b/src/soc/mediatek/common/dp/dptx_hal.c index b246c20..c46f457 100644 --- a/src/soc/mediatek/common/dp/dptx_hal.c +++ b/src/soc/mediatek/common/dp/dptx_hal.c @@ -324,7 +324,6 @@ void dptx_hal_setsdp_downcnt_init_inhblanking(struct mtk_dp *mtk_dp, u16 value) { mtk_dp_mask(mtk_dp, REG_3364_DP_ENCODER1_P0, value, 0xfff); - } void dptx_hal_setsdp_downcnt_init(struct mtk_dp *mtk_dp, u16 value) diff --git a/src/soc/mediatek/common/i2c.c b/src/soc/mediatek/common/i2c.c index ab7b0de..886fb2a 100644 --- a/src/soc/mediatek/common/i2c.c +++ b/src/soc/mediatek/common/i2c.c @@ -472,7 +472,6 @@ base_step_cnt = step_cnt; if (best_mul == opt_div + clock_div_constraint) break; - } if (!success) diff --git a/src/soc/mediatek/common/msdc.c b/src/soc/mediatek/common/msdc.c index 0d1dbb5..e7cd571 100644 --- a/src/soc/mediatek/common/msdc.c +++ b/src/soc/mediatek/common/msdc.c @@ -388,7 +388,6 @@ msdc_set_clock(host, ctrlr->request_hz); msdc_set_buswidth(host, ctrlr->bus_width); - } static void msdc_update_pointers(struct msdc_ctrlr *host) diff --git a/src/soc/mediatek/common/uart.c b/src/soc/mediatek/common/uart.c index 79ca072..4585fc0 100644 --- a/src/soc/mediatek/common/uart.c +++ b/src/soc/mediatek/common/uart.c @@ -111,7 +111,6 @@ write8(&uart_ptr->fcr, UART8250_FCR_FIFO_EN | UART8250_FCR_CLEAR_RCVR | UART8250_FCR_CLEAR_XMIT); - } static void mtk_uart_tx_byte(unsigned char data) diff --git a/src/soc/mediatek/mt8173/da9212.c b/src/soc/mediatek/mt8173/da9212.c index 5028f18..2b118bf 100644 --- a/src/soc/mediatek/mt8173/da9212.c +++ b/src/soc/mediatek/mt8173/da9212.c @@ -47,7 +47,6 @@ if (ret) printk(BIOS_ERR, "%s failed\n", __func__); - } void da9212_probe(uint8_t i2c_num) diff --git a/src/soc/mediatek/mt8173/dramc_pi_basic_api.c b/src/soc/mediatek/mt8173/dramc_pi_basic_api.c index 10d03e0..e58ea53 100644 --- a/src/soc/mediatek/mt8173/dramc_pi_basic_api.c +++ b/src/soc/mediatek/mt8173/dramc_pi_basic_api.c @@ -154,7 +154,6 @@ static void pll_phase_adjust(u32 channel, struct mem_pll *mempll, int reg_offs) { switch (mempll->phase) { - case MEMPLL_INIT: /* initial phase: zero out RG_MEPLL(2,3,4)_(REF_DL,FB)_DL */ clrbits32(&ch[channel].ddrphy_regs->mempll[reg_offs], @@ -189,7 +188,6 @@ (idx + 2), mempll->phase, one_count, zero_count); switch (mempll->phase) { - case MEMPLL_INIT: if ((one_count - zero_count) > JMETER_COUNT_N) { /* REF lag FBK */ @@ -243,7 +241,6 @@ JMETER_COUNT << JMETER_COUNTER_SHIFT); while (1) { - for (i = 0; i < 3; i++) { if (!mempll[i].done) { pll_phase_adjust(channel, &mempll[i], (i + 2) * 3); @@ -317,7 +314,6 @@ udelay(100); for (channel = 0; channel < CHANNEL_NUM; channel++) { - /* mempll_bias_en */ write32(&ch[channel].ddrphy_regs->mempll[3], 0xd << 28 | 0x1 << 6); diff --git a/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c index fc5c58c..b9f11a0 100644 --- a/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c +++ b/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c @@ -751,7 +751,6 @@ max_taps = MAX_DQDLY_TAPS - 1; for (i = 0; i < DATA_WIDTH_32BIT; i++) { - index = i / DQS_BIT_NUMBER; if (i % DQS_BIT_NUMBER == 0) @@ -823,7 +822,6 @@ value += (curr_val << (4 * i)); switch (type) { - case TX_DQS: write32(&ch[channel].ddrphy_regs->padctl3, value); break; @@ -979,7 +977,6 @@ /* delay DQ from 0 to 15 to get the setup time */ for (dly = FIRST_DQ_DELAY; dly < MAX_DQDLY_TAPS; dly++) { - set_dly_factor(channel, STAGE_SETUP, type, dly); err_value = dram_k_perbit(channel); @@ -1015,7 +1012,6 @@ /* delay DQS to get the hold time, dq_dly = dqs_dly = 0 is counted */ /* when we delay dq, so we set first dqs delay to 1 */ for (dly = (FIRST_DQS_DELAY + 1); dly < max_dqs_taps; dly++) { - set_dly_factor(channel, STAGE_HOLD, type, dly); err_value = dram_k_perbit(channel); diff --git a/src/soc/mediatek/mt8173/mt6391.c b/src/soc/mediatek/mt8173/mt6391.c index 2186c06..f9a4629 100644 --- a/src/soc/mediatek/mt8173/mt6391.c +++ b/src/soc/mediatek/mt8173/mt6391.c @@ -78,7 +78,6 @@ pwrap_write_field(addr, vsel, 0x7, 5); pwrap_write_field(PMIC_RG_DIGLDO_CON5 + ldo * 2, 1, 1, 15); - } void mt6391_enable_reset_when_ap_resets(void) @@ -362,7 +361,6 @@ pwrap_write_field(PMIC_RG_ANALDO_CON0, 0x3, 0x3, 3); /* For low power, VIO18 set sleep_en to HW mode */ pwrap_write_field(PMIC_RG_VIO18_CON18, 0x1, 0x1, 8); - } static void mt6391_default_buck_voltage(void) diff --git a/src/soc/mediatek/mt8183/dramc_pi_basic_api.c b/src/soc/mediatek/mt8183/dramc_pi_basic_api.c index d992371..0a4039b 100644 --- a/src/soc/mediatek/mt8183/dramc_pi_basic_api.c +++ b/src/soc/mediatek/mt8183/dramc_pi_basic_api.c @@ -289,7 +289,6 @@ clrsetbits32(&ch[chn].phy.r[rank].b[b].rxdvs[2], (0x3 << 30) | (0x1 << 28) | (0x1 << 23), (0x2 << 30) | (0x1 << 28) | (0x1 << 23)); - } static void dramc_hw_dqs_gating_tracking(u8 chn) diff --git a/src/soc/mediatek/mt8183/emi.c b/src/soc/mediatek/mt8183/emi.c index 5e4f01531..8b05667 100644 --- a/src/soc/mediatek/mt8183/emi.c +++ b/src/soc/mediatek/mt8183/emi.c @@ -537,7 +537,6 @@ dst_addr = (u8 *)&ch[chn].ao.shu[dst_shuffle] + offset; write32(dst_addr, read32(src_addr)); - } } @@ -569,7 +568,6 @@ dst_addr = (u8 *)&ch[chn].phy.shu[dst_shuffle] + offset; write32(dst_addr, read32(src_addr)); - } } } diff --git a/src/soc/mediatek/mt8186/devapc.c b/src/soc/mediatek/mt8186/devapc.c index d831dcd..d32e62c 100644 --- a/src/soc/mediatek/mt8186/devapc.c +++ b/src/soc/mediatek/mt8186/devapc.c @@ -370,7 +370,6 @@ /* module, AP permission, N/A, SSPM permission, N/A */ static const struct apc_infra_peri_dom_4 mm_ao_sys0_devices[] = { - /* 0 */ DAPC_MM_AO_SYS0_ATTR("IP", NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION), diff --git a/src/soc/mediatek/mt8188/devapc.c b/src/soc/mediatek/mt8188/devapc.c index 6e47f705..6c585ba 100644 --- a/src/soc/mediatek/mt8188/devapc.c +++ b/src/soc/mediatek/mt8188/devapc.c @@ -1492,7 +1492,6 @@ for (j = 0; j < ARRAY_SIZE(infra_ao_sys2_devices[i].d_permission); j++) set_module_apc(base + SYS2_D0_APC_0, i, domain_map[j], infra_ao_sys2_devices[i].d_permission[j]); - } static void set_peri_ao_apc(uintptr_t base) @@ -1516,7 +1515,6 @@ for (j = 0; j < ARRAY_SIZE(peri_ao_sys1_devices[i].d_permission); j++) set_module_apc(base + SYS1_D0_APC_0, i, domain_map[j], peri_ao_sys1_devices[i].d_permission[j]); - } static void set_peri2_ao_apc(uintptr_t base) @@ -1527,7 +1525,6 @@ for (j = 0; j < ARRAY_SIZE(peri2_ao_sys0_devices[i].d_permission); j++) set_module_apc(base + SYS0_D0_APC_0, i, domain_map[j], peri2_ao_sys0_devices[i].d_permission[j]); - } static void set_peri_par_ao_apc(uintptr_t base) @@ -1538,7 +1535,6 @@ for (j = 0; j < ARRAY_SIZE(peri_par_ao_sys0_devices[i].d_permission); j++) set_module_apc(base + SYS0_D0_APC_0, i, domain_map[j], peri_par_ao_sys0_devices[i].d_permission[j]); - } static void dump_infra_ao_apc(uintptr_t base) @@ -1599,7 +1595,6 @@ for (i = 0; i < reg_max; i++) printk(BIOS_DEBUG, "[DEVAPC] (PERI2_AO_SYS0)D%d_APC_%d: %#x\n", d, i, read32(getreg_domain(base, SYS0_D0_APC_0, d, i))); - } static void dump_peri_par_ao_apc(uintptr_t base) @@ -1716,7 +1711,6 @@ /* Master Domain */ SET32_BITFIELDS(getreg_domain(base, MAS_DOM_0, 0, 4), PCIE0_DOM, DOMAIN_2); - } static void fmem_master_init(uintptr_t base) diff --git a/src/soc/mediatek/mt8188/include/soc/gpio.h b/src/soc/mediatek/mt8188/include/soc/gpio.h index 8767e0f..916cf84 100644 --- a/src/soc/mediatek/mt8188/include/soc/gpio.h +++ b/src/soc/mediatek/mt8188/include/soc/gpio.h @@ -44,7 +44,6 @@ }) enum { - PIN(0, GPIO00, 0, 6, 0x31, 0xe0, TP_GPIO0_AO, SPIM5_CSB, UTXD1, DMIC3_CLK, I2SIN_MCK, I2SO2_MCK, DBG_MON_A0), diff --git a/src/soc/mediatek/mt8192/devapc.c b/src/soc/mediatek/mt8192/devapc.c index 1fdc519..96bd2bd 100644 --- a/src/soc/mediatek/mt8192/devapc.c +++ b/src/soc/mediatek/mt8192/devapc.c @@ -46,7 +46,6 @@ TWO_BIT_DOM_REMAP_2, MAS_DOMAIN_1, TWO_BIT_DOM_REMAP_3, MAS_DOMAIN_3, TWO_BIT_DOM_REMAP_4, MAS_DOMAIN_1); - } static void peri_master_init(uintptr_t base) diff --git a/src/soc/mediatek/mt8195/include/soc/gpio.h b/src/soc/mediatek/mt8195/include/soc/gpio.h index 60f3af1..02c3580 100644 --- a/src/soc/mediatek/mt8195/include/soc/gpio.h +++ b/src/soc/mediatek/mt8195/include/soc/gpio.h @@ -37,7 +37,6 @@ }) enum { - PIN(0, GPIO_00, 1, 0, 0x23, 0x60, TP_GPIO0_AO, MSDC2_CMD, TDMIN_MCK, CLKM0, PERSTN_1, IDDIG_1P, DMIC4_CLK), diff --git a/src/soc/mediatek/mt8195/spm.c b/src/soc/mediatek/mt8195/spm.c index 457c019..01df38d 100644 --- a/src/soc/mediatek/mt8195/spm.c +++ b/src/soc/mediatek/mt8195/spm.c @@ -467,7 +467,6 @@ SPM_DVFSRC_ENABLE_LSB, 1); write32(&mtk_spm->spm_dvfs_level, SPM_DVFS_LEVEL_DEF); write32(&mtk_spm->spm_dvs_dfs_level, SPM_DVS_DFS_LEVEL_DEF); - } void spm_reset_and_init_pcm(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/81462?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0ce2b61329efede1ba8a02446610e3eb635ceedc Gerrit-Change-Number: 81462 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: soc/mediatek: Remove blank lines before '}' and after '{'
by Yu-Ping Wu (Code Review) 28 Mar '24

28 Mar '24

Attention is currently required from: Elyes Haouas, Felix Singer, Hung-Te Lin, Xi Chen. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81462?usp=email ) Change subject: soc/mediatek: Remove blank lines before '}' and after '{' ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81462?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0ce2b61329efede1ba8a02446610e3eb635ceedc Gerrit-Change-Number: 81462 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Thu, 28 Mar 2024 09:18:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[main]: mb/google: Remove blank lines before '}' and after '{'
by Yu-Ping Wu (Code Review) 28 Mar '24

28 Mar '24

Attention is currently required from: Dinesh Gehlot, Elyes Haouas, Eran Mitrani, Hung-Te Lin, Jason Nien, Kapil Porwal, Martin Roth, Nick Vaccaro, Subrata Banik, Tarun, Yidi Lin. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81477?usp=email ) Change subject: mb/google: Remove blank lines before '}' and after '{' ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81477?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If68303cd59b287c8a5c982063b2ab75fd74898d6 Gerrit-Change-Number: 81477 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Thu, 28 Mar 2024 09:17:17 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: soc/intel/xeon_sp: Redefine data types for 6th Gen adoption
by Shuo Liu (Code Review) 28 Mar '24

28 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, David Hendricks, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Shuo Liu, TangYiwei, Tim Chu. Hello Arthur Heymans, Christian Walter, David Hendricks, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, TangYiwei, Tim Chu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81040?usp=email to look at the new patch set (#25). The following approvals got outdated and were removed: Code-Review+2 by Patrick Rudolph, Verified+1 by build bot (Jenkins) The change is no longer submittable: Code-Review and Verified are unsatisfied now. Change subject: soc/intel/xeon_sp: Redefine data types for 6th Gen adoption ...................................................................... soc/intel/xeon_sp: Redefine data types for 6th Gen adoption GraniteRapids (6th Gen Xeon-SP) FSP introduces UDS_STACK_RES/ UDS_SOCKET_RES and retires the usages of STACK_RES/ IIO_RESOURCE_INSTANCE. Make redinitions to make Xeon-SP common codes to work for both 6th Gen before and later. Change-Id: I28c948525cd6d7ac4b9c3fa67e3c99ec637ed38f Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> --- M src/soc/intel/xeon_sp/chip_common.c M src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h M src/soc/intel/xeon_sp/include/soc/chip_common.h M src/soc/intel/xeon_sp/include/soc/util.h M src/soc/intel/xeon_sp/skx/include/soc/soc_util.h M src/soc/intel/xeon_sp/spr/include/soc/soc_util.h 6 files changed, 24 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/81040/25 -- To view, visit https://review.coreboot.org/c/coreboot/+/81040?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I28c948525cd6d7ac4b9c3fa67e3c99ec637ed38f Gerrit-Change-Number: 81040 Gerrit-PatchSet: 25 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: TangYiwei Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[main]: mb/intel/avenuecity_crb: Add Avenue City CRB
by Varshit Pandya (Code Review) 28 Mar '24

28 Mar '24

Attention is currently required from: Arthur Heymans, David Hendricks, Jincheng Li, Jonathan Zhang, Lean Sheng Tan, Nicholas Chin, Patrick Rudolph, Shuo Liu, TangYiwei. Varshit Pandya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81319?usp=email ) Change subject: mb/intel/avenuecity_crb: Add Avenue City CRB ...................................................................... Patch Set 26: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/81319?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I64fdd5388aadf7732f6d3daa600c1455d3672a46 Gerrit-Change-Number: 81319 Gerrit-PatchSet: 26 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-CC: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: TangYiwei Gerrit-Comment-Date: Thu, 28 Mar 2024 09:10:47 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: soc/intel/alderlake: Remove FSP_PUBLISH_MBP_HOB config for RPL
by Varshit Pandya (Code Review) 28 Mar '24

28 Mar '24

Attention is currently required from: Dinesh Gehlot, Kapil Porwal, Kilari Raasi, Nick Vaccaro, Paul Menzel. Varshit Pandya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81446?usp=email ) Change subject: soc/intel/alderlake: Remove FSP_PUBLISH_MBP_HOB config for RPL ...................................................................... Patch Set 7: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/81446?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8a99a57b644732074e41051d99e63576f1edd229 Gerrit-Change-Number: 81446 Gerrit-PatchSet: 7 Gerrit-Owner: Kilari Raasi <kilari.raasi(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kilari Raasi <kilari.raasi(a)intel.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kilari Raasi <kilari.raasi(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Thu, 28 Mar 2024 09:10:20 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[L] Change in coreboot[main]: mb/intel/avenuecity_crb: Add Beechnut City CRB
by Shuo Liu (Code Review) 28 Mar '24

28 Mar '24

Attention is currently required from: Arthur Heymans, Chen, Gang C, David Hendricks, Jincheng Li, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Shuo Liu, TangYiwei. Hello Arthur Heymans, Chen, Gang C, David Hendricks, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, TangYiwei, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81322?usp=email to look at the new patch set (#6). Change subject: mb/intel/avenuecity_crb: Add Beechnut City CRB ...................................................................... mb/intel/avenuecity_crb: Add Beechnut City CRB Beechnut City CRB is the reference board for 6th Gen Xeon-SP SP SoCs (Granite Rapids SP and Sierra Forest SP). This patch initially sets the code set up as a compilation target with GNR N-1 FSP, and with basic feature supports (Integrated IO Controller (IIO) configuration, BMC, UART, HPET). Change-Id: I3f6a0fb97b62baadb438fb9f11fdd78fccb3f89a Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> Signed-off-by: Gang Chen <gang.c.chen(a)intel.com> --- A configs/builder/config.intel.crb.bnc A src/mainboard/intel/beechnutcity_crb/Kconfig A src/mainboard/intel/beechnutcity_crb/Kconfig.name A src/mainboard/intel/beechnutcity_crb/Makefile.mk A src/mainboard/intel/beechnutcity_crb/board.fmd A src/mainboard/intel/beechnutcity_crb/board_info.txt A src/mainboard/intel/beechnutcity_crb/bootblock.c A src/mainboard/intel/beechnutcity_crb/devicetree.cb A src/mainboard/intel/beechnutcity_crb/dsdt.asl A src/mainboard/intel/beechnutcity_crb/include/config/iio.h A src/mainboard/intel/beechnutcity_crb/ramstage.c A src/mainboard/intel/beechnutcity_crb/romstage.c 12 files changed, 288 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/81322/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/81322?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3f6a0fb97b62baadb438fb9f11fdd78fccb3f89a Gerrit-Change-Number: 81322 Gerrit-PatchSet: 6 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: TangYiwei Gerrit-MessageType: newpatchset

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[L] Change in coreboot[main]: soc/intel/xeon_sp: Unshare Xeon-SP chip common codes
by Shuo Liu (Code Review) 28 Mar '24

28 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, David Hendricks, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Martin L Roth, Nico Huber, Patrick Rudolph, Paul Menzel, TangYiwei, Tim Chu. Hello Arthur Heymans, Christian Walter, David Hendricks, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Nico Huber, Patrick Rudolph, TangYiwei, Tim Chu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81312?usp=email to look at the new patch set (#22). The following approvals got outdated and were removed: Code-Review+1 by Nico Huber, Verified+1 by build bot (Jenkins) Change subject: soc/intel/xeon_sp: Unshare Xeon-SP chip common codes ...................................................................... soc/intel/xeon_sp: Unshare Xeon-SP chip common codes GraniteRapids (6th Gen Xeon-SP) FSP contains changes in IIO stack descriptors impacting the way of coreboot's creation of domains. Separates the codes as preparation for 6th Gen and later platforms. Change-Id: Iab6acaa5e5c090c8d821bd7c2d3e0e0ad7486bdc Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> --- M src/soc/intel/xeon_sp/chip_common.c A src/soc/intel/xeon_sp/chip_gen1.c M src/soc/intel/xeon_sp/cpx/Makefile.mk M src/soc/intel/xeon_sp/include/soc/chip_common.h M src/soc/intel/xeon_sp/skx/Makefile.mk M src/soc/intel/xeon_sp/spr/Makefile.mk M src/soc/intel/xeon_sp/spr/ioat.c 7 files changed, 221 insertions(+), 194 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/81312/22 -- To view, visit https://review.coreboot.org/c/coreboot/+/81312?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iab6acaa5e5c090c8d821bd7c2d3e0e0ad7486bdc Gerrit-Change-Number: 81312 Gerrit-PatchSet: 22 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: TangYiwei Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: include/device/pci_ids.h: Add DIDs for MTL Touch controller
by Varshit Pandya (Code Review) 28 Mar '24

28 Mar '24

Attention is currently required from: Cliff Huang, Eran Mitrani, Jingyuan Liang. Varshit Pandya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81330?usp=email ) Change subject: include/device/pci_ids.h: Add DIDs for MTL Touch controller ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/81330/comment/6f96bc0d_d605c9f7 : PS1, Line 9: DID is 0x7e49 for : THC0, and 0x7e4b for THC1. is this documented somewhere ? would be good to have a reference to the doc if it is. -- To view, visit https://review.coreboot.org/c/coreboot/+/81330?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1b98fdbd8d8588492bcafa0f3998818dc83ff1d9 Gerrit-Change-Number: 81330 Gerrit-PatchSet: 1 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jingyuan Liang <jingyliang(a)google.com> Gerrit-Reviewer: Kyoung Il Kim <kyoung.il.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Henry Barnor <hbarnor(a)chromium.org> Gerrit-CC: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-CC: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Jingyuan Liang <jingyliang(a)google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Comment-Date: Thu, 28 Mar 2024 09:05:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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