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I'd like you to reexamine a change. Please visit
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Verified+1 by build bot (Jenkins)
Change subject: soc/intel/xeon_sp: Unshare Xeon-SP chip common codes
......................................................................
soc/intel/xeon_sp: Unshare Xeon-SP chip common codes
GraniteRapids (6th Gen Xeon-SP) FSP contains changes in IIO stack
descriptors impacting the way of coreboot's creation of domains.
Separates the codes as preparation for 6th Gen and later platforms.
Change-Id: Iab6acaa5e5c090c8d821bd7c2d3e0e0ad7486bdc
Signed-off-by: Shuo Liu <shuo.liu(a)intel.com>
---
M src/soc/intel/xeon_sp/chip_common.c
A src/soc/intel/xeon_sp/chip_gen1.c
M src/soc/intel/xeon_sp/cpx/Makefile.mk
M src/soc/intel/xeon_sp/include/soc/chip_common.h
M src/soc/intel/xeon_sp/skx/Makefile.mk
M src/soc/intel/xeon_sp/spr/Makefile.mk
M src/soc/intel/xeon_sp/spr/ioat.c
7 files changed, 224 insertions(+), 194 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/81312/24
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Change subject: drivers/intel/fsp2_0: Support FSP-T in long mode
......................................................................
Patch Set 4: Code-Review+1
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Change subject: mb/google/{brya,hades}: use soc index for variant_update_power_limits()
......................................................................
Patch Set 7:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/81436/comment/88d7b59e_92b511fd :
PS5, Line 13: override the PL4 value
> The purpose of this code is to override PL1/PL2/PL4 settings for the each board according to thier p […]
Acknowledged
File src/mainboard/google/brya/variants/baseboard/brya/ramstage.c:
https://review.coreboot.org/c/coreboot/+/81436/comment/a2fa5722_eb06cee1 :
PS5, Line 68: soc_config->tdp_pl4 = DIV_ROUND_UP(limits[i].pl4_power,
> > SOC will use the lower PL1/PL2 value of MMIO and MSR. […]
Acknowledged
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Change subject: mb/google/nissa: Create sundance variant
......................................................................
Patch Set 13:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/81347/comment/63acff1e_de445a0c :
PS12, Line 15: BUG=b:328505938
> if this patch is tested, it would be good to add info on how it was tested.
Done
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I'd like you to reexamine a change. Please visit
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Change subject: mb/google/nissa: Create sundance variant
......................................................................
mb/google/nissa: Create sundance variant
Create the sundance variant of nissa reference board by copying the
template files to a new directory named for the variant.
Due to new_variant.py limitation that repo can no longer be used in
inside, created this CL manually following google suggestion.
BUG=b:328505938
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_SUNDANCE
Change-Id: Ia8ba318f18d2cac69898687311631778e61bf2ea
Signed-off-by: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com>
---
M src/mainboard/google/brya/Kconfig
M src/mainboard/google/brya/Kconfig.name
A src/mainboard/google/brya/variants/sundance/include/variant/ec.h
A src/mainboard/google/brya/variants/sundance/include/variant/gpio.h
A src/mainboard/google/brya/variants/sundance/memory/Makefile.mk
A src/mainboard/google/brya/variants/sundance/memory/dram_id.generated.txt
A src/mainboard/google/brya/variants/sundance/memory/mem_parts_used.txt
A src/mainboard/google/brya/variants/sundance/overridetree.cb
8 files changed, 47 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/81347/13
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Change subject: mb/google/screebo: Add FW_CONFIG and device for VPU
......................................................................
Set Ready For Review
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