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Change subject: intel/common/pch: Add Kconfig SOC_INTEL_COMMON_IBL_BASE
......................................................................
Patch Set 25:
(1 comment)
Patchset:
PS24:
> could you help to briefly mention which features are absent/ different from the PCH platforms? that […]
Sure, updated. And details diff could be referred to IBL_SPECIFIC_BASE_OPTIONS.
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Change subject: mb/google/{brya,hades}: use soc index for variant_update_power_limits()
......................................................................
Patch Set 8:
(1 comment)
File src/mainboard/google/brya/variants/baseboard/brya/ramstage.c:
https://review.coreboot.org/c/coreboot/+/81436/comment/730ca470_0fbbeff8 :
PS8, Line 69:
https://review.coreboot.org/c/coreboot/+/81436/8/src/mainboard/google/brya/…
can you please follow unified style across?
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Change subject: mb/intel/avenuecity_crb: Add 2S GNR/SRF-AP server board Avenue City
......................................................................
Patch Set 28:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/81319/comment/fcce3c88_17e108d1 :
PS27, Line 7: Add Avenue City CRB
:
> Please add the socket number and “chipset name abbreviation“ into the summary.
Done
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Change subject: mb/intel/beechnutcity_crb: Add GNR/SRF-SP 2S server board Beechnut City
......................................................................
Patch Set 9:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/81322/comment/293d33ae_0bbb0533 :
PS5, Line 7: Add Beechnut City CRB initial support
> Please follow the “template”.
Done
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Change subject: soc/intel/xeon_sp: Remove PAM lock and unlock operations
......................................................................
Patch Set 13:
(1 comment)
File src/soc/intel/xeon_sp/util.c:
https://review.coreboot.org/c/coreboot/+/81349/comment/ebfadc9f_57a94fb0 :
PS5, Line 115: lock_pam0123
> Why was this removed? Does FSP lock PAM on all sockets even when CHIPSET_LOCKDOWN_COREBOOT is used?
In UEFI (in bootloader and in FSP), CPX/SKX need the lock, but SPR doesn't need nor do the lock. So based on the alignment, I think it should be okay. We can take this pattern as of now and handle additional requirement later if any. Your opinion?
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Change subject: mb/google/{brya,hades}: use soc index for variant_update_power_limits()
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Patch Set 8:
(1 comment)
File src/mainboard/google/brya/variants/baseboard/brya/ramstage.c:
https://review.coreboot.org/c/coreboot/+/81436/comment/e6ec53dc_89413be2 :
PS7, Line 72:
> nit: one tab less may be ?
Done
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Change subject: mb/google/screebo: Add FW_CONFIG and device for VPU
......................................................................
Patch Set 1:
(1 comment)
File src/mainboard/google/rex/variants/screebo/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/81560/comment/bed311b1_d8bcc50d :
PS1, Line 33: field VPU 22
: option VPU_DIS 0
: option VPU_EN 1
: end
have you verified the config.star as well for making the same entry there for Screebo ?
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Change subject: mb/google/{brya,hades}: use soc index for variant_update_power_limits()
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Patch Set 7:
(1 comment)
File src/mainboard/google/brya/variants/baseboard/brya/ramstage.c:
https://review.coreboot.org/c/coreboot/+/81436/comment/40b08385_cbab8763 :
PS7, Line 72:
nit: one tab less may be ?
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Change subject: mb/google/brya/var/bujia: Add VBT data files for bujia
......................................................................
Patch Set 2:
(1 comment)
File src/mainboard/google/brya/Kconfig:
https://review.coreboot.org/c/coreboot/+/81553/comment/a1933a15_b672acfc :
PS2, Line 170: select INTEL_GMA_HAVE_VBT
please pay attention towards order ?
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Change subject: mb/google/brya/var/xol: Update GPIO settings for speaker and DMIC
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Patch Set 3: Code-Review+2
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