coreboot-gerrit March 2024

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[S] Change in coreboot[main]: soc/intel/xeon_sp: Redefine data types for GNR
by Lean Sheng Tan (Code Review) 30 Mar '24

30 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, David Hendricks, Johnny Lin, Jonathan Zhang, Patrick Rudolph, Paul Menzel, Shuo Liu, TangYiwei, Tim Chu. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81040?usp=email ) Change subject: soc/intel/xeon_sp: Redefine data types for GNR ...................................................................... Patch Set 27: Code-Review+2 (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/81040/comment/97eaed90_2fa4fde1 : PS26, Line 7: 6th Gen adoption > Add (GRP) at the end? Done https://review.coreboot.org/c/coreboot/+/81040/comment/a6079009_f8637baa : PS26, Line 9: GraniteRapids > Granite Rapids Done -- To view, visit https://review.coreboot.org/c/coreboot/+/81040?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I28c948525cd6d7ac4b9c3fa67e3c99ec637ed38f Gerrit-Change-Number: 81040 Gerrit-PatchSet: 27 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: TangYiwei Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Sat, 30 Mar 2024 07:46:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: soc/intel/xeon_sp: Redefine data types for GNR
by Lean Sheng Tan (Code Review) 30 Mar '24

30 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, David Hendricks, Johnny Lin, Jonathan Zhang, Patrick Rudolph, Shuo Liu, TangYiwei, Tim Chu. Lean Sheng Tan has uploaded a new patch set (#27) to the change originally created by Shuo Liu. ( https://review.coreboot.org/c/coreboot/+/81040?usp=email ) Change subject: soc/intel/xeon_sp: Redefine data types for GNR ...................................................................... soc/intel/xeon_sp: Redefine data types for GNR Granite Rapids (6th Gen Xeon-SP) FSP introduces UDS_STACK_RES/ UDS_SOCKET_RES and retires the usages of STACK_RES/ IIO_RESOURCE_INSTANCE. Make redinitions to make Xeon-SP common codes to work for both 6th Gen before and later. Change-Id: I28c948525cd6d7ac4b9c3fa67e3c99ec637ed38f Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> --- M src/soc/intel/xeon_sp/chip_common.c M src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h M src/soc/intel/xeon_sp/include/soc/chip_common.h M src/soc/intel/xeon_sp/include/soc/util.h M src/soc/intel/xeon_sp/skx/include/soc/soc_util.h M src/soc/intel/xeon_sp/spr/include/soc/soc_util.h 6 files changed, 23 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/81040/27 -- To view, visit https://review.coreboot.org/c/coreboot/+/81040?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I28c948525cd6d7ac4b9c3fa67e3c99ec637ed38f Gerrit-Change-Number: 81040 Gerrit-PatchSet: 27 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: TangYiwei Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[main]: mb/google: Remove blank lines before '}' and after '{'
by Elyes Haouas (Code Review) 30 Mar '24

30 Mar '24

Elyes Haouas has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81477?usp=email ) Change subject: mb/google: Remove blank lines before '}' and after '{' ...................................................................... mb/google: Remove blank lines before '}' and after '{' Change-Id: If68303cd59b287c8a5c982063b2ab75fd74898d6 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81477 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <ericllai(a)google.com> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Reviewed-by: Jakub Czapiga <czapiga(a)google.com> --- M src/mainboard/google/brox/mainboard.c M src/mainboard/google/brya/mainboard.c M src/mainboard/google/brya/variants/aurash/fw_config.c M src/mainboard/google/brya/variants/brask/fw_config.c M src/mainboard/google/brya/variants/felwinter/fw_config.c M src/mainboard/google/brya/variants/moli/fw_config.c M src/mainboard/google/brya/variants/volmar/variant.c M src/mainboard/google/brya/variants/xivu/fw_config.c M src/mainboard/google/brya/variants/xol/gpio.c M src/mainboard/google/butterfly/ec.c M src/mainboard/google/butterfly/mainboard.c M src/mainboard/google/cherry/chromeos.c M src/mainboard/google/cherry/regulator.c M src/mainboard/google/cyan/variants/banon/romstage.c M src/mainboard/google/cyan/variants/celes/ramstage.c M src/mainboard/google/cyan/variants/edgar/romstage.c M src/mainboard/google/cyan/variants/kefka/ramstage.c M src/mainboard/google/cyan/variants/kefka/romstage.c M src/mainboard/google/cyan/variants/reks/romstage.c M src/mainboard/google/cyan/variants/relm/romstage.c M src/mainboard/google/cyan/variants/setzer/romstage.c M src/mainboard/google/cyan/variants/terra/romstage.c M src/mainboard/google/cyan/variants/ultima/gpio.c M src/mainboard/google/dedede/mainboard.c M src/mainboard/google/dedede/variants/baseboard/memory.c M src/mainboard/google/dedede/variants/beadrix/memory.c M src/mainboard/google/dedede/variants/drawcia/gpio.c M src/mainboard/google/dedede/variants/drawcia/variant.c M src/mainboard/google/dedede/variants/galtic/gpio.c M src/mainboard/google/dedede/variants/pirika/gpio.c M src/mainboard/google/fizz/variants/baseboard/nhlt.c M src/mainboard/google/fizz/variants/endeavour/board.c M src/mainboard/google/fizz/variants/karma/nhlt.c M src/mainboard/google/gale/bootblock.c M src/mainboard/google/gale/verstage.c M src/mainboard/google/gru/sdram_configs.c M src/mainboard/google/guybrush/romstage.c M src/mainboard/google/hatch/variants/nightfury/gpio.c M src/mainboard/google/kahlee/mainboard.c M src/mainboard/google/kukui/bootblock.c M src/mainboard/google/mistral/bootblock.c M src/mainboard/google/mistral/chromeos.c M src/mainboard/google/nyan/mainboard.c M src/mainboard/google/nyan_big/mainboard.c M src/mainboard/google/nyan_blaze/mainboard.c M src/mainboard/google/octopus/smihandler.c M src/mainboard/google/octopus/variants/bloog/gpio.c M src/mainboard/google/octopus/variants/fleex/gpio.c M src/mainboard/google/peach_pit/romstage.c M src/mainboard/google/poppy/variants/nami/nhlt.c M src/mainboard/google/poppy/variants/nautilus/nhlt.c M src/mainboard/google/poppy/variants/rammus/nhlt.c M src/mainboard/google/rex/variants/deku/gpio.c M src/mainboard/google/skyrim/bootblock.c M src/mainboard/google/skyrim/variants/markarth/gpio.c M src/mainboard/google/skyrim/variants/winterhold/gpio.c M src/mainboard/google/storm/bootblock.c M src/mainboard/google/stout/early_init.c M src/mainboard/google/stout/ec.c M src/mainboard/google/zork/variants/baseboard/ramstage_common.c M src/mainboard/google/zork/variants/baseboard/trembyle/fsps.c M src/mainboard/google/zork/variants/baseboard/trembyle/gpio.c M src/mainboard/google/zork/variants/dirinboz/variant.c M src/mainboard/google/zork/variants/gumboz/variant.c 64 files changed, 0 insertions(+), 73 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved Eric Lai: Looks good to me, approved Jakub Czapiga: Looks good to me, approved diff --git a/src/mainboard/google/brox/mainboard.c b/src/mainboard/google/brox/mainboard.c index 5820805..9285ae2 100644 --- a/src/mainboard/google/brox/mainboard.c +++ b/src/mainboard/google/brox/mainboard.c @@ -191,7 +191,6 @@ mainboard_generate_s0ix_hook(); acpigen_write_method_end(); /* Method */ acpigen_write_scope_end(); /* Scope */ - } void __weak variant_fill_ssdt(const struct device *dev) diff --git a/src/mainboard/google/brya/mainboard.c b/src/mainboard/google/brya/mainboard.c index 9cf56b2..07aa4b5 100644 --- a/src/mainboard/google/brya/mainboard.c +++ b/src/mainboard/google/brya/mainboard.c @@ -191,7 +191,6 @@ mainboard_generate_s0ix_hook(); acpigen_write_method_end(); /* Method */ acpigen_write_scope_end(); /* Scope */ - } void __weak variant_fill_ssdt(const struct device *dev) diff --git a/src/mainboard/google/brya/variants/aurash/fw_config.c b/src/mainboard/google/brya/variants/aurash/fw_config.c index 5302923..4491781 100644 --- a/src/mainboard/google/brya/variants/aurash/fw_config.c +++ b/src/mainboard/google/brya/variants/aurash/fw_config.c @@ -39,6 +39,5 @@ printk(BIOS_INFO, "BT offload enabled over I2S with NAU88L25B\n"); gpio_configure_pads(bt_i2s_enable_pads, ARRAY_SIZE(bt_i2s_enable_pads)); } - } BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL); diff --git a/src/mainboard/google/brya/variants/brask/fw_config.c b/src/mainboard/google/brya/variants/brask/fw_config.c index 5302923..4491781 100644 --- a/src/mainboard/google/brya/variants/brask/fw_config.c +++ b/src/mainboard/google/brya/variants/brask/fw_config.c @@ -39,6 +39,5 @@ printk(BIOS_INFO, "BT offload enabled over I2S with NAU88L25B\n"); gpio_configure_pads(bt_i2s_enable_pads, ARRAY_SIZE(bt_i2s_enable_pads)); } - } BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL); diff --git a/src/mainboard/google/brya/variants/felwinter/fw_config.c b/src/mainboard/google/brya/variants/felwinter/fw_config.c index 2a89c94..584c9a5 100644 --- a/src/mainboard/google/brya/variants/felwinter/fw_config.c +++ b/src/mainboard/google/brya/variants/felwinter/fw_config.c @@ -40,6 +40,5 @@ printk(BIOS_INFO, "BT offload enabled over I2S with MAX98360+RT5682VS\n"); gpio_configure_pads(bt_i2s_enable_pads, ARRAY_SIZE(bt_i2s_enable_pads)); } - } BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL); diff --git a/src/mainboard/google/brya/variants/moli/fw_config.c b/src/mainboard/google/brya/variants/moli/fw_config.c index 5302923..4491781 100644 --- a/src/mainboard/google/brya/variants/moli/fw_config.c +++ b/src/mainboard/google/brya/variants/moli/fw_config.c @@ -39,6 +39,5 @@ printk(BIOS_INFO, "BT offload enabled over I2S with NAU88L25B\n"); gpio_configure_pads(bt_i2s_enable_pads, ARRAY_SIZE(bt_i2s_enable_pads)); } - } BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL); diff --git a/src/mainboard/google/brya/variants/volmar/variant.c b/src/mainboard/google/brya/variants/volmar/variant.c index d1ef1fa..1521fea 100644 --- a/src/mainboard/google/brya/variants/volmar/variant.c +++ b/src/mainboard/google/brya/variants/volmar/variant.c @@ -17,5 +17,4 @@ if (fw_config_probe(FW_CONFIG(FPMCU_MASK, FPMCU_DISABLED))) config->serial_io_gspi_mode[PchSerialIoIndexGSPI1] = PchSerialIoDisabled; - } diff --git a/src/mainboard/google/brya/variants/xivu/fw_config.c b/src/mainboard/google/brya/variants/xivu/fw_config.c index 9008b95..f292404 100644 --- a/src/mainboard/google/brya/variants/xivu/fw_config.c +++ b/src/mainboard/google/brya/variants/xivu/fw_config.c @@ -24,5 +24,4 @@ gpio_padbased_override(padbased_table, wfc_disable_pads, ARRAY_SIZE(wfc_disable_pads)); } - } diff --git a/src/mainboard/google/brya/variants/xol/gpio.c b/src/mainboard/google/brya/variants/xol/gpio.c index 3a92b8e..13fd10d 100644 --- a/src/mainboard/google/brya/variants/xol/gpio.c +++ b/src/mainboard/google/brya/variants/xol/gpio.c @@ -221,7 +221,6 @@ { *num = ARRAY_SIZE(gpio_overrides); return gpio_overrides; - } const struct pad_config *variant_early_gpio_table(size_t *num) diff --git a/src/mainboard/google/butterfly/ec.c b/src/mainboard/google/butterfly/ec.c index 4e5e422..b979bf5 100644 --- a/src/mainboard/google/butterfly/ec.c +++ b/src/mainboard/google/butterfly/ec.c @@ -18,5 +18,4 @@ /* Disable wake on USB, LAN & RTC */ /* Enable Wake from Keyboard */ ec_mem_write(EC_EC_PSW, EC_PSW_IKB); - } diff --git a/src/mainboard/google/butterfly/mainboard.c b/src/mainboard/google/butterfly/mainboard.c index 988c210..a574d38 100644 --- a/src/mainboard/google/butterfly/mainboard.c +++ b/src/mainboard/google/butterfly/mainboard.c @@ -126,7 +126,6 @@ char kbd_type = EC_KBD_EN; /* Default keyboard type is English */ if (search_length != -1) { - /* * Search for keyboard_layout identifier * The only options in the EC are Japanese or English. diff --git a/src/mainboard/google/cherry/chromeos.c b/src/mainboard/google/cherry/chromeos.c index 4a93ae2..7838c5e 100644 --- a/src/mainboard/google/cherry/chromeos.c +++ b/src/mainboard/google/cherry/chromeos.c @@ -21,7 +21,6 @@ gpio_output(GPIO_BEEP_ON, 0); else if (CONFIG(CHERRY_USE_RT1011)) gpio_output(GPIO_RST_RT1011, 0); - } void fill_lb_gpios(struct lb_gpios *gpios) diff --git a/src/mainboard/google/cherry/regulator.c b/src/mainboard/google/cherry/regulator.c index 61f53d1..83ba9ed 100644 --- a/src/mainboard/google/cherry/regulator.c +++ b/src/mainboard/google/cherry/regulator.c @@ -174,7 +174,6 @@ } return !!enabled; } - } printk(BIOS_ERR, "Invalid regulator ID: %d\n; assuming disabled", regulator); diff --git a/src/mainboard/google/cyan/variants/banon/romstage.c b/src/mainboard/google/cyan/variants/banon/romstage.c index 7dcf622..a711e19 100644 --- a/src/mainboard/google/cyan/variants/banon/romstage.c +++ b/src/mainboard/google/cyan/variants/banon/romstage.c @@ -13,7 +13,6 @@ * RAMID = 12 - 2GiB Micron MT52L256M32D1PF */ if (ram_id == 4 || ram_id == 12) { - /* * For new micron part, it requires read/receive * enable training before sending cmds to get MR8. diff --git a/src/mainboard/google/cyan/variants/celes/ramstage.c b/src/mainboard/google/cyan/variants/celes/ramstage.c index a126a48..a287838 100644 --- a/src/mainboard/google/cyan/variants/celes/ramstage.c +++ b/src/mainboard/google/cyan/variants/celes/ramstage.c @@ -5,7 +5,6 @@ void board_silicon_USB2_override(SILICON_INIT_UPD *params) { if (SocStepping() >= SocD0) { - //Follow Intel recommendation to set //BSW D-stepping PERPORTRXISET 2 (low strength) params->Usb2Port0PerPortPeTxiSet = 7; diff --git a/src/mainboard/google/cyan/variants/edgar/romstage.c b/src/mainboard/google/cyan/variants/edgar/romstage.c index 7b1d8cc..af55b8a 100644 --- a/src/mainboard/google/cyan/variants/edgar/romstage.c +++ b/src/mainboard/google/cyan/variants/edgar/romstage.c @@ -13,7 +13,6 @@ * RAMID = 7 - 2GiB Micron MT52L256M32D1PF-107 */ if (ram_id == 5 || ram_id == 7) { - /* * For new micron part, it requires read/receive * enable training before sending cmds to get MR8. diff --git a/src/mainboard/google/cyan/variants/kefka/ramstage.c b/src/mainboard/google/cyan/variants/kefka/ramstage.c index e1fd33a..96d53c2 100644 --- a/src/mainboard/google/cyan/variants/kefka/ramstage.c +++ b/src/mainboard/google/cyan/variants/kefka/ramstage.c @@ -5,7 +5,6 @@ void board_silicon_USB2_override(SILICON_INIT_UPD *params) { if (SocStepping() >= SocD0) { - //Follow Intel recommendation to set //BSW D-stepping PERPORTRXISET 2 (low strength) params->D0Usb2Port0PerPortRXISet = 2; diff --git a/src/mainboard/google/cyan/variants/kefka/romstage.c b/src/mainboard/google/cyan/variants/kefka/romstage.c index 9492b84..d5e8883 100644 --- a/src/mainboard/google/cyan/variants/kefka/romstage.c +++ b/src/mainboard/google/cyan/variants/kefka/romstage.c @@ -13,7 +13,6 @@ * RAMID = 3 - 2GiB Micron MT52L256M32D1PF-107 */ if (ram_id == 2 || ram_id == 3) { - /* * For new micron part, it requires read/receive * enable training before sending cmds to get MR8. diff --git a/src/mainboard/google/cyan/variants/reks/romstage.c b/src/mainboard/google/cyan/variants/reks/romstage.c index c8fd30b..4b817e5 100644 --- a/src/mainboard/google/cyan/variants/reks/romstage.c +++ b/src/mainboard/google/cyan/variants/reks/romstage.c @@ -13,7 +13,6 @@ * RAMID = 2 - 2GiB Micron MT52L256M32D1PF-107 */ if (ram_id == 2 || ram_id == 0xA) { - /* * For new micron part, it requires read/receive * enable training before sending cmds to get MR8. diff --git a/src/mainboard/google/cyan/variants/relm/romstage.c b/src/mainboard/google/cyan/variants/relm/romstage.c index c8fd30b..4b817e5 100644 --- a/src/mainboard/google/cyan/variants/relm/romstage.c +++ b/src/mainboard/google/cyan/variants/relm/romstage.c @@ -13,7 +13,6 @@ * RAMID = 2 - 2GiB Micron MT52L256M32D1PF-107 */ if (ram_id == 2 || ram_id == 0xA) { - /* * For new micron part, it requires read/receive * enable training before sending cmds to get MR8. diff --git a/src/mainboard/google/cyan/variants/setzer/romstage.c b/src/mainboard/google/cyan/variants/setzer/romstage.c index e8c3c1c..21e1569 100644 --- a/src/mainboard/google/cyan/variants/setzer/romstage.c +++ b/src/mainboard/google/cyan/variants/setzer/romstage.c @@ -13,7 +13,6 @@ * RAMID = 5 - 2GiB Micron MT52L256M32D1PF-107 */ if (ram_id == 4 || ram_id == 5) { - /* * For new micron part, it requires read/receive * enable training before sending cmds to get MR8. diff --git a/src/mainboard/google/cyan/variants/terra/romstage.c b/src/mainboard/google/cyan/variants/terra/romstage.c index 5bdd7fe..531f1ea 100644 --- a/src/mainboard/google/cyan/variants/terra/romstage.c +++ b/src/mainboard/google/cyan/variants/terra/romstage.c @@ -13,7 +13,6 @@ * RAMID = 11 - 4GiB Micron MT52L256M32D1PF-107 */ if (ram_id == 3 || ram_id == 11) { - /* * For new micron part, it requires read/receive * enable training before sending cmds to get MR8. diff --git a/src/mainboard/google/cyan/variants/ultima/gpio.c b/src/mainboard/google/cyan/variants/ultima/gpio.c index ede6229..13cc639 100644 --- a/src/mainboard/google/cyan/variants/ultima/gpio.c +++ b/src/mainboard/google/cyan/variants/ultima/gpio.c @@ -237,5 +237,4 @@ struct soc_gpio_config *mainboard_get_gpios(void) { return &gpio_config; - } diff --git a/src/mainboard/google/dedede/mainboard.c b/src/mainboard/google/dedede/mainboard.c index b381d98..aae4155 100644 --- a/src/mainboard/google/dedede/mainboard.c +++ b/src/mainboard/google/dedede/mainboard.c @@ -128,18 +128,15 @@ static void mainboard_fill_ssdt(const struct device *dev) { - acpigen_write_scope("\\_SB"); acpigen_write_method_serialized("MS0X", 1); mainboard_generate_s0ix_hook(); acpigen_write_method_end(); /* Method */ acpigen_write_scope_end(); /* Scope */ - } void __weak variant_generate_s0ix_hook(enum s0ix_entry entry) { - /* Add board-specific MS0X entries */ /* if (s0ix_entry == S0IX_ENTRY) { diff --git a/src/mainboard/google/dedede/variants/baseboard/memory.c b/src/mainboard/google/dedede/variants/baseboard/memory.c index aa52636..da8439a 100644 --- a/src/mainboard/google/dedede/variants/baseboard/memory.c +++ b/src/mainboard/google/dedede/variants/baseboard/memory.c @@ -7,7 +7,6 @@ #include <soc/romstage.h> static const struct mb_cfg baseboard_memcfg_cfg = { - .dq_map[DDR_CH0] = { {0xf, 0xf0}, {0xf, 0xf0}, diff --git a/src/mainboard/google/dedede/variants/beadrix/memory.c b/src/mainboard/google/dedede/variants/beadrix/memory.c index bfef45b..d80832d 100644 --- a/src/mainboard/google/dedede/variants/beadrix/memory.c +++ b/src/mainboard/google/dedede/variants/beadrix/memory.c @@ -7,7 +7,6 @@ #include <soc/romstage.h> static const struct mb_cfg board_memcfg_cfg = { - .dq_map[DDR_CH0] = { {0xf, 0xf0}, {0xf, 0xf0}, diff --git a/src/mainboard/google/dedede/variants/drawcia/gpio.c b/src/mainboard/google/dedede/variants/drawcia/gpio.c index fa4d4d5..d42b38e 100644 --- a/src/mainboard/google/dedede/variants/drawcia/gpio.c +++ b/src/mainboard/google/dedede/variants/drawcia/gpio.c @@ -9,14 +9,12 @@ /* Pad configuration in ramstage */ static const struct pad_config not_board6or8_gpio_table[] = { - /* C12 : AP_PEN_DET_ODL */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, UP_20K, DEEP), }; /* bid6: Pad configuration for board version 6 or 8 in ramstage */ static const struct pad_config board6or8_gpio_table[] = { - /* A10 : WWAN_EN */ PAD_CFG_GPO(GPP_A10, 1, PWROK), diff --git a/src/mainboard/google/dedede/variants/drawcia/variant.c b/src/mainboard/google/dedede/variants/drawcia/variant.c index 9077bae..5f85f6a 100644 --- a/src/mainboard/google/dedede/variants/drawcia/variant.c +++ b/src/mainboard/google/dedede/variants/drawcia/variant.c @@ -19,7 +19,6 @@ uint32_t sku_id = google_chromeec_get_board_sku(); if (fw_config_probe(FW_CONFIG(TABLETMODE, TABLETMODE_ENABLED))) { - if (sku_id >= OSCINO_SKU_START && sku_id <= OSCINO_SKU_END) return "wifi_sar-oscino.hex"; else diff --git a/src/mainboard/google/dedede/variants/galtic/gpio.c b/src/mainboard/google/dedede/variants/galtic/gpio.c index e2e6669..d92bdf5 100644 --- a/src/mainboard/google/dedede/variants/galtic/gpio.c +++ b/src/mainboard/google/dedede/variants/galtic/gpio.c @@ -5,7 +5,6 @@ /* Pad configuration in ramstage */ static const struct pad_config gpio_table[] = { - /* A11 : TOUCH_RPT_EN */ PAD_NC(GPP_A11, NONE), diff --git a/src/mainboard/google/dedede/variants/pirika/gpio.c b/src/mainboard/google/dedede/variants/pirika/gpio.c index e2e6669..d92bdf5 100644 --- a/src/mainboard/google/dedede/variants/pirika/gpio.c +++ b/src/mainboard/google/dedede/variants/pirika/gpio.c @@ -5,7 +5,6 @@ /* Pad configuration in ramstage */ static const struct pad_config gpio_table[] = { - /* A11 : TOUCH_RPT_EN */ PAD_NC(GPP_A11, NONE), diff --git a/src/mainboard/google/fizz/variants/baseboard/nhlt.c b/src/mainboard/google/fizz/variants/baseboard/nhlt.c index 3011955..6dba2b4 100644 --- a/src/mainboard/google/fizz/variants/baseboard/nhlt.c +++ b/src/mainboard/google/fizz/variants/baseboard/nhlt.c @@ -6,11 +6,9 @@ void __weak variant_nhlt_init(struct nhlt *nhlt) { - /* RT5663 Headset codec */ if (nhlt_soc_add_rt5663(nhlt, AUDIO_LINK_SSP1)) printk(BIOS_ERR, "Couldn't add headset codec.\n"); - } void __weak variant_nhlt_oem_overrides(const char **oem_id, diff --git a/src/mainboard/google/fizz/variants/endeavour/board.c b/src/mainboard/google/fizz/variants/endeavour/board.c index 3da8f22..03716c2 100644 --- a/src/mainboard/google/fizz/variants/endeavour/board.c +++ b/src/mainboard/google/fizz/variants/endeavour/board.c @@ -15,5 +15,4 @@ void variant_chip_display_init(void) { - } diff --git a/src/mainboard/google/fizz/variants/karma/nhlt.c b/src/mainboard/google/fizz/variants/karma/nhlt.c index e237d2e..b0f4527 100644 --- a/src/mainboard/google/fizz/variants/karma/nhlt.c +++ b/src/mainboard/google/fizz/variants/karma/nhlt.c @@ -18,7 +18,6 @@ /* MAXIM Smart Amps for left and right speakers. */ if (nhlt_soc_add_max98357(nhlt, AUDIO_LINK_SSP0)) printk(BIOS_ERR, "Couldn't add Maxim_98357 codec.\n"); - } void variant_nhlt_oem_overrides(const char **oem_id, diff --git a/src/mainboard/google/gale/bootblock.c b/src/mainboard/google/gale/bootblock.c index 343fe65..d900510 100644 --- a/src/mainboard/google/gale/bootblock.c +++ b/src/mainboard/google/gale/bootblock.c @@ -39,7 +39,6 @@ /* Is maskrom parameter address set to a sensible value? */ if ((maskrom_param->start_magic != UBER_SBL_SHARED_INFO_START_MAGIC) || (maskrom_param->end_magic != UBER_SBL_SHARED_INFO_END_MAGIC)) { - printk(BIOS_INFO, "Uber-sbl: invalid magic!\n"); } else { printk(BIOS_INFO, "Uber-sbl version: %s\n", diff --git a/src/mainboard/google/gale/verstage.c b/src/mainboard/google/gale/verstage.c index 6dfc230..68a4aa4 100644 --- a/src/mainboard/google/gale/verstage.c +++ b/src/mainboard/google/gale/verstage.c @@ -8,7 +8,6 @@ static void ipq_setup_tpm(void) { - if (CONFIG(I2C_TPM)) { gpio_tlmm_config_set(TPM_RESET_GPIO, FUNC_SEL_GPIO, GPIO_PULL_UP, GPIO_6MA, 1); diff --git a/src/mainboard/google/gru/sdram_configs.c b/src/mainboard/google/gru/sdram_configs.c index aae3377..64f45de 100644 --- a/src/mainboard/google/gru/sdram_configs.c +++ b/src/mainboard/google/gru/sdram_configs.c @@ -9,7 +9,6 @@ #include <types.h> static const char *sdram_configs[] = { - /* Samsung K4E6E304EB-EGCE */ [0] = "sdram-lpddr3-generic-4GB", diff --git a/src/mainboard/google/guybrush/romstage.c b/src/mainboard/google/guybrush/romstage.c index 571eb44..96ac0e6 100644 --- a/src/mainboard/google/guybrush/romstage.c +++ b/src/mainboard/google/guybrush/romstage.c @@ -14,5 +14,4 @@ gpio_configure_pads_with_override(base_gpios, base_num_gpios, override_gpios, override_num_gpios); - } diff --git a/src/mainboard/google/hatch/variants/nightfury/gpio.c b/src/mainboard/google/hatch/variants/nightfury/gpio.c index 1f36e01..1a84bac 100644 --- a/src/mainboard/google/hatch/variants/nightfury/gpio.c +++ b/src/mainboard/google/hatch/variants/nightfury/gpio.c @@ -153,7 +153,6 @@ * See https://review.coreboot.org/c/coreboot/+/32111 . */ static const struct pad_config default_sleep_gpio_table[] = { - }; /* @@ -161,7 +160,6 @@ * default_sleep_gpio_table but also, turn off FPMCU. */ static const struct pad_config s5_sleep_gpio_table[] = { - }; const struct pad_config *variant_sleep_gpio_table(u8 slp_typ, size_t *num) diff --git a/src/mainboard/google/kahlee/mainboard.c b/src/mainboard/google/kahlee/mainboard.c index 5ecc52e..427f094 100644 --- a/src/mainboard/google/kahlee/mainboard.c +++ b/src/mainboard/google/kahlee/mainboard.c @@ -135,7 +135,6 @@ { /* Initialize the PIRQ data structures for consumption */ pirq_setup(); - } int mainboard_get_xhci_oc_map(uint16_t *map) diff --git a/src/mainboard/google/kukui/bootblock.c b/src/mainboard/google/kukui/bootblock.c index d5df223..8324916 100644 --- a/src/mainboard/google/kukui/bootblock.c +++ b/src/mainboard/google/kukui/bootblock.c @@ -12,5 +12,4 @@ 2); gpio_set_spi_driving(CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, SPI_PAD0_MASK, 10); - } diff --git a/src/mainboard/google/mistral/bootblock.c b/src/mainboard/google/mistral/bootblock.c index 4327ccc..5dcae8c 100644 --- a/src/mainboard/google/mistral/bootblock.c +++ b/src/mainboard/google/mistral/bootblock.c @@ -4,5 +4,4 @@ void bootblock_mainboard_init(void) { - } diff --git a/src/mainboard/google/mistral/chromeos.c b/src/mainboard/google/mistral/chromeos.c index 7ffcd57..b9a190e 100644 --- a/src/mainboard/google/mistral/chromeos.c +++ b/src/mainboard/google/mistral/chromeos.c @@ -5,7 +5,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) { - } int get_ec_is_trusted(void) diff --git a/src/mainboard/google/nyan/mainboard.c b/src/mainboard/google/nyan/mainboard.c index e4e7975..ba2fe28 100644 --- a/src/mainboard/google/nyan/mainboard.c +++ b/src/mainboard/google/nyan/mainboard.c @@ -50,7 +50,6 @@ clrsetbits32(&clk_rst->clk_src_disp1, CLK_SOURCE_MASK | CLK_DIVISOR_MASK, 2 /*PLLD_OUT0 */ << CLK_SOURCE_SHIFT); - } static void setup_pinmux(void) diff --git a/src/mainboard/google/nyan_big/mainboard.c b/src/mainboard/google/nyan_big/mainboard.c index 0250b45..3a45729 100644 --- a/src/mainboard/google/nyan_big/mainboard.c +++ b/src/mainboard/google/nyan_big/mainboard.c @@ -50,7 +50,6 @@ clrsetbits32(&clk_rst->clk_src_disp1, CLK_SOURCE_MASK | CLK_DIVISOR_MASK, 2 /*PLLD_OUT0 */ << CLK_SOURCE_SHIFT); - } static void setup_pinmux(void) diff --git a/src/mainboard/google/nyan_blaze/mainboard.c b/src/mainboard/google/nyan_blaze/mainboard.c index d6aa05a..5b82208 100644 --- a/src/mainboard/google/nyan_blaze/mainboard.c +++ b/src/mainboard/google/nyan_blaze/mainboard.c @@ -50,7 +50,6 @@ clrsetbits32(&clk_rst->clk_src_disp1, CLK_SOURCE_MASK | CLK_DIVISOR_MASK, 2 /*PLLD_OUT0 */ << CLK_SOURCE_SHIFT); - } static void setup_pinmux(void) diff --git a/src/mainboard/google/octopus/smihandler.c b/src/mainboard/google/octopus/smihandler.c index 4400342..5d07d5b 100644 --- a/src/mainboard/google/octopus/smihandler.c +++ b/src/mainboard/google/octopus/smihandler.c @@ -62,7 +62,6 @@ void power_off_lte_module(void) { - const struct gpio_with_delay lte_power_off_gpios[] = { { GPIO_161, /* AVS_I2S1_MCLK -- PLT_RST_LTE_L */ diff --git a/src/mainboard/google/octopus/variants/bloog/gpio.c b/src/mainboard/google/octopus/variants/bloog/gpio.c index f77d429..4e09297 100644 --- a/src/mainboard/google/octopus/variants/bloog/gpio.c +++ b/src/mainboard/google/octopus/variants/bloog/gpio.c @@ -5,7 +5,6 @@ #include <gpio.h> static const struct pad_config default_override_table[] = { - PAD_NC(GPIO_50, UP_20K), /* PCH_I2C_PEN_SDA -- unused */ PAD_NC(GPIO_51, UP_20K), /* PCH_I2C_PEN_SCL -- unused */ PAD_NC(GPIO_52, UP_20K), /* PCH_I2C_P_SENSOR_SDA -- unused */ diff --git a/src/mainboard/google/octopus/variants/fleex/gpio.c b/src/mainboard/google/octopus/variants/fleex/gpio.c index 0b561d8..f2e6475 100644 --- a/src/mainboard/google/octopus/variants/fleex/gpio.c +++ b/src/mainboard/google/octopus/variants/fleex/gpio.c @@ -5,7 +5,6 @@ #include <gpio.h> static const struct pad_config default_override_table[] = { - PAD_NC(GPIO_52, UP_20K), PAD_NC(GPIO_53, UP_20K), /* UART2-CTS_B -- EN_PP3300_DX_LTE_SOC */ diff --git a/src/mainboard/google/peach_pit/romstage.c b/src/mainboard/google/peach_pit/romstage.c index e38d1cb..fd310bd 100644 --- a/src/mainboard/google/peach_pit/romstage.c +++ b/src/mainboard/google/peach_pit/romstage.c @@ -194,7 +194,6 @@ printk(BIOS_SPEW, "RTRY at %d(%p):\nRAM %08lx\nSPI %08lx\n", i, &data[i/4], (unsigned long)data[i/4], (unsigned long)in); } - } printk(BIOS_SPEW, "%d errors\n", errors); } @@ -219,7 +218,6 @@ void __noreturn romstage_main(void) { - extern struct mem_timings mem_timings; int is_resume = (get_wakeup_state() != IS_NOT_WAKEUP); int power_init_failed; diff --git a/src/mainboard/google/poppy/variants/nami/nhlt.c b/src/mainboard/google/poppy/variants/nami/nhlt.c index 343b835..5cd8e5a 100644 --- a/src/mainboard/google/poppy/variants/nami/nhlt.c +++ b/src/mainboard/google/poppy/variants/nami/nhlt.c @@ -18,7 +18,6 @@ /* MAXIM Smart Amps for left and right speakers. */ if (nhlt_soc_add_max98357(nhlt, AUDIO_LINK_SSP0)) printk(BIOS_ERR, "Couldn't add Maxim_98357 codec.\n"); - } void variant_nhlt_oem_overrides(const char **oem_id, const char **oem_table_id, diff --git a/src/mainboard/google/poppy/variants/nautilus/nhlt.c b/src/mainboard/google/poppy/variants/nautilus/nhlt.c index 267dbfc..ed44b84 100644 --- a/src/mainboard/google/poppy/variants/nautilus/nhlt.c +++ b/src/mainboard/google/poppy/variants/nautilus/nhlt.c @@ -18,7 +18,6 @@ /* MAXIM Smart Amps for left and right speakers. */ if (nhlt_soc_add_max98357(nhlt, AUDIO_LINK_SSP0)) printk(BIOS_ERR, "Couldn't add Maxim_98357 codec.\n"); - } void variant_nhlt_oem_overrides(const char **oem_id, const char **oem_table_id, diff --git a/src/mainboard/google/poppy/variants/rammus/nhlt.c b/src/mainboard/google/poppy/variants/rammus/nhlt.c index c893ee9..49a3f7a 100644 --- a/src/mainboard/google/poppy/variants/rammus/nhlt.c +++ b/src/mainboard/google/poppy/variants/rammus/nhlt.c @@ -19,7 +19,6 @@ /* Render time_slot is 0 and feedback time_slot is 2 */ if (nhlt_soc_add_max98927(nhlt, AUDIO_LINK_SSP0, 0, 2)) printk(BIOS_ERR, "Couldn't add Maxim MAX98927\n"); - } void variant_nhlt_oem_overrides(const char **oem_id, const char **oem_table_id, diff --git a/src/mainboard/google/rex/variants/deku/gpio.c b/src/mainboard/google/rex/variants/deku/gpio.c index 515b1d0..55464dd 100644 --- a/src/mainboard/google/rex/variants/deku/gpio.c +++ b/src/mainboard/google/rex/variants/deku/gpio.c @@ -409,7 +409,6 @@ const struct pad_config *variant_gpio_table(size_t *num) { - *num = ARRAY_SIZE(gpio_table); return gpio_table; } diff --git a/src/mainboard/google/skyrim/bootblock.c b/src/mainboard/google/skyrim/bootblock.c index d285d7f..30f300c 100644 --- a/src/mainboard/google/skyrim/bootblock.c +++ b/src/mainboard/google/skyrim/bootblock.c @@ -27,11 +27,9 @@ cmos_bit_set = (byte_value & CMOS_BITMAP_SKIP_RESET_TOGGLE) != 0; if (CONFIG(BOARD_GOOGLE_FROSTFLOW)) { - printk(BIOS_SPEW, "Checking DRAM part #\n"); if (google_chromeec_cbi_get_dram_part_num( cbi_part_number, sizeof(cbi_part_number)) == 0) { - skip_reset_toggle = strncmp(cbi_part_number, HYNIX_PART_NAME, HYNIX_PART_LEN) == 0; if (skip_reset_toggle) { printk(BIOS_SPEW, "SKIP_RESET_TOGGLE needed, checking CMOS bit is set\n"); diff --git a/src/mainboard/google/skyrim/variants/markarth/gpio.c b/src/mainboard/google/skyrim/variants/markarth/gpio.c index 9753179..c320228 100644 --- a/src/mainboard/google/skyrim/variants/markarth/gpio.c +++ b/src/mainboard/google/skyrim/variants/markarth/gpio.c @@ -5,7 +5,6 @@ /* GPIO configuration in ramstage */ static const struct soc_amd_gpio override_gpio_table[] = { - /* SOC_PEN_DETECT_ODL => Unused */ PAD_NC(GPIO_3), /* EN_PWR_FP => Unused */ diff --git a/src/mainboard/google/skyrim/variants/winterhold/gpio.c b/src/mainboard/google/skyrim/variants/winterhold/gpio.c index 340bfb6..888ba32 100644 --- a/src/mainboard/google/skyrim/variants/winterhold/gpio.c +++ b/src/mainboard/google/skyrim/variants/winterhold/gpio.c @@ -6,7 +6,6 @@ /* GPIO configuration in ramstage */ static const struct soc_amd_gpio override_gpio_table[] = { - /* SOC_PEN_DETECT_ODL */ PAD_NC(GPIO_3), diff --git a/src/mainboard/google/storm/bootblock.c b/src/mainboard/google/storm/bootblock.c index e7ff6a3..47cb937 100644 --- a/src/mainboard/google/storm/bootblock.c +++ b/src/mainboard/google/storm/bootblock.c @@ -39,7 +39,6 @@ /* Is maskrom parameter address set to a sensible value? */ if ((maskrom_param->start_magic != UBER_SBL_SHARED_INFO_START_MAGIC) || (maskrom_param->end_magic != UBER_SBL_SHARED_INFO_END_MAGIC)) { - printk(BIOS_INFO, "Uber-sbl: invalid magic!\n"); } else { printk(BIOS_INFO, "Uber-sbl version: %s\n", diff --git a/src/mainboard/google/stout/early_init.c b/src/mainboard/google/stout/early_init.c index 0739f6e..e6e6227 100644 --- a/src/mainboard/google/stout/early_init.c +++ b/src/mainboard/google/stout/early_init.c @@ -63,7 +63,6 @@ if (((ec_status & 0x3) == EC_IN_RO_MODE) || ((ec_status & 0x3) == EC_IN_RECOVERY_MODE)) { - printk(BIOS_DEBUG, "EC Cold Boot Detected\n"); if (!rec_mode) { /* diff --git a/src/mainboard/google/stout/ec.c b/src/mainboard/google/stout/ec.c index 2584166..deb2bd2 100644 --- a/src/mainboard/google/stout/ec.c +++ b/src/mainboard/google/stout/ec.c @@ -11,7 +11,6 @@ void stout_ec_init(void) { - printk(BIOS_DEBUG,"%s: EC FW version %x%x\n", __func__, ec_read(EC_FW_VER), ec_read(EC_FW_VER + 1)); diff --git a/src/mainboard/google/zork/variants/baseboard/ramstage_common.c b/src/mainboard/google/zork/variants/baseboard/ramstage_common.c index a544548..44acef9 100644 --- a/src/mainboard/google/zork/variants/baseboard/ramstage_common.c +++ b/src/mainboard/google/zork/variants/baseboard/ramstage_common.c @@ -57,7 +57,6 @@ gpio->pins[0] = GPIO_13; else gpio->pins[0] = GPIO_6; - } void variant_audio_update(void) @@ -73,7 +72,6 @@ */ static void remove_usb_device_reset_gpio(const struct device *usb_dev) { - struct drivers_usb_acpi_config *usb_cfg; /* config_of dies on failure, so a NULL check is not required */ usb_cfg = config_of(usb_dev); diff --git a/src/mainboard/google/zork/variants/baseboard/trembyle/fsps.c b/src/mainboard/google/zork/variants/baseboard/trembyle/fsps.c index ae36731..0f503c7 100644 --- a/src/mainboard/google/zork/variants/baseboard/trembyle/fsps.c +++ b/src/mainboard/google/zork/variants/baseboard/trembyle/fsps.c @@ -119,7 +119,6 @@ *num = ARRAY_SIZE(pco_dxio_descriptors); return pco_dxio_descriptors; } - } static const fsp_ddi_descriptor pco_ddi_descriptors[] = { diff --git a/src/mainboard/google/zork/variants/baseboard/trembyle/gpio.c b/src/mainboard/google/zork/variants/baseboard/trembyle/gpio.c index 3f65d5c..d978360 100644 --- a/src/mainboard/google/zork/variants/baseboard/trembyle/gpio.c +++ b/src/mainboard/google/zork/variants/baseboard/trembyle/gpio.c @@ -193,7 +193,6 @@ PAD_GPO(GPIO_42, LOW), }; gpio_configure_pads(v3_wifi_table, ARRAY_SIZE(v3_wifi_table)); - } static void wifi_power_reset_configure_active_high_power(void) @@ -283,7 +282,6 @@ __weak void finalize_gpios(int slp_typ) { if (variant_has_fingerprint() && slp_typ != ACPI_S3) { - if (fpmcu_needs_delay()) mdelay(550); diff --git a/src/mainboard/google/zork/variants/dirinboz/variant.c b/src/mainboard/google/zork/variants/dirinboz/variant.c index ebe2292..81cadb6 100644 --- a/src/mainboard/google/zork/variants/dirinboz/variant.c +++ b/src/mainboard/google/zork/variants/dirinboz/variant.c @@ -35,7 +35,6 @@ const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num) { - *dxio_descs = baseboard_get_dxio_descriptors(dxio_num); *ddi_descs = &non_hdmi_ddi_descriptors[0]; *ddi_num = ARRAY_SIZE(non_hdmi_ddi_descriptors); diff --git a/src/mainboard/google/zork/variants/gumboz/variant.c b/src/mainboard/google/zork/variants/gumboz/variant.c index ebe2292..81cadb6 100644 --- a/src/mainboard/google/zork/variants/gumboz/variant.c +++ b/src/mainboard/google/zork/variants/gumboz/variant.c @@ -35,7 +35,6 @@ const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num) { - *dxio_descs = baseboard_get_dxio_descriptors(dxio_num); *ddi_descs = &non_hdmi_ddi_descriptors[0]; *ddi_num = ARRAY_SIZE(non_hdmi_ddi_descriptors); -- To view, visit https://review.coreboot.org/c/coreboot/+/81477?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If68303cd59b287c8a5c982063b2ab75fd74898d6 Gerrit-Change-Number: 81477 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-MessageType: merged

1 0

[XS] Change in coreboot[main]: soc/cavium: Remove blank lines before '}' and after '{'
by Elyes Haouas (Code Review) 30 Mar '24

30 Mar '24

Elyes Haouas has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81470?usp=email ) Change subject: soc/cavium: Remove blank lines before '}' and after '{' ...................................................................... soc/cavium: Remove blank lines before '}' and after '{' Change-Id: Id604dc981d6ca0a8163b7477b7916210faa56a77 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81470 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <ericllai(a)google.com> --- M src/soc/cavium/cn81xx/spi.c 1 file changed, 0 insertions(+), 1 deletion(-) Approvals: Eric Lai: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/cavium/cn81xx/spi.c b/src/soc/cavium/cn81xx/spi.c index a3ef567..8faa972 100644 --- a/src/soc/cavium/cn81xx/spi.c +++ b/src/soc/cavium/cn81xx/spi.c @@ -393,7 +393,6 @@ return 0; } static const struct spi_ctrlr spi_ctrlr = { - .xfer_vector = spi_ctrlr_xfer_vector, .max_xfer_size = SPI_CTRLR_DEFAULT_MAX_XFER_SIZE, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/81470?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id604dc981d6ca0a8163b7477b7916210faa56a77 Gerrit-Change-Number: 81470 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-MessageType: merged

1 0

[XS] Change in coreboot[main]: mb/emulation: Remove blank lines before '}' and after '{'
by Elyes Haouas (Code Review) 30 Mar '24

30 Mar '24

Elyes Haouas has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81465?usp=email ) Change subject: mb/emulation: Remove blank lines before '}' and after '{' ...................................................................... mb/emulation: Remove blank lines before '}' and after '{' Change-Id: I7071cbcc26e2080020e83b894cf4ac4ef46913c3 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81465 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <ericllai(a)google.com> --- M src/mainboard/emulation/qemu-power8/mainboard.c M src/mainboard/emulation/qemu-power8/uart.c 2 files changed, 0 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved diff --git a/src/mainboard/emulation/qemu-power8/mainboard.c b/src/mainboard/emulation/qemu-power8/mainboard.c index f1ce497..ed34a57 100644 --- a/src/mainboard/emulation/qemu-power8/mainboard.c +++ b/src/mainboard/emulation/qemu-power8/mainboard.c @@ -5,7 +5,6 @@ static void mainboard_enable(struct device *dev) { - if (!dev) { die("No dev0; die\n"); } diff --git a/src/mainboard/emulation/qemu-power8/uart.c b/src/mainboard/emulation/qemu-power8/uart.c index c9113b4..39f9340 100644 --- a/src/mainboard/emulation/qemu-power8/uart.c +++ b/src/mainboard/emulation/qemu-power8/uart.c @@ -21,7 +21,6 @@ void uart_tx_byte(unsigned int idx, unsigned char data) { - } void uart_tx_flush(unsigned int idx) -- To view, visit https://review.coreboot.org/c/coreboot/+/81465?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7071cbcc26e2080020e83b894cf4ac4ef46913c3 Gerrit-Change-Number: 81465 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-MessageType: merged

1 0

[XS] Change in coreboot[main]: mb/amd: Remove blank lines before '}' and after '{'
by Elyes Haouas (Code Review) 30 Mar '24

30 Mar '24

Elyes Haouas has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81461?usp=email ) Change subject: mb/amd: Remove blank lines before '}' and after '{' ...................................................................... mb/amd: Remove blank lines before '}' and after '{' Change-Id: I2dae34441909f6135b95e7b017659ce4f4666b4e Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81461 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <ericllai(a)google.com> --- M src/mainboard/amd/bilby/mainboard.c M src/mainboard/amd/gardenia/BiosCallOuts.c M src/mainboard/amd/pademelon/BiosCallOuts.c 3 files changed, 0 insertions(+), 3 deletions(-) Approvals: Eric Lai: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/amd/bilby/mainboard.c b/src/mainboard/amd/bilby/mainboard.c index ed4e706..7af66e6 100644 --- a/src/mainboard/amd/bilby/mainboard.c +++ b/src/mainboard/amd/bilby/mainboard.c @@ -66,7 +66,6 @@ else if (port_type == DP) gpio_output(display_sel[idx], 1); } - } static void mainboard_init(void *chip_info) diff --git a/src/mainboard/amd/gardenia/BiosCallOuts.c b/src/mainboard/amd/gardenia/BiosCallOuts.c index 55a915b..0a5105d 100644 --- a/src/mainboard/amd/gardenia/BiosCallOuts.c +++ b/src/mainboard/amd/gardenia/BiosCallOuts.c @@ -6,5 +6,4 @@ void platform_FchParams_env(FCH_DATA_BLOCK *FchParams_env) { - } diff --git a/src/mainboard/amd/pademelon/BiosCallOuts.c b/src/mainboard/amd/pademelon/BiosCallOuts.c index c296285..8afb0f8 100644 --- a/src/mainboard/amd/pademelon/BiosCallOuts.c +++ b/src/mainboard/amd/pademelon/BiosCallOuts.c @@ -4,5 +4,4 @@ void platform_FchParams_env(FCH_DATA_BLOCK *FchParams_env) { - } -- To view, visit https://review.coreboot.org/c/coreboot/+/81461?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2dae34441909f6135b95e7b017659ce4f4666b4e Gerrit-Change-Number: 81461 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[S] Change in coreboot[main]: soc/qualcomm: Remove blank lines before '}' and after '{'
by Elyes Haouas (Code Review) 30 Mar '24

30 Mar '24

Elyes Haouas has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81460?usp=email ) Change subject: soc/qualcomm: Remove blank lines before '}' and after '{' ...................................................................... soc/qualcomm: Remove blank lines before '}' and after '{' Change-Id: If2c2138ed3dc437b924297330805caa8c357853d Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81460 Reviewed-by: Eric Lai <ericllai(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/qualcomm/common/pcie_common.c M src/soc/qualcomm/common/qclib.c M src/soc/qualcomm/ipq40xx/blobs_init.c M src/soc/qualcomm/ipq40xx/qup.c M src/soc/qualcomm/ipq40xx/spi.c M src/soc/qualcomm/ipq806x/spi.c M src/soc/qualcomm/qcs405/clock.c M src/soc/qualcomm/qcs405/qup.c M src/soc/qualcomm/qcs405/soc.c M src/soc/qualcomm/qcs405/spi.c M src/soc/qualcomm/sc7180/display/dsi_phy.c M src/soc/qualcomm/sc7280/display/disp.c M src/soc/qualcomm/sc7280/display/edp_ctrl.c M src/soc/qualcomm/sc7280/socinfo.c 14 files changed, 0 insertions(+), 30 deletions(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved diff --git a/src/soc/qualcomm/common/pcie_common.c b/src/soc/qualcomm/common/pcie_common.c index 9825508..65c2940 100644 --- a/src/soc/qualcomm/common/pcie_common.c +++ b/src/soc/qualcomm/common/pcie_common.c @@ -468,5 +468,4 @@ printk(BIOS_NOTICE, "PCIe enumerated succussfully..\n"); else printk(BIOS_EMERG, "Failed to enable PCIe\n"); - } diff --git a/src/soc/qualcomm/common/qclib.c b/src/soc/qualcomm/common/qclib.c index 56fd3bf..97b6e2d 100644 --- a/src/soc/qualcomm/common/qclib.c +++ b/src/soc/qualcomm/common/qclib.c @@ -124,10 +124,8 @@ static void write_table_entry(struct qclib_cb_if_table_entry *te) { - if (!strncmp(QCLIB_TE_DDR_INFORMATION, te->name, sizeof(te->name))) { - write_ddr_information(te); } else if (!strncmp(QCLIB_TE_DDR_TRAINING_DATA, te->name, @@ -137,13 +135,11 @@ } else if (!strncmp(QCLIB_TE_LIMITS_CFG_DATA, te->name, sizeof(te->name))) { - assert(fmap_overwrite_area(QCLIB_FR_LIMITS_CFG_DATA, (const void *)te->blob_address, te->size)); } else if (!strncmp(QCLIB_TE_QCLIB_LOG_BUFFER, te->name, sizeof(te->name))) { - write_qclib_log_to_cbmemc(te); } else if (!strncmp(QCLIB_TE_MEM_CHIP_INFO, te->name, @@ -151,11 +147,9 @@ write_mem_chip_information(te); } else { - printk(BIOS_WARNING, "%s write not implemented\n", te->name); printk(BIOS_WARNING, " blob_address[%llx]..size[%x]\n", te->blob_address, te->size); - } } diff --git a/src/soc/qualcomm/ipq40xx/blobs_init.c b/src/soc/qualcomm/ipq40xx/blobs_init.c index ef19053..14b37da 100644 --- a/src/soc/qualcomm/ipq40xx/blobs_init.c +++ b/src/soc/qualcomm/ipq40xx/blobs_init.c @@ -113,5 +113,4 @@ printk(BIOS_INFO, "Starting TZBSP\n"); tz_init_wrapper(0, 0, tzbsp); - } diff --git a/src/soc/qualcomm/ipq40xx/qup.c b/src/soc/qualcomm/ipq40xx/qup.c index 88e9169..9627cbe 100644 --- a/src/soc/qualcomm/ipq40xx/qup.c +++ b/src/soc/qualcomm/ipq40xx/qup.c @@ -199,7 +199,6 @@ stopwatch_init_usecs_expire(&timeout, CONFIG_I2C_TRANSFER_TIMEOUT_US); while (data_len) { - tag = qup_i2c_create_output_tag(data_len == 1 && stop_seq, data_ptr[idx]); data_len--; diff --git a/src/soc/qualcomm/ipq40xx/spi.c b/src/soc/qualcomm/ipq40xx/spi.c index ab8f530..cf5c214 100644 --- a/src/soc/qualcomm/ipq40xx/spi.c +++ b/src/soc/qualcomm/ipq40xx/spi.c @@ -74,10 +74,8 @@ */ static int check_qup_state_valid(struct ipq_spi_slave *ds) { - return check_bit_state(ds->regs->qup_state, QUP_STATE_VALID_MASK, QUP_STATE_VALID, 1); - } /* @@ -297,7 +295,6 @@ else clrsetbits32(ds->regs->io_control, SPI_IO_CTRL_FORCE_CS_MSK, SPI_IO_CTRL_FORCE_CS_DIS); - } /* @@ -354,7 +351,6 @@ static void enable_io_config(struct ipq_spi_slave *ds, uint32_t write_cnt, uint32_t read_cnt) { - if (write_cnt) { clrsetbits32(ds->regs->qup_config, QUP_CONF_OUTPUT_MSK, QUP_CONF_OUTPUT_ENA); @@ -370,7 +366,6 @@ clrsetbits32(ds->regs->qup_config, QUP_CONF_INPUT_MSK, QUP_CONF_NO_INPUT); } - } /* @@ -486,7 +481,6 @@ * to get the actual data on the subsequent read cycle that happens */ while (write_len || read_len) { - ret = check_fifo_status(ds->regs->qup_operational); if (ret != SUCCESS) goto out; diff --git a/src/soc/qualcomm/ipq806x/spi.c b/src/soc/qualcomm/ipq806x/spi.c index c538c27..dd478c4 100644 --- a/src/soc/qualcomm/ipq806x/spi.c +++ b/src/soc/qualcomm/ipq806x/spi.c @@ -161,10 +161,8 @@ */ static int check_qup_state_valid(struct ipq_spi_slave *ds) { - return check_bit_state(ds->regs->qup_state, QUP_STATE_VALID_BIT, QUP_STATE_VALID, 1); - } /* diff --git a/src/soc/qualcomm/qcs405/clock.c b/src/soc/qualcomm/qcs405/clock.c index ce84654..a3a41c7 100644 --- a/src/soc/qualcomm/qcs405/clock.c +++ b/src/soc/qualcomm/qcs405/clock.c @@ -144,7 +144,6 @@ static int clock_enable_vote(void *cbcr_addr, void *vote_addr, uint32_t vote_bit) { - /* Set clock vote bit */ setbits32(vote_addr, BIT(vote_bit)); @@ -156,7 +155,6 @@ static int clock_enable(void *cbcr_addr) { - /* Set clock enable bit */ setbits32(cbcr_addr, BIT(CLK_CTL_CBC_CLK_EN_SHFT)); @@ -169,7 +167,6 @@ static int clock_disable(void *cbcr_addr) { - /* Set clock enable bit */ clrbits32(cbcr_addr, BIT(CLK_CTL_CBC_CLK_EN_SHFT)); return 0; @@ -303,7 +300,6 @@ clock_enable(&gcc->blsp2_qup0_spi_apps_cbcr); else printk(BIOS_ERR, "BLSP%d not supported\n", blsp); - } void clock_enable_i2c(void) diff --git a/src/soc/qualcomm/qcs405/qup.c b/src/soc/qualcomm/qcs405/qup.c index e3a4e5e..b5805b0 100644 --- a/src/soc/qualcomm/qcs405/qup.c +++ b/src/soc/qualcomm/qcs405/qup.c @@ -235,7 +235,6 @@ stopwatch_init_usecs_expire(&timeout, CONFIG_I2C_TRANSFER_TIMEOUT_US); while (data_len) { - tag = qup_i2c_create_output_tag(data_len == 1 && stop_seq, data_ptr[idx]); data_len--; diff --git a/src/soc/qualcomm/qcs405/soc.c b/src/soc/qualcomm/qcs405/soc.c index 18bf698..c53cbf2 100644 --- a/src/soc/qualcomm/qcs405/soc.c +++ b/src/soc/qualcomm/qcs405/soc.c @@ -13,7 +13,6 @@ static void soc_init(struct device *dev) { - } static struct device_operations soc_ops = { diff --git a/src/soc/qualcomm/qcs405/spi.c b/src/soc/qualcomm/qcs405/spi.c index 4863188..b263d2f 100644 --- a/src/soc/qualcomm/qcs405/spi.c +++ b/src/soc/qualcomm/qcs405/spi.c @@ -403,7 +403,6 @@ static void enable_io_config(struct qcs_spi_slave *ds, uint32_t write_cnt, uint32_t read_cnt) { - if (write_cnt) { clrsetbits32(ds->regs->qup_config, QUP_CONF_OUTPUT_MSK, QUP_CONF_OUTPUT_ENA); diff --git a/src/soc/qualcomm/sc7180/display/dsi_phy.c b/src/soc/qualcomm/sc7180/display/dsi_phy.c index a43470d..7f26a68 100644 --- a/src/soc/qualcomm/sc7180/display/dsi_phy.c +++ b/src/soc/qualcomm/sc7180/display/dsi_phy.c @@ -483,7 +483,6 @@ /* pll system muxes */ write32(&phy_pll_qlink->pll_system_muxes, reg_val); - } static void dsi_phy_mnd_divider(struct dsi_phy_configtype *phy_cfg) @@ -598,7 +597,6 @@ /* VCO output freq*/ vco_freq_hz = pll_output_freq_hz * pll_post_div; - } return (unsigned long)vco_freq_hz; diff --git a/src/soc/qualcomm/sc7280/display/disp.c b/src/soc/qualcomm/sc7280/display/disp.c index fd3ed3c..bd2259e 100644 --- a/src/soc/qualcomm/sc7280/display/disp.c +++ b/src/soc/qualcomm/sc7280/display/disp.c @@ -58,5 +58,4 @@ /* PPB0 to INTF1 */ write32(&mdp_ctl->ctl_intf_active, INTF_ACTIVE_5); - } diff --git a/src/soc/qualcomm/sc7280/display/edp_ctrl.c b/src/soc/qualcomm/sc7280/display/edp_ctrl.c index 469e1b6..2bf7958 100644 --- a/src/soc/qualcomm/sc7280/display/edp_ctrl.c +++ b/src/soc/qualcomm/sc7280/display/edp_ctrl.c @@ -762,7 +762,6 @@ static int edp_link_lane_down_shift(struct edp_ctrl *ctrl, uint8_t *dpcd) { - if (ctrl->lane_cnt <= 1) return -1; @@ -1275,7 +1274,6 @@ write32(&edp_lclk->active_hor_ver, (edid->mode.ha) | ((edid->mode.va << 16) & 0xffff0000)); - } static void edp_mainlink_ctrl(int enable) diff --git a/src/soc/qualcomm/sc7280/socinfo.c b/src/soc/qualcomm/sc7280/socinfo.c index 8046237..af6901e 100644 --- a/src/soc/qualcomm/sc7280/socinfo.c +++ b/src/soc/qualcomm/sc7280/socinfo.c @@ -80,5 +80,4 @@ return chipinfolut[ret].pro; die("could not match jtagid\n"); - } -- To view, visit https://review.coreboot.org/c/coreboot/+/81460?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If2c2138ed3dc437b924297330805caa8c357853d Gerrit-Change-Number: 81460 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: soc/rockchip: Remove blank lines before '}' and after '{'
by Elyes Haouas (Code Review) 30 Mar '24

30 Mar '24

Elyes Haouas has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81459?usp=email ) Change subject: soc/rockchip: Remove blank lines before '}' and after '{' ...................................................................... soc/rockchip: Remove blank lines before '}' and after '{' Change-Id: I140daa5b862ffd3a5b5468d7cb9dbdd81426855e Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81459 Reviewed-by: Eric Lai <ericllai(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/rockchip/common/edp.c M src/soc/rockchip/common/vop.c M src/soc/rockchip/rk3288/clock.c M src/soc/rockchip/rk3288/sdram.c 4 files changed, 0 insertions(+), 10 deletions(-) Approvals: Eric Lai: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/rockchip/common/edp.c b/src/soc/rockchip/common/edp.c index 422b306..4fbe0d6 100644 --- a/src/soc/rockchip/common/edp.c +++ b/src/soc/rockchip/common/edp.c @@ -147,7 +147,6 @@ } while (!stopwatch_expired(&sw)); return -1; - } static int rk_edp_is_aux_reply(struct rk_edp *edp) @@ -213,7 +212,6 @@ while (length) { len = MIN(length, 16); for (try_times = 0; try_times < 10; try_times++) { - /* Clear AUX CH data buffer */ val = BUF_CLR; write32(&edp->regs->buf_data_ctl, val); @@ -251,7 +249,6 @@ break; else printk(BIOS_WARNING, "read dpcd Aux Transaction fail!\n"); - } if (retval) @@ -629,7 +626,6 @@ return -1; } return 0; - } static int rk_edp_select_i2c_device(struct rk_edp *edp, diff --git a/src/soc/rockchip/common/vop.c b/src/soc/rockchip/common/vop.c index 5674339..b1b76d7 100644 --- a/src/soc/rockchip/common/vop.c +++ b/src/soc/rockchip/common/vop.c @@ -94,7 +94,6 @@ struct rockchip_vop_regs *preg = vop_regs[vop_id]; switch (mode) { - case VOP_MODE_HDMI: clrsetbits32(&preg->sys_ctrl, M_ALL_OUT_EN, V_HDMI_OUT_EN(1)); diff --git a/src/soc/rockchip/rk3288/clock.c b/src/soc/rockchip/rk3288/clock.c index 5b1350a..c3a9ac2 100644 --- a/src/soc/rockchip/rk3288/clock.c +++ b/src/soc/rockchip/rk3288/clock.c @@ -304,7 +304,6 @@ write32(&cru_ptr->cru_mode_con, RK_CLRSETBITS(GPLL_MODE_MSK, GPLL_MODE_NORM) | RK_CLRSETBITS(CPLL_MODE_MSK, CPLL_MODE_NORM)); - } void rkclk_configure_cpu(enum apll_frequencies apll_freq) @@ -665,5 +664,4 @@ default: return -1; /* Should never happen. */ } - } diff --git a/src/soc/rockchip/rk3288/sdram.c b/src/soc/rockchip/rk3288/sdram.c index 2efe19b..0237ca2 100644 --- a/src/soc/rockchip/rk3288/sdram.c +++ b/src/soc/rockchip/rk3288/sdram.c @@ -683,7 +683,6 @@ for (i = 0; i < 4; i++) clrbits32(&ddr_publ_regs->datx8[i].dxgcr, DQSRTT | DQRTT); - } } @@ -798,7 +797,6 @@ DXDLLCR_DLLSRST); } setbits32(&ddr_pctl_regs->dfistcfg0, 1 << 2); - } static int data_training(u32 channel, @@ -1074,7 +1072,6 @@ u32 ch; if (!size_mb) { - u32 sys_reg = read32(&rk3288_pmu->sys_reg[2]); u32 ch_num = SYS_REG_DEC_NUM_CH(sys_reg); -- To view, visit https://review.coreboot.org/c/coreboot/+/81459?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I140daa5b862ffd3a5b5468d7cb9dbdd81426855e Gerrit-Change-Number: 81459 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: soc/amd: Remove blank lines before '}' and after '{'
by Elyes Haouas (Code Review) 30 Mar '24

30 Mar '24

Elyes Haouas has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81457?usp=email ) Change subject: soc/amd: Remove blank lines before '}' and after '{' ...................................................................... soc/amd: Remove blank lines before '}' and after '{' Change-Id: I0203e77dd23fa026cd252abbda50f1e9f6892721 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81457 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <ericllai(a)google.com> --- M src/soc/amd/common/block/acpi/ivrs.c M src/soc/amd/common/block/lpc/espi_util.c M src/soc/amd/common/fsp/dmi.c M src/soc/amd/common/pi/agesawrapper.c M src/soc/amd/common/pi/heapmanager.c M src/soc/amd/genoa_poc/early_fch.c M src/soc/amd/glinda/psp_verstage/svc.c M src/soc/amd/mendocino/fsp_s_params.c M src/soc/amd/mendocino/psp_verstage/svc.c M src/soc/amd/phoenix/psp_verstage/svc.c M src/soc/amd/picasso/acpi_crat.c 11 files changed, 0 insertions(+), 15 deletions(-) Approvals: Eric Lai: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/amd/common/block/acpi/ivrs.c b/src/soc/amd/common/block/acpi/ivrs.c index 74c5c39..a2f7715 100644 --- a/src/soc/amd/common/block/acpi/ivrs.c +++ b/src/soc/amd/common/block/acpi/ivrs.c @@ -131,7 +131,6 @@ } else if ((header_type == PCI_HEADER_TYPE_NORMAL) && !is_pcie) { /* Device is legacy PCI or PCI-X */ add_ivhd_dev_entry(parent, dev, current, IVHD_DEV_8_BYTE_ALIAS_SELECT, 0x0); - } } @@ -316,7 +315,6 @@ ivhd = &ivrs->ivhd; while ((dev = dev_find_path(dev, DEVICE_PATH_DOMAIN)) != NULL) { - nb_dev = pcidev_path_behind(dev->downstream, PCI_DEVFN(0, 0)); iommu_dev = pcidev_path_behind(dev->downstream, PCI_DEVFN(0, 2)); if (!nb_dev) { diff --git a/src/soc/amd/common/block/lpc/espi_util.c b/src/soc/amd/common/block/lpc/espi_util.c index c0f2354..f05575a 100644 --- a/src/soc/amd/common/block/lpc/espi_util.c +++ b/src/soc/amd/common/block/lpc/espi_util.c @@ -317,7 +317,6 @@ } return -1; - } static size_t espi_get_mmio_window_size(int idx) @@ -824,7 +823,6 @@ printk(BIOS_ERR, "Channel is not ready after %d usec (slave addr: 0x%x)\n", ESPI_CH_READY_TIMEOUT_US, slave_reg_addr); return CB_ERR; - } static void espi_enable_ctrlr_channel(uint32_t channel_en) diff --git a/src/soc/amd/common/fsp/dmi.c b/src/soc/amd/common/fsp/dmi.c index d0d9873..d132590 100644 --- a/src/soc/amd/common/fsp/dmi.c +++ b/src/soc/amd/common/fsp/dmi.c @@ -23,7 +23,6 @@ */ static uint16_t ddr_speed_mhz_to_reported_mts(uint16_t ddr_type, uint16_t speed) { - if (CONFIG(USE_DDR4) && ddr_type == MEMORY_TYPE_DDR4) return ddr4_speed_mhz_to_reported_mts(speed); else if (CONFIG(USE_LPDDR4) && ddr_type == MEMORY_TYPE_LPDDR4) diff --git a/src/soc/amd/common/pi/agesawrapper.c b/src/soc/amd/common/pi/agesawrapper.c index beae4ba..8ad1e0e 100644 --- a/src/soc/amd/common/pi/agesawrapper.c +++ b/src/soc/amd/common/pi/agesawrapper.c @@ -387,7 +387,6 @@ default: return AGESA_UNSUPPORTED; } - } AGESA_STATUS agesa_execute_state(AGESA_STRUCT_NAME func) diff --git a/src/soc/amd/common/pi/heapmanager.c b/src/soc/amd/common/pi/heapmanager.c index 154f04d..34a4837 100644 --- a/src/soc/amd/common/pi/heapmanager.c +++ b/src/soc/amd/common/pi/heapmanager.c @@ -236,7 +236,6 @@ * betterfit than the previous nodes */ if (BestFitNodeSize > FreedNodeSize) { - BestFitNodeOffset = FreedNodeOffset; BestFitPrevNodeOffset = @@ -308,7 +307,6 @@ AGESA_STATUS agesa_DeallocateBuffer(uint32_t Func, uintptr_t Data, void *ConfigPtr) { - uint8_t *BiosHeapBaseAddr; uint32_t AllocNodeOffset; uint32_t PrevNodeOffset; @@ -436,5 +434,4 @@ } return Status; - } diff --git a/src/soc/amd/genoa_poc/early_fch.c b/src/soc/amd/genoa_poc/early_fch.c index e134f49..d82ebcb 100644 --- a/src/soc/amd/genoa_poc/early_fch.c +++ b/src/soc/amd/genoa_poc/early_fch.c @@ -30,5 +30,4 @@ /* After console init */ void fch_early_init(void) { - } diff --git a/src/soc/amd/glinda/psp_verstage/svc.c b/src/soc/amd/glinda/psp_verstage/svc.c index 293bf46..d533d8f 100644 --- a/src/soc/amd/glinda/psp_verstage/svc.c +++ b/src/soc/amd/glinda/psp_verstage/svc.c @@ -183,7 +183,6 @@ }; SVC_CALL2(SVC_VERSTAGE_CMD, CMD_MODEXP, (void *)&param, retval); return retval; - } uint32_t svc_ccp_dma(uint32_t spi_rom_offset, void *dest, uint32_t size) diff --git a/src/soc/amd/mendocino/fsp_s_params.c b/src/soc/amd/mendocino/fsp_s_params.c index e1eff32..8374fb3 100644 --- a/src/soc/amd/mendocino/fsp_s_params.c +++ b/src/soc/amd/mendocino/fsp_s_params.c @@ -19,7 +19,6 @@ scfg->vbios_buffer = 0; printk(BIOS_SPEW, "%s: using VBIOS cache; skipping GOP driver.\n", __func__); return; - } printk(BIOS_SPEW, "%s: not using VBIOS cache; running GOP driver.\n", __func__); scfg->vbios_buffer = CONFIG(RUN_FSP_GOP) ? PCI_VGA_RAM_IMAGE_START : 0; diff --git a/src/soc/amd/mendocino/psp_verstage/svc.c b/src/soc/amd/mendocino/psp_verstage/svc.c index 53d1751..0c6fb5e 100644 --- a/src/soc/amd/mendocino/psp_verstage/svc.c +++ b/src/soc/amd/mendocino/psp_verstage/svc.c @@ -191,7 +191,6 @@ }; SVC_CALL2(SVC_VERSTAGE_CMD, CMD_MODEXP, (void *)&param, retval); return retval; - } uint32_t svc_ccp_dma(uint32_t spi_rom_offset, void *dest, uint32_t size) diff --git a/src/soc/amd/phoenix/psp_verstage/svc.c b/src/soc/amd/phoenix/psp_verstage/svc.c index 45d18c1..6f08678 100644 --- a/src/soc/amd/phoenix/psp_verstage/svc.c +++ b/src/soc/amd/phoenix/psp_verstage/svc.c @@ -181,7 +181,6 @@ }; SVC_CALL2(SVC_VERSTAGE_CMD, CMD_MODEXP, (void *)&param, retval); return retval; - } uint32_t svc_ccp_dma(uint32_t spi_rom_offset, void *dest, uint32_t size) diff --git a/src/soc/amd/picasso/acpi_crat.c b/src/soc/amd/picasso/acpi_crat.c index e528515..bcc3901 100644 --- a/src/soc/amd/picasso/acpi_crat.c +++ b/src/soc/amd/picasso/acpi_crat.c @@ -372,7 +372,6 @@ new_entries = 0; for (thread = 0; thread < total_num_threads; thread++) { - /* L1 data TLB */ if (thread % num_threads_sharing0 == 0) { current = add_crat_tlb_entry(&tlb_affinity, current); -- To view, visit https://review.coreboot.org/c/coreboot/+/81457?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0203e77dd23fa026cd252abbda50f1e9f6892721 Gerrit-Change-Number: 81457 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-MessageType: merged

1 0

[XS] Change in coreboot[main]: acpi: Remove blank lines before '}' and after '{'
by Elyes Haouas (Code Review) 30 Mar '24

30 Mar '24

Elyes Haouas has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81452?usp=email ) Change subject: acpi: Remove blank lines before '}' and after '{' ...................................................................... acpi: Remove blank lines before '}' and after '{' Change-Id: I9ba061fe0b1396ccc1597e26685a6b4e312e3549 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81452 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <ericllai(a)google.com> --- M src/acpi/acpi.c M src/acpi/acpigen.c M src/acpi/device.c M src/acpi/gnvs.c 4 files changed, 0 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index 30a07bf..c33d195 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -1506,7 +1506,6 @@ */ for (int i = 0; existing_rsdt->entry[i]; i++) acpi_add_table(rsdp, (void *)(uintptr_t)existing_rsdt->entry[i]); - } /* Add BOOT0000 for Linux google firmware driver */ diff --git a/src/acpi/acpigen.c b/src/acpi/acpigen.c index 257bd52..9c04e84 100644 --- a/src/acpi/acpigen.c +++ b/src/acpi/acpigen.c @@ -1880,7 +1880,6 @@ acpigen_write_return_singleton_buffer(0x0); acpigen_write_if_end(); /* If (LEqual (Local0, ToUUID(uuid))) */ - } /* diff --git a/src/acpi/device.c b/src/acpi/device.c index 368b86c..7fe5a37 100644 --- a/src/acpi/device.c +++ b/src/acpi/device.c @@ -1158,7 +1158,6 @@ acpi_dp_add_array(dp, gpio); return gpio; - } diff --git a/src/acpi/gnvs.c b/src/acpi/gnvs.c index 827cd2d..1e5d746 100644 --- a/src/acpi/gnvs.c +++ b/src/acpi/gnvs.c @@ -30,7 +30,6 @@ if (dnvs_size) dnvs = (char *)gnvs + gnvs_size; - } BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_EXIT, acpi_create_gnvs, NULL); -- To view, visit https://review.coreboot.org/c/coreboot/+/81452?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9ba061fe0b1396ccc1597e26685a6b4e312e3549 Gerrit-Change-Number: 81452 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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