coreboot-gerrit February 2024

coreboot-gerrit@coreboot.org

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[XS] Change in coreboot[main]: geralt: Enable CROS_WIDEVINE_SMC
by Yidi Lin (Code Review) 06 Feb '24

06 Feb '24

Attention is currently required from: Hung-Te Lin, Yi Chou. Yidi Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80315?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: geralt: Enable CROS_WIDEVINE_SMC ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/80315/comment/f63a5d79_876b77d7 : PS1, Line 7: geralt soc/mediatek/mt8188 -- To view, visit https://review.coreboot.org/c/coreboot/+/80315?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3dded9042abd85a948598f98475c21a1af9b4d80 Gerrit-Change-Number: 80315 Gerrit-PatchSet: 1 Gerrit-Owner: Yi Chou <yich(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yi Chou <yich(a)google.com> Gerrit-Comment-Date: Tue, 06 Feb 2024 09:15:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Drop code to locate the UBOX bus
by Shuo Liu (Code Review) 06 Feb '24

06 Feb '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Lean Sheng Tan, Patrick Rudolph, Tim Chu. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80102?usp=email ) Change subject: soc/intel/xeon_sp: Drop code to locate the UBOX bus ...................................................................... Patch Set 9: (2 comments) File src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h: https://review.coreboot.org/c/coreboot/+/80102/comment/9969248c_6338096d : PS9, Line 27: uint8_t get_stack_busno(const uint8_t stack); > optional to have wording fixes here or leave to later discussions. close the open. Done File src/soc/intel/xeon_sp/util.c: https://review.coreboot.org/c/coreboot/+/80102/comment/10860842_188ad914 : PS9, Line 27: > optional to have wording fixes here or leave to later discussions. close the open. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/80102?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2b18f02f62b69ec7c73cd5665102cb6bfc6e64b5 Gerrit-Change-Number: 80102 Gerrit-PatchSet: 9 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Tue, 06 Feb 2024 09:14:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Drop code to locate the UBOX bus
by Shuo Liu (Code Review) 06 Feb '24

06 Feb '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Lean Sheng Tan, Patrick Rudolph, Tim Chu. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80102?usp=email ) Change subject: soc/intel/xeon_sp: Drop code to locate the UBOX bus ...................................................................... Patch Set 9: (2 comments) File src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h: https://review.coreboot.org/c/coreboot/+/80102/comment/3803318b_43eed15a : PS9, Line 27: uint8_t get_stack_busno(const uint8_t stack); > the wording 'stack' might be confused, can we use below instead? […] optional to have wording fixes here or leave to later discussions. close the open. File src/soc/intel/xeon_sp/util.c: https://review.coreboot.org/c/coreboot/+/80102/comment/b27c581b_28218c28 : PS9, Line 27: > The words STACK is confusing, can we use UNCORE_BUS_1 directly? or UNCORE_PCU instead? optional to have wording fixes here or leave to later discussions. close the open. -- To view, visit https://review.coreboot.org/c/coreboot/+/80102?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2b18f02f62b69ec7c73cd5665102cb6bfc6e64b5 Gerrit-Change-Number: 80102 Gerrit-PatchSet: 9 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Tue, 06 Feb 2024 09:14:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Drop code to locate the UBOX bus
by Shuo Liu (Code Review) 06 Feb '24

06 Feb '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Lean Sheng Tan, Patrick Rudolph, Tim Chu. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80102?usp=email ) Change subject: soc/intel/xeon_sp: Drop code to locate the UBOX bus ...................................................................... Patch Set 9: Code-Review+1 (1 comment) File src/soc/intel/xeon_sp/spr/soc_util.c: https://review.coreboot.org/c/coreboot/+/80102/comment/6bd039e0_1d60b631 : PS9, Line 142: uint32_t get_ubox_busno(uint32_t socket, uint8_t offset) > It cannot be used on multi PCI segment groups since bus numbers are duplicated. […] I see, thanks. -- To view, visit https://review.coreboot.org/c/coreboot/+/80102?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2b18f02f62b69ec7c73cd5665102cb6bfc6e64b5 Gerrit-Change-Number: 80102 Gerrit-PatchSet: 9 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Tue, 06 Feb 2024 09:13:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: geralt: Enable CROS_WIDEVINE_SMC
by Yu-Ping Wu (Code Review) 06 Feb '24

06 Feb '24

Attention is currently required from: Hung-Te Lin, Yi Chou, Yidi Lin. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80315?usp=email ) Change subject: geralt: Enable CROS_WIDEVINE_SMC ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/80315?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3dded9042abd85a948598f98475c21a1af9b4d80 Gerrit-Change-Number: 80315 Gerrit-PatchSet: 1 Gerrit-Owner: Yi Chou <yich(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yi Chou <yich(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Tue, 06 Feb 2024 09:08:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: cpu/x86: Add 1GiB pages for memory access up to 512GiB
by Ashish Kumar Mishra (Code Review) 06 Feb '24

06 Feb '24

Attention is currently required from: Arthur Heymans, Jérémy Compostella, Paul Menzel, Subrata Banik, Wonkyu Kim. Ashish Kumar Mishra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80088?usp=email ) Change subject: cpu/x86: Add 1GiB pages for memory access up to 512GiB ...................................................................... Patch Set 9: (1 comment) File src/cpu/x86/64bit/pt1G.S: https://review.coreboot.org/c/coreboot/+/80088/comment/a2986a76_6dcdc360 : PS8, Line 28: PDE_tables > no 's' at the end. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/80088?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id569ae5b50abf5b72e4db33b5e4cd802399e76ec Gerrit-Change-Number: 80088 Gerrit-PatchSet: 9 Gerrit-Owner: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Tue, 06 Feb 2024 08:55:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: arch/arm64/armv8: Add exception output without printk
by Maximilian Brune (Code Review) 06 Feb '24

06 Feb '24

Attention is currently required from: Arthur Heymans, Benjamin Doron, David Milosevic, Julius Werner. Maximilian Brune has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80184?usp=email ) Change subject: arch/arm64/armv8: Add exception output without printk ...................................................................... Patch Set 3: (1 comment) File src/arch/arm64/armv8/exception.c: https://review.coreboot.org/c/coreboot/+/80184/comment/ce5811da_6f62694d : PS1, Line 113: if (idx < 10) : __uart_tx_byte('0' + (char)idx); : else if (idx < 16) : __uart_tx_byte('A' - 10 + (char)idx); : __uart_tx_byte('!'); : UART_DIRECT_PRINT(raw_read_esr(), 32) : __uart_tx_byte('!'); > Yeah, honestly, I feel like outputting the arguments is a bit much. […] Sounds good. But I will have to write it like this (even if it is taking a bit more space): ``` __uart_tx_byte('\r'); __uart_tx_byte('\n'); __uart_tx_byte('!'); __uart_tx_byte('E'); __uart_tx_byte('X'); __uart_tx_byte('C'); __uart_tx_byte('E'); __uart_tx_byte('P'); __uart_tx_byte('T'); __uart_tx_byte('!'); ``` The reason is the following: The issue that I hit was linking the bootblock at the wrong memory address (in memlayout.ld). During that time quite some stuff worked fine. But printk didn't work and my only clue was the `__uart_tx_byte` output. The reason why printk didn't work and that is also why this code didn't work: ``` const char *msg = "\r\n!EXCPT!"; while (*msg) __uart_tx_byte(*msg++); ``` is that the compiler will reference `msg` variable using an address relative to where I linked the bootblock. If I on the other hand write all the `__uart_tx_byte` seperate than the compiler doesn't need to access something using a memory address, but only needs to write a single byte character in a register as argument to `__uart_tx_byte`. I hope my explanation was good enough. I added an explanation into the commit-msg in case someone tries to update this code in the future and wonders why it was written this way. -- To view, visit https://review.coreboot.org/c/coreboot/+/80184?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2f858730469fff3cae120fd7c32fec53b3d309ca Gerrit-Change-Number: 80184 Gerrit-PatchSet: 3 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Comment-Date: Tue, 06 Feb 2024 08:51:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: arch/arm64/armv8: Add exception output without printk
by Maximilian Brune (Code Review) 06 Feb '24

06 Feb '24

Attention is currently required from: Arthur Heymans, Benjamin Doron, David Milosevic, Maximilian Brune. Hello Arthur Heymans, Benjamin Doron, David Milosevic, Julius Werner, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/80184?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: arch/arm64/armv8: Add exception output without printk ...................................................................... arch/arm64/armv8: Add exception output without printk In case printk does not work the current exception handler will print a simple "!" to notify the developer that coreboot is actually there but something went wrong. The "!" can be quite confusing when it actually happens that printk does not work. Since "!" doesn't really say much (if you don't know the exception arm64 code) the developer (like me) can easily assume that something went wrong while configuring clocks or baud rate of UART, since the output seemingly does not seem to make sense. This adds a little bit more output to assure the developer that what was printed was actually intended to be printed. Therefore it prints "EXCEPT" which assures the developer that this was intended output. It also adds a comment above so that developer can more easily grep for this message. It has intentionally not been written as: ``` const char *msg = "\r\n!EXCPT!"; while (*msg) __uart_tx_byte(*msg++); ``` because in this case the compiler will generate code that will place `msg` somewhere in bootblock and the code will try to access this using a memory address. In rare cases (if you link bootblock at the wrong address) this memory address can be wrong and coreboot will not print the message. Using individual calls to `__uart_tx_byte` ensures that the compiler will generate code which directly puts the character bytes into the argument register without referencing a variable in bootblock. Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> Change-Id: I2f858730469fff3cae120fd7c32fec53b3d309ca --- M src/arch/arm64/armv8/exception.c 1 file changed, 12 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/80184/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/80184?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2f858730469fff3cae120fd7c32fec53b3d309ca Gerrit-Change-Number: 80184 Gerrit-PatchSet: 3 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: cpu/x86: Add 1GiB pages for memory access up to 512GiB
by Ashish Kumar Mishra (Code Review) 06 Feb '24

06 Feb '24

Attention is currently required from: Ashish Kumar Mishra, Jérémy Compostella, Paul Menzel, Subrata Banik, Wonkyu Kim. Hello Arthur Heymans, Jérémy Compostella, Subrata Banik, Wonkyu Kim, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/80088?usp=email to look at the new patch set (#9). Change subject: cpu/x86: Add 1GiB pages for memory access up to 512GiB ...................................................................... cpu/x86: Add 1GiB pages for memory access up to 512GiB Current pagetable implementation allows memory access up to 4GiB using 2MiB pages. If user wants to access more than 4GiB with a 2MiB page it will require more pagetable entries. By using a 1GiB page table, users can access more than 4GiB of memory while reducing the number of pagetable entries. This patch enables memory access up to 512GiB through 1GiB pages by selecting USE_1G_PAGES_TLB in Kconfig. TEST: Verified in 64bit mode boot and access above 4GiB Change-Id: Id569ae5b50abf5b72e4db33b5e4cd802399e76ec Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> --- M src/cpu/x86/64bit/Makefile.mk A src/cpu/x86/64bit/pt1G.S M src/cpu/x86/Kconfig 3 files changed, 43 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/80088/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/80088?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id569ae5b50abf5b72e4db33b5e4cd802399e76ec Gerrit-Change-Number: 80088 Gerrit-PatchSet: 9 Gerrit-Owner: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: mb/amd/birman: Add Birmanplus board variant related configs
by Anand Vaikar (Code Review) 06 Feb '24

06 Feb '24

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk. Hello Felix Held, Fred Reitberger, Jason Glenesk, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/80351?usp=email to look at the new patch set (#3). Change subject: mb/amd/birman: Add Birmanplus board variant related configs ...................................................................... mb/amd/birman: Add Birmanplus board variant related configs Initial commit for upstreaming Birmanplus mainboard changes. Change-Id: I075dcf0214f8dc8b33b0e429d83d270b2f0952e1 Signed-off-by: Anand Vaikar <a.vaikar2021(a)gmail.com> --- M src/mainboard/amd/birman/Kconfig M src/mainboard/amd/birman/Kconfig.name 2 files changed, 12 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/80351/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/80351?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I075dcf0214f8dc8b33b0e429d83d270b2f0952e1 Gerrit-Change-Number: 80351 Gerrit-PatchSet: 3 Gerrit-Owner: Anand Vaikar <a.vaikar2021(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-CC: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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coreboot-gerrit February 2024