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Change subject: mb/google/nissa/var/anraggar: Skip locking for GPP_F15 GPIO
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
Anraggar follow the same design as nissa reference, the issue is not Anragger unique. would it be better to make the change to the baseboard?
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Hello Angel Pons, Arthur Heymans, Benjamin Doron, Christian Walter, Lean Sheng Tan, Patrick Rudolph, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: mb/emulation: Add SIMICS QSP support
......................................................................
mb/emulation: Add SIMICS QSP support
SIMICS Quick Start Platform (QSP) is weird. It doesn't implement a single X58 register
besides DEVID/VENID. Likely because those are never used by an OS.
As it is a slimmed-down entry-level platform, it is not so suitable for developing complex firmware.
ICH10 seems to be more properly implemented.
Working:
- Boots to EDK2 payload (payloads/external/edk2)
- TSEG works, ASEG is broken
- Graphics init works
Signed-off-by: Leon Gross <leon.gross(a)9elements.com>
Change-Id: I175b20bb4746608e4d868aa96492fc06c149bd36
---
A Documentation/mainboard/emulation/simics-qsp.md
M src/cpu/qemu-x86/Kconfig
A src/mainboard/emulation/simics-qsp/Kconfig
A src/mainboard/emulation/simics-qsp/Kconfig.name
A src/mainboard/emulation/simics-qsp/Makefile.inc
A src/mainboard/emulation/simics-qsp/acpi.h
A src/mainboard/emulation/simics-qsp/acpi_tables.c
A src/mainboard/emulation/simics-qsp/board_info.txt
A src/mainboard/emulation/simics-qsp/bootblock.c
A src/mainboard/emulation/simics-qsp/cmos.default
A src/mainboard/emulation/simics-qsp/cmos.layout
A src/mainboard/emulation/simics-qsp/cpu.c
A src/mainboard/emulation/simics-qsp/devicetree.cb
A src/mainboard/emulation/simics-qsp/dsdt.asl
A src/mainboard/emulation/simics-qsp/exit_car.S
A src/mainboard/emulation/simics-qsp/hda_verb.c
A src/mainboard/emulation/simics-qsp/mainboard.c
A src/mainboard/emulation/simics-qsp/memmap.c
A src/mainboard/emulation/simics-qsp/memory.h
A src/mainboard/emulation/simics-qsp/northbridge.c
A src/mainboard/emulation/simics-qsp/romstage.c
A src/mainboard/emulation/simics-qsp/vboot-rwa-16M.fmd
A src/mainboard/emulation/simics-qsp/vboot-rwab-16M.fmd
M src/southbridge/intel/i82801jx/Kconfig
24 files changed, 1,230 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/77905/18
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Change subject: mb/google/nissa/var/anraggar: Skip locking for GPP_F15 GPIO
......................................................................
Patch Set 1:
(1 comment)
File src/mainboard/google/brya/variants/anraggar/gpio.c:
https://review.coreboot.org/c/coreboot/+/80316/comment/27d48967_a8c6386b :
PS1, Line 54: PLTRST
@Eric PLTRST or others, could you give some suggestion?
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Change subject: drivers/smmstore: Add support for virtual CPUs
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
No longer needed once CB:79738 is merged
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Change subject: libpayload/libc/time: Fix possible overflow in multiplication
......................................................................
Patch Set 11:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/78888/comment/200ae047_5c21d467 :
PS11, Line 15: counter should never be that fast.
> Wouldn't that mean that we'd have broken things with the `assert(UINT32_MAX / 1000 >= lib_sysinfo. […]
Sorry, forgot to mention, Paul ran into the assertion.
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Change subject: soc/mediatek/mt8188: Enable CROS_WIDEVINE_SMC
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/80315/comment/303470e8_e14ec19a :
PS1, Line 7: geralt
> soc/mediatek/mt8188
Done
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Change subject: soc/mediatek/mt8188: Enable CROS_WIDEVINE_SMC
......................................................................
soc/mediatek/mt8188: Enable CROS_WIDEVINE_SMC
BUG=b:248612503
TEST=Test with crrev.com/c/4756330
BRANCH=none
Signed-off-by: Yi Chou <yich(a)google.com>
Change-Id: I3dded9042abd85a948598f98475c21a1af9b4d80
---
M src/soc/mediatek/mt8188/Makefile.mk
1 file changed, 1 insertion(+), 0 deletions(-)
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Change subject: mb/google/nissa/var/anraggar: Skip locking for GPP_F15 GPIO
......................................................................
mb/google/nissa/var/anraggar: Skip locking for GPP_F15 GPIO
There is an existing issue for Anraggar where wake up from
RTC wake is not working during suspend_stress_test.
The phenomenon of the issue is that after pulling out the
stylus, can see an interrupt storm occurs through
"cat /proc/interrupts | grep acpi".
When the counter of interrupts is greater than a certain
value, "Disabling IRQ #9" will occur, so RTC wake is not
working.
Reference: https://review.coreboot.org/c/coreboot/+/65086
This patch skips the locking for GPP_F15 to allow kernel to
configure it later. The interrupt storm of acpi dispeared.
BUG=b:321348117
TEST=cat /proc/interrupts | grep acpi
There isn't interrupt storm of acpi when pulling out stylus.
Pass suspend_stress_test -c 2500 --suspend_min=15 --suspend_max=20
Change-Id: Ie143c43e0555d17d8a290f17637b537fba806144
Signed-off-by: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com>
---
M src/mainboard/google/brya/variants/anraggar/gpio.c
1 file changed, 2 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/80316/1
diff --git a/src/mainboard/google/brya/variants/anraggar/gpio.c b/src/mainboard/google/brya/variants/anraggar/gpio.c
index 8bc3f6b..0bd13b6 100644
--- a/src/mainboard/google/brya/variants/anraggar/gpio.c
+++ b/src/mainboard/google/brya/variants/anraggar/gpio.c
@@ -50,6 +50,8 @@
PAD_CFG_GPO_LOCK(GPP_F11, 1, LOCK_CONFIG),
/* F12 : GSXDOUT ==> WWAN_RST_L */
PAD_CFG_GPO_LOCK(GPP_F12, 1, LOCK_CONFIG),
+ /* F15 : GSXSRESET# ==> SOC_PEN_DETECT_ODL */
+ PAD_CFG_GPI_SCI_HIGH(GPP_F15, NONE, PLTRST, EDGE_SINGLE),
/* F18 : THC1_SPI2_INT# ==> EN_PP2800_AFVDD */
PAD_CFG_GPO(GPP_F18, 0, DEEP),
/* F23 : V1P05_CTRL ==> NC*/
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Change subject: geralt: Enable CROS_WIDEVINE_SMC
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/80315/comment/f63a5d79_876b77d7 :
PS1, Line 7: geralt
soc/mediatek/mt8188
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