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Change subject: cpu/x86/smm: Set up page tables in safe SMRAM
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
> Okay, this approach is simpler than CB:79865.
That patch train has some more sophisticated code to generate page tables in both ramstage and smm. I like it better, as it seems better suited to use NX. Maybe this simple approach could be merged first and then revisited when the mmu runtime code is ready?
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Change subject: cpu/x86: Add 1GiB pages for memory access up to 512GiB
......................................................................
Patch Set 7:
(3 comments)
File src/cpu/x86/64bit/pt1G.S:
https://review.coreboot.org/c/coreboot/+/80088/comment/db728e36_215e8503 :
PS7, Line 21: 32
actually this needs to be 4096 too. The lower 12 bits of cr0 are not be used.
https://review.coreboot.org/c/coreboot/+/80088/comment/2de5593b_4f64ee6e :
PS7, Line 27: 512
I some size constrained cases a different number is nice. I suppose making this configurable could be done in a follow-up.
File src/cpu/x86/Kconfig:
https://review.coreboot.org/c/coreboot/+/80088/comment/d082bd66_b1ca58e1 :
PS7, Line 158: pages
add a '.' at the end.
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Change subject: mb/google/brya/var/xol: Update memory configuration
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Patch Set 5:
This change is ready for review.
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Change subject: Update arm-trusted-firmware submodule to upstream master
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Patch Set 1: Code-Review+2
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Hello Felix Held, Fred Reitberger, Jason Glenesk,
I'd like you to reexamine a change. Please visit
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Change subject: mb/amd/birman: Add Birmanplus board variant related configs
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mb/amd/birman: Add Birmanplus board variant related configs
Initial commit for upstreaming Birmanplus mainboard changes.
Change-Id: I075dcf0214f8dc8b33b0e429d83d270b2f0952e1
Signed-off-by: Anand Vaikar <a.vaikar2021(a)gmail.com>
---
M src/mainboard/amd/birman/Kconfig
M src/mainboard/amd/birman/Kconfig.name
2 files changed, 12 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/80351/2
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Change subject: mb/google/brox: Initialize TCHSCR_RST_L/EN_PP3300_TCHSCR to 0
......................................................................
Patch Set 2:
(1 comment)
File src/mainboard/google/brox/variants/baseboard/brox/gpio.c:
https://review.coreboot.org/c/coreboot/+/80300/comment/a39e62a1_08c8ffbd :
PS2, Line 247: PAD_CFG_GPO(GPP_F7, 1, PLTRST),
I think the problem is you should change to DEEP for the power control pin.
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Change subject: mb/google/brya/var/xol: Update Kconfig and devicetree
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Patch Set 6: Code-Review+2
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