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Change subject: mb/google/nissa/var/yaviks: Enable USE_MTCL for YAVIKS
......................................................................
Patch Set 3: Code-Review+2
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Change subject: mb/google/nissa/var/anraggar: Config DP AUX BIAS according to fw_config
......................................................................
Patch Set 10:
(1 comment)
File src/mainboard/google/brya/variants/anraggar/variant.c:
https://review.coreboot.org/c/coreboot/+/80259/comment/8a3088d2_3e8b6f52 :
PS10, Line 32: 0
> Yes, for Anraggar project, TCP0(C0) is connected to DB, TCP1(C1) is connected to MB.
Two questions:
1. Why config for C1 (MB) is changed in the above code.
```
config->typec_aux_bias_pads[1].pad_auxp_dc = GPP_E22;
config->typec_aux_bias_pads[1].pad_auxn_dc = GPP_E23;
```
2. There is no `else` case for REDRIVER (vs SOC).
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Change subject: arch/riscv: Add OPENSBI_FW_DYNAMIC_BOOT_HART option
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Patch Set 2: Code-Review+2
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Change subject: cpu/x86: Add 1GiB pages for memory access up to 512GiB
......................................................................
Patch Set 7:
(2 comments)
File src/cpu/x86/64bit/pt1G.S:
https://review.coreboot.org/c/coreboot/+/80088/comment/3fb3dbb0_df3a27ed :
PS7, Line 21: 32
> actually this needs to be 4096 too. The lower 12 bits of cr0 are not be used.
Done
File src/cpu/x86/Kconfig:
https://review.coreboot.org/c/coreboot/+/80088/comment/32142347_7a587b8d :
PS7, Line 158: pages
> add a '.' at the end.
Done
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Hello Arthur Heymans, Jérémy Compostella, Subrata Banik, Wonkyu Kim, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: cpu/x86: Add 1GiB pages for memory access up to 512GiB
......................................................................
cpu/x86: Add 1GiB pages for memory access up to 512GiB
Current pagetable implementation allows memory access up to 4GiB using
2MiB pages. If user wants to access more than 4GiB with a 2MiB page it
will require more pagetable entries. By using a 1GiB page table, users
can access more than 4GiB of memory while reducing the number of
pagetable entries. This patch enables memory access up to 512GiB through
1GiB pages by selecting USE_1G_PAGES_TLB in Kconfig.
TEST: Verified in 64bit mode boot and access above 4GiB
Change-Id: Id569ae5b50abf5b72e4db33b5e4cd802399e76ec
Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com>
---
M src/cpu/x86/64bit/Makefile.mk
A src/cpu/x86/64bit/pt1G.S
M src/cpu/x86/Kconfig
3 files changed, 43 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/80088/8
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Change subject: cpu/x86: Support runtime page tables on APs
......................................................................
Patch Set 1:
(1 comment)
File src/cpu/x86/mp_init.c:
https://review.coreboot.org/c/coreboot/+/79864/comment/156395a3_5f63e12e :
PS1, Line 236: uint32_t
> > should be uint64_t in case cbmem was installed >4GiB […]
agree.
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Change subject: mb/emulation/riscv: Limit DRAM size
......................................................................
Patch Set 7:
(1 comment)
Patchset:
PS7:
> We could probably read the DRAM regions from dtb or fw_cfg. Looking at current
> QEMU code the riscv `virt' machine seems to support both. Though, I couldn't
> figure out the details. Support for the latter currently lives in the x86
>board ports, but could probably be moved into drivers/.
Reading dtb in romstage is painful. The fdt libraries in coreboot are from depthcharge which unflattens it using heap, which is not available in romstage. Maybe we should think about importing libfdt in coreboot which is better for just parsing it which we need here.
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Change subject: cpu/x86/(sipi|smm): Pass on CR3 from ramstage
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
> Oh, if I had known you were working on this, I wouldn't have done CB:79864.
Oh I missed that one too :-D
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Change subject: cpu/x86: Support runtime page tables on APs
......................................................................
Patch Set 1:
(1 comment)
File src/cpu/x86/mp_init.c:
https://review.coreboot.org/c/coreboot/+/79864/comment/208c5a6f_f8c4e1ba :
PS1, Line 236: uint32_t
> should be uint64_t in case cbmem was installed >4GiB
In that case you need a below 4G trampoline pages before setting those above 4G pages. Maybe that could be done as part of a follow-up, that makes above 4G firmware working in general?
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