coreboot-gerrit February 2024

coreboot-gerrit@coreboot.org

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[M] Change in coreboot[main]: cpu/x86/64bit: Turn jumping to long mode into a macro
by Felix Held (Code Review) 06 Feb '24

06 Feb '24

Attention is currently required from: Arthur Heymans, Fred Reitberger, Jason Glenesk, Jérémy Compostella, Matt DeVillier. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79261?usp=email ) Change subject: cpu/x86/64bit: Turn jumping to long mode into a macro ...................................................................... Patch Set 4: Code-Review+1 (1 comment) File src/cpu/qemu-x86/cache_as_ram_bootblock.S: https://review.coreboot.org/c/coreboot/+/79261/comment/fec9002e_954b5dda : PS4, Line 83: setup_longmode $(CONFIG_ARCH_X86_64_PGTBL_LOC) this looks to me like it fixed a bug by moving the long mode entry into the #if ENV_X86_64 guards. if this is true, it would be good to either mention that in the commit message or do that in a separate patch -- To view, visit https://review.coreboot.org/c/coreboot/+/79261?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ida861338004187e4e714be41e17c8447fa4cf935 Gerrit-Change-Number: 79261 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Tue, 06 Feb 2024 14:18:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[main]: device/pciexp_device.c: Fix setting Max Payload Size
by Michał Żygowski (Code Review) 06 Feb '24

06 Feb '24

Attention is currently required from: Angel Pons, Arthur Heymans, Felix Held, Krystian Hebel, Kyösti Mälkki, Michał Żygowski, Nico Huber. Hello Angel Pons, Arthur Heymans, Felix Held, Kyösti Mälkki, Nico Huber, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/77338?usp=email to look at the new patch set (#15). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: device/pciexp_device.c: Fix setting Max Payload Size ...................................................................... device/pciexp_device.c: Fix setting Max Payload Size Current implementation assumes that the endpoint device is connected directly to the PCIe Root Port, which does not always have to be true. In a case where there is a PCIe switch between the endpoint and the root port, the Max Payload Size capability may differ across the devices in the chain and coreboot will not set a correct Max Payload Size. This results in a PCIe device malfunction in pre-OS environment, e.g. if the Ethernet NICs are connected behind a PCIe switch, the iPXE fails to obtain the DHCP configuration. Fix this by traversing the topology and programming the highest common Max Payload Size in the given PCIe device chain during enumeration. Once finished, the root port has the highest common Max Payload Size supported by all the devices in the chain. So at the end of roott port bus scan, propagate the root port's Max Payload Size to all downstream devices to keep Max Payload Size in sync within the whole chain. TEST=Perform successful dhcp command in iPXE on the NIC connected to the PCIe root port via ASMedia ASM1806 PCIe switch and again on the NIC connected directly to the PCIe root port. Change-Id: I24386dc208363b7d94fea46dec25c231a3968225 Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> --- M src/device/pciexp_device.c 1 file changed, 140 insertions(+), 28 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/77338/15 -- To view, visit https://review.coreboot.org/c/coreboot/+/77338?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I24386dc208363b7d94fea46dec25c231a3968225 Gerrit-Change-Number: 77338 Gerrit-PatchSet: 15 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: arch/arm64/armv8: Add exception output without printk
by Maximilian Brune (Code Review) 06 Feb '24

06 Feb '24

Attention is currently required from: Arthur Heymans, Benjamin Doron, David Milosevic, Julius Werner. Hello Arthur Heymans, Benjamin Doron, David Milosevic, Julius Werner, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/80184?usp=email to look at the new patch set (#4). Change subject: arch/arm64/armv8: Add exception output without printk ...................................................................... arch/arm64/armv8: Add exception output without printk In case printk does not work the current exception handler will print a simple "!" to notify the developer that coreboot is actually there but something went wrong. The "!" can be quite confusing when it actually happens that printk does not work. Since "!" doesn't really say much (if you don't know the exception arm64 code) the developer (like me) can easily assume that something went wrong while configuring clocks or baud rate of UART, since the output seemingly does not seem to make sense. This adds a little bit more output to assure the developer that what was printed was actually intended to be printed. Therefore it prints "EXCEPT" which assures the developer that this was intended output. It also adds a comment above so that developer can more easily grep for this message. It has intentionally not been written as: ``` const char *msg = "\r\n!EXCPT!"; while (*msg) __uart_tx_byte(*msg++); ``` because in this case the compiler will generate code that will place `msg` somewhere in bootblock and the code will try to access this using a memory address. In rare cases (if you link bootblock at the wrong address) this memory address can be wrong and coreboot will not print the message. Using individual calls to `__uart_tx_byte` ensures that the compiler will generate code which directly puts the character bytes into the argument register without referencing a variable in bootblock. Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> Change-Id: I2f858730469fff3cae120fd7c32fec53b3d309ca --- M src/arch/arm64/armv8/exception.c 1 file changed, 12 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/80184/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/80184?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2f858730469fff3cae120fd7c32fec53b3d309ca Gerrit-Change-Number: 80184 Gerrit-PatchSet: 4 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: util/crossgcc: Support building gcc for riscv32
by Arthur Heymans (Code Review) 06 Feb '24

06 Feb '24

Attention is currently required from: Martin L Roth, Zebreus. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80317?usp=email ) Change subject: util/crossgcc: Support building gcc for riscv32 ...................................................................... Patch Set 1: Code-Review-1 (1 comment) Patchset: PS1: The riscv64 toolchain can build 32bit binaries just fine. Why is this needed? -- To view, visit https://review.coreboot.org/c/coreboot/+/80317?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ice89e3af86a42d47b3b24022dd6a5a70ab3b6504 Gerrit-Change-Number: 80317 Gerrit-PatchSet: 1 Gerrit-Owner: Zebreus <lennarteichhorn(a)googlemail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Zebreus <lennarteichhorn(a)googlemail.com> Gerrit-Comment-Date: Tue, 06 Feb 2024 13:12:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[main]: device/pciexp_device.c: Fix setting Max Payload Size
by Patrick Rudolph (Code Review) 06 Feb '24

06 Feb '24

Attention is currently required from: Angel Pons, Arthur Heymans, Felix Held, Krystian Hebel, Kyösti Mälkki, Michał Żygowski, Nico Huber. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77338?usp=email ) Change subject: device/pciexp_device.c: Fix setting Max Payload Size ...................................................................... Patch Set 14: (1 comment) File src/device/pciexp_device.c: https://review.coreboot.org/c/coreboot/+/77338/comment/15923188_7000789a : PS10, Line 709: pciexp_configure_max_payload > This is done. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/77338?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I24386dc208363b7d94fea46dec25c231a3968225 Gerrit-Change-Number: 77338 Gerrit-PatchSet: 14 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 06 Feb 2024 12:59:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/emulation/riscv: Limit DRAM size
by Maximilian Brune (Code Review) 06 Feb '24

06 Feb '24

Attention is currently required from: Arthur Heymans, Christian Walter, Nico Huber, Philipp Hug, ron minnich. Maximilian Brune has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68843?usp=email ) Change subject: mb/emulation/riscv: Limit DRAM size ...................................................................... Patch Set 7: (1 comment) Patchset: PS7: > > We could probably read the DRAM regions from dtb or fw_cfg. Looking at current […] I agree we may be better of just adding libfdt so we don't always need to unflatten it. Or we extend our FDT implementation to also be able to read the DTB representation. It may also come in handy for other mainboards (I actually needed it at some point). -- To view, visit https://review.coreboot.org/c/coreboot/+/68843?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib8555de361d1129d3d1995f056518c576f055515 Gerrit-Change-Number: 68843 Gerrit-PatchSet: 7 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Christian Walter <christian.walter(a)9elements.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Tue, 06 Feb 2024 12:52:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: device/pciexp_device.c: Fix setting Max Payload Size
by Michał Żygowski (Code Review) 06 Feb '24

06 Feb '24

Attention is currently required from: Angel Pons, Arthur Heymans, Felix Held, Krystian Hebel, Kyösti Mälkki, Nico Huber, Patrick Rudolph. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77338?usp=email ) Change subject: device/pciexp_device.c: Fix setting Max Payload Size ...................................................................... Patch Set 14: (2 comments) File src/device/pciexp_device.c: https://review.coreboot.org/c/coreboot/+/77338/comment/fab04332_b926cf7f : PS11, Line 598: awlays Just to confirm we are on the same page. Patchset 14 currently does the following (in chronological order of execution): 1. Sets the bridge's MPS to its max cap in pciexp_scan_bus. 2. Sets device MPS to its max cap in pciexp_tune_dev. 3. In pciexp_tune_dev, traverses the topology up to eventually limit the currently configured MPS to the lower MPS of the device and its parent. 4. At the end of pciexp_scan_bus the MPS of root port is programmed to all devices beneath it. I have removed the state tracking as per your idea: > On the way down, set every device to its own maximum. On the way up, propagate the minimum from the endpoints up to the root port This would work without additional state tracking. Is there any way to make it simpler? According to your comment: > With the max_payload_set state, we can also do everything on the way up. Then we would have to look at the already set value and the cap maximum (like the current implementation does). it looks like there is such a way. Although, I can't see how "do everything the way up" can be done, so any further suggestions are appreciated. File src/device/pciexp_device.c: https://review.coreboot.org/c/coreboot/+/77338/comment/4ab2e770_9415d996 : PS13, Line 755: (child->upstream->secondary > max_bus)) > `child->upstream` is the same as `bus` by definition. So this check […] Removed -- To view, visit https://review.coreboot.org/c/coreboot/+/77338?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I24386dc208363b7d94fea46dec25c231a3968225 Gerrit-Change-Number: 77338 Gerrit-PatchSet: 14 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 06 Feb 2024 12:22:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Comment-In-Reply-To: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: util/crossgcc: Support building gcc for riscv32
by Zebreus (Code Review) 06 Feb '24

06 Feb '24

Zebreus has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80317?usp=email ) Change subject: util/crossgcc: Support building gcc for riscv32 ...................................................................... util/crossgcc: Support building gcc for riscv32 Adds a target for building gcc for the riscv32-elf target architecture to the Makefile and buildgcc. riscv32 support is needed for porting coreboot to some smaller RISC-V SoCs like the BL808. Change-Id: Ice89e3af86a42d47b3b24022dd6a5a70ab3b6504 Signed-off-by: Lennart Eichhorn <lennarteichhorn(a)googlemail.com> --- M util/crossgcc/Makefile M util/crossgcc/buildgcc 2 files changed, 11 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/80317/1 diff --git a/util/crossgcc/Makefile b/util/crossgcc/Makefile index 06ec91c..db1916b 100644 --- a/util/crossgcc/Makefile +++ b/util/crossgcc/Makefile @@ -10,8 +10,8 @@ all: $(MAKE) build-i386 build-x64 build-arm \ - build-riscv build-aarch64 build-ppc64 build-nds32le \ - build_clang build_iasl build_nasm + build-riscv build-riscv32 build-aarch64 build-ppc64 \ + build-nds32le build_clang build_iasl build_nasm ########################################################### ### targets to do buildgcc builds @@ -47,6 +47,9 @@ build-riscv: @$(MAKE) build_gcc BUILD_PLATFORM=riscv-elf +build-riscv32: + @$(MAKE) build_gcc BUILD_PLATFORM=riscv32-elf + build-ppc64: @$(MAKE) build_gcc BUILD_PLATFORM=powerpc64-linux-gnu @@ -69,6 +72,6 @@ .PHONY: all build_gcc build_iasl build_clang build_nasm \ clean distclean clean_tempfiles \ build-i386 build-x64 build-arm build-aarch64 \ - build-riscv build-ppc64 build-nds32le + build-riscv build-riscv32 build-ppc64 build-nds32le .NOTPARALLEL: diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index b294da5..529df98 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -593,8 +593,8 @@ printf " [-l|--languages <languages>] comma separated list of target languages\n" printf " (defaults to $DEFAULT_LANGUAGES)\n" printf "Platforms for GCC:\n" - printf " x86_64 i386-elf i386-mingw32 riscv-elf arm aarch64\n" - printf " powerpc64le-linux-gnu nds32le-elf\n\n" + printf " x86_64 i386-elf i386-mingw32 riscv-elf riscv32-elf arm\n" + printf " aarch64 powerpc64le-linux-gnu nds32le-elf\n\n" } printversion() { @@ -1000,6 +1000,9 @@ TARGET_BINUTILS_OPTIONS="$TARGET_BINUTILS_OPTIONS --with-isa-spec=20191213";; powerpc64*-linux*) ;; i386*) TARGETARCH=i386-elf;; + riscv32-elf) TARGETARCH=riscv32-elf + GCC_OPTIONS="$GCC_OPTIONS --with-isa-spec=20191213" + BINUTILS_OPTIONS="$BINUTILS_OPTIONS --with-isa-spec=20191213";; arm*) TARGETARCH=arm-eabi;; aarch64*) TARGETARCH=aarch64-elf;; nds32le-elf) ;; -- To view, visit https://review.coreboot.org/c/coreboot/+/80317?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ice89e3af86a42d47b3b24022dd6a5a70ab3b6504 Gerrit-Change-Number: 80317 Gerrit-PatchSet: 1 Gerrit-Owner: Zebreus <lennarteichhorn(a)googlemail.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[main]: device/pciexp_device.c: Fix setting Max Payload Size
by Michał Żygowski (Code Review) 06 Feb '24

06 Feb '24

Attention is currently required from: Angel Pons, Arthur Heymans, Felix Held, Krystian Hebel, Kyösti Mälkki, Michał Żygowski, Patrick Rudolph. Hello Angel Pons, Arthur Heymans, Felix Held, Kyösti Mälkki, Nico Huber, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/77338?usp=email to look at the new patch set (#14). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: device/pciexp_device.c: Fix setting Max Payload Size ...................................................................... device/pciexp_device.c: Fix setting Max Payload Size Current implementation assumes that the endpoint device is connected directly to the PCIe Root Port, which does not always have to be true. In a case where there is a PCIe switch between the endpoint and the root port, the Max Payload Size capability may differ across the devices in the chain and coreboot will not set a correct Max Payload Size. This results in a PCIe device malfunction in pre-OS environment, e.g. if the Ethernet NICs are connected behind a PCIe switch, the iPXE fails to obtain the DHCP configuration. Fix this by traversing the topology and programming the highest common Max Payload Size in the given PCIe device chain during enumeration. Once finished, the root port has the highest common Max Payload Size supported by all the devices in the chain. So at the end of roott port bus scan, propagate the root port's Max Payload Size to all downstream devices to keep Max Payload Size in sync within the whole chain. TEST=Perform successful dhcp command in iPXE on the NIC connected to the PCIe root port via ASMedia ASM1806 PCIe switch and again on the NIC connected directly to the PCIe root port. Change-Id: I24386dc208363b7d94fea46dec25c231a3968225 Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> --- M src/device/pciexp_device.c 1 file changed, 140 insertions(+), 28 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/77338/14 -- To view, visit https://review.coreboot.org/c/coreboot/+/77338?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I24386dc208363b7d94fea46dec25c231a3968225 Gerrit-Change-Number: 77338 Gerrit-PatchSet: 14 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[main]: mb/amd/birman: Add Birmanplus board support for PHX1 SOC
by Anand Vaikar (Code Review) 06 Feb '24

06 Feb '24

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk. Hello Felix Held, Fred Reitberger, Jason Glenesk, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/80353?usp=email to look at the new patch set (#2). Change subject: mb/amd/birman: Add Birmanplus board support for PHX1 SOC ...................................................................... mb/amd/birman: Add Birmanplus board support for PHX1 SOC 1)Initial commit for upstreaming Birmanplus mainboard changes. 2)Add the DXIO descriptors for Birmanplus mainboard. Change-Id: I075dcf0214f8dc8b33b0e429d83d270b2f0952e1 Signed-off-by: Anand Vaikar <a.vaikar2021(a)gmail.com> --- M src/mainboard/amd/birman/Kconfig M src/mainboard/amd/birman/Kconfig.name M src/mainboard/amd/birman/Makefile.mk A src/mainboard/amd/birman/variants/birmanplus/port_descriptors.c 4 files changed, 216 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/80353/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/80353?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I075dcf0214f8dc8b33b0e429d83d270b2f0952e1 Gerrit-Change-Number: 80353 Gerrit-PatchSet: 2 Gerrit-Owner: Anand Vaikar <a.vaikar2021(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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