Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80330?usp=email )
Change subject: arch/x86/ioapic: always write IOAPIC ID in set_ioapic_id
......................................................................
arch/x86/ioapic: always write IOAPIC ID in set_ioapic_id
Back in the days of the APIC bus, the IOAPIC IDs mustn't overlap with
the LAPIC IDs (0 to CONFIG_MAX_CPUS - 1), but since the IOAPIC and LAPIC
nowadays talk to each other via the system bus, an IOAPIC ID of 0 is
valid. When set_ioapic_id gets called with an IOAPIC ID of 0, it skipped
writing the IOAPIC ID to the corresponding IOAPIC register, so the code
was relying of the register having the expected default value of the
IOAPIC IO 0 for things to work as expected. The case of the IOAPIC ID
being 0 is the most common case in coreboot, since that's what
register_new_ioapic_gsi0 will end up doing. Fix this issue by not making
the io_apic_write call conditional on ioapic_id being non-zero. The only
southbridge that doesn't call register_new_ioapic_gsi0, calls
set_ioapic_id with the IOAPIC ID 2 for which this won't cause any
changes in behavior.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: Ic8538f82a6b10f16eeb228669db197dc8e326ffd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80330
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Nico Huber <nico.h(a)gmx.de>
Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com>
Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/arch/x86/ioapic.c
1 file changed, 2 insertions(+), 6 deletions(-)
Approvals:
Matt DeVillier: Looks good to me, approved
build bot (Jenkins): Verified
Arthur Heymans: Looks good to me, approved
Nico Huber: Looks good to me, but someone else must approve
diff --git a/src/arch/x86/ioapic.c b/src/arch/x86/ioapic.c
index 04c852b..df97a50 100644
--- a/src/arch/x86/ioapic.c
+++ b/src/arch/x86/ioapic.c
@@ -131,12 +131,8 @@
ioapic_base);
printk(BIOS_DEBUG, "IOAPIC: ID = 0x%02x\n", ioapic_id);
- if (ioapic_id) {
- /* Set IOAPIC ID if it has been specified. */
- io_apic_write(ioapic_base, 0x00,
- (io_apic_read(ioapic_base, 0x00) & 0xf0ffffff) |
- (ioapic_id << 24));
- }
+ io_apic_write(ioapic_base, 0x00,
+ (io_apic_read(ioapic_base, 0x00) & 0xf0ffffff) | (ioapic_id << 24));
printk(BIOS_SPEW, "IOAPIC: Dumping registers\n");
for (i = 0; i < 3; i++)
--
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Attention is currently required from: Felix Singer, Nico Huber.
Hello Nico Huber,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/80168?usp=email
to look at the new patch set (#3).
The following approvals got outdated and were removed:
Code-Review+1 by Nico Huber
Change subject: superio/ite/env_ctrl: Allow to override the fan PWM clock
......................................................................
superio/ite/env_ctrl: Allow to override the fan PWM clock
Change-Id: I5c43aec792195df835d1c39c9c25233899ba1a85
Signed-off-by: Nico Huber <nico.huber(a)secunet.com>
---
M src/superio/ite/common/env_ctrl.c
M src/superio/ite/common/env_ctrl.h
M src/superio/ite/common/env_ctrl_chip.h
3 files changed, 29 insertions(+), 14 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/80168/3
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Weimin Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80316?usp=email )
Change subject: mb/google/nissa: Skip locking for GPP_F15 GPIO
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS1:
> Anraggar follow the same design as nissa reference, the issue is not Anragger unique. […]
Done
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Hello Dolan Liu, Eric Lai, Kapil Porwal, Nick Vaccaro, Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#3).
Change subject: mb/google/nissa: Skip locking for GPP_F15 GPIO
......................................................................
mb/google/nissa: Skip locking for GPP_F15 GPIO
There is an existing issue for nissa where wake up from
RTC wake is not working during suspend_stress_test.
The phenomenon of the issue is that after pulling out the
stylus, can see an interrupt storm occurs checking through
"cat /proc/interrupts | grep acpi".
When the counter of interrupt is greater than a certain
value, "Disabling IRQ #9" will occurs, so RTC wake is not
working.
Reference: https://review.coreboot.org/c/coreboot/+/65086
This patch skips the locking for GPP_F15 to allow kernel to
configure it later. The interrupt storm of acpi dispeared.
BUG=b:321348117
TEST=1. cat /proc/interrupts | grep acpi
there isn't interrupt storm of acpi when pulling out stylus.
2. The stylus tools panel will pop up when pulling out it.
3. Inserts stylus can wakeup DUT after powerd_dbus_suspend.
4. Passed:
suspend_stress_test -c 2500 --suspend_min=15 --suspend_max=20
Change-Id: Ie143c43e0555d17d8a290f17637b537fba806144
Signed-off-by: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com>
---
M src/mainboard/google/brya/variants/baseboard/nissa/gpio.c
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/80316/3
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I'd like you to reexamine a change. Please visit
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The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: mb/google/nissa/var/anraggar: Skip locking for GPP_F15 GPIO
......................................................................
mb/google/nissa/var/anraggar: Skip locking for GPP_F15 GPIO
There is an existing issue for nissa where wake up from
RTC wake is not working during suspend_stress_test.
The phenomenon of the issue is that after pulling out the
stylus, can see an interrupt storm occurs checking through
"cat /proc/interrupts | grep acpi".
When the counter of interrupt is greater than a certain
value, "Disabling IRQ #9" will occurs, so RTC wake is not
working.
Reference: https://review.coreboot.org/c/coreboot/+/65086
This patch skips the locking for GPP_F15 to allow kernel to
configure it later. The interrupt storm of acpi dispeared.
BUG=b:321348117
TEST=1. cat /proc/interrupts | grep acpi
there isn't interrupt storm of acpi when pulling out stylus.
2. The stylus tools panel will pop up when pulling out it.
3. Inserts stylus can wakeup DUT after powerd_dbus_suspend.
4. Passed:
suspend_stress_test -c 2500 --suspend_min=15 --suspend_max=20
Change-Id: Ie143c43e0555d17d8a290f17637b537fba806144
Signed-off-by: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com>
---
M src/mainboard/google/brya/variants/baseboard/nissa/gpio.c
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/80316/2
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Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79261?usp=email )
Change subject: cpu/x86/64bit: Turn jumping to long mode into a macro
......................................................................
Patch Set 5:
(1 comment)
File src/cpu/qemu-x86/cache_as_ram_bootblock.S:
https://review.coreboot.org/c/coreboot/+/79261/comment/f5e10642_f6a03843 :
PS4, Line 83: setup_longmode $(CONFIG_ARCH_X86_64_PGTBL_LOC)
> > this looks to me like it fixed a bug by moving the long mode entry into the #if ENV_X86_64 guards. if this is true, it would be good to either mention that in the commit message or do that in a separate patch
>
> Hmm entry64.inc actually guards everything, so nothing changes. I'll move it to a separate patch.
Done.
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Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80354?usp=email )
Change subject: cpu/qemu-x86/cache_as_ram: Move guard
......................................................................
cpu/qemu-x86/cache_as_ram: Move guard
Although entry64.inc does guard against ENV_X86_64, it's more aesthetic
to have it with the other 64bit code below a guard just like other
platforms.
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
Change-Id: If3ef19dd6654cd2fa0be3c68dee4a472e7a7935d
---
M src/cpu/qemu-x86/cache_as_ram_bootblock.S
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/80354/1
diff --git a/src/cpu/qemu-x86/cache_as_ram_bootblock.S b/src/cpu/qemu-x86/cache_as_ram_bootblock.S
index 0943e35..859b760 100644
--- a/src/cpu/qemu-x86/cache_as_ram_bootblock.S
+++ b/src/cpu/qemu-x86/cache_as_ram_bootblock.S
@@ -77,11 +77,11 @@
/* Align the stack and keep aligned for call to bootblock_c_entry() */
and $0xfffffff0, %esp
+#if ENV_X86_64
/* entry64.inc preserves ebx. */
#include <cpu/x86/64bit/entry64.inc>
/* Restore the BIST result and timestamps. */
-#if ENV_X86_64
movd %mm2, %rdi
shlq $32, %rdi
movd %mm1, %rsi
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Hello Felix Held, Fred Reitberger, Jason Glenesk, Jérémy Compostella, Matt DeVillier, Patrick Rudolph, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#5).
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Code-Review+1 by Felix Held, Code-Review+2 by Patrick Rudolph, Verified+1 by build bot (Jenkins)
The change is no longer submittable: Code-Review and Verified are unsatisfied now.
Change subject: cpu/x86/64bit: Turn jumping to long mode into a macro
......................................................................
cpu/x86/64bit: Turn jumping to long mode into a macro
This makes it easier to reuse, e.g. if you want to do it twice in one
assembly file.
Change-Id: Ida861338004187e4e714be41e17c8447fa4cf935
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/cpu/intel/car/core2/cache_as_ram.S
M src/cpu/intel/car/non-evict/cache_as_ram.S
M src/cpu/intel/car/p4-netburst/cache_as_ram.S
M src/cpu/qemu-x86/cache_as_ram_bootblock.S
M src/cpu/x86/64bit/entry64.inc
M src/cpu/x86/64bit/mode_switch.S
M src/cpu/x86/64bit/mode_switch2.S
M src/cpu/x86/sipi_vector.S
M src/cpu/x86/smm/smm_stub.S
M src/soc/amd/common/block/cpu/noncar/pre_c.S
M src/soc/intel/common/block/cpu/car/cache_as_ram.S
11 files changed, 30 insertions(+), 19 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/79261/5
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Change subject: cpu/x86/64bit: Turn jumping to long mode into a macro
......................................................................
Patch Set 4:
(1 comment)
File src/cpu/qemu-x86/cache_as_ram_bootblock.S:
https://review.coreboot.org/c/coreboot/+/79261/comment/a66f0657_58050705 :
PS4, Line 83: setup_longmode $(CONFIG_ARCH_X86_64_PGTBL_LOC)
> this looks to me like it fixed a bug by moving the long mode entry into the #if ENV_X86_64 guards. if this is true, it would be good to either mention that in the commit message or do that in a separate patch
Hmm entry64.inc actually guards everything, so nothing changes. I'll move it to a separate patch.
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Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79261?usp=email )
Change subject: cpu/x86/64bit: Turn jumping to long mode into a macro
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Patch Set 4: Code-Review+1
(1 comment)
File src/cpu/qemu-x86/cache_as_ram_bootblock.S:
https://review.coreboot.org/c/coreboot/+/79261/comment/fec9002e_954b5dda :
PS4, Line 83: setup_longmode $(CONFIG_ARCH_X86_64_PGTBL_LOC)
this looks to me like it fixed a bug by moving the long mode entry into the #if ENV_X86_64 guards. if this is true, it would be good to either mention that in the commit message or do that in a separate patch
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