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I'd like you to reexamine a change. Please visit
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Change subject: mb/google/brox: Handle GPI_INT pin lower to GPI_WAKE
......................................................................
mb/google/brox: Handle GPI_INT pin lower to GPI_WAKE
In case where PAD_CFG_GPI_INT() is initialized with a pin value
lower to PAD_CFG_GPI_IRQ_WAKE() for same GPIO community
the set_ioapic_used() is only called for the PAD_CFG_GPI_IRQ_WAKE() pin.
Due to this the IRQ associated with PAD_CFG_GPI_INT() is found free by
find_free_unique_irq() during IRQ assignment and assigned to other pins
which causes IRQ conflicts
BUG=b:322984217
BRANCH=None
TEST=Boot test on brox, check if correct IRQ assigned to EC
Change-Id: I8c3d557e888b8d0ceac203f49b702910fba26d6d
Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com>
---
M src/mainboard/google/brox/variants/baseboard/brox/gpio.c
M src/soc/intel/common/block/gpio/gpio.c
M src/soc/intel/common/block/include/intelblocks/gpio_defs.h
3 files changed, 26 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/80334/3
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Change subject: mb/dell: Add OptiPlex 7020/9020 port
......................................................................
Patch Set 31:
(1 comment)
Patchset:
PS31:
> Yes, this is what I get with a jumper on the SERVICE_MODE header. […]
@nat @Ben you can get around this on newer kernels by first removing the spi-intel-platform module - rmmod spi-intel-platform.
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Change subject: device/pciexp_device.c: Fix setting Max Payload Size
......................................................................
Patch Set 15:
(6 comments)
File src/device/pciexp_device.c:
https://review.coreboot.org/c/coreboot/+/77338/comment/4032840c_b5bef0c3 :
PS11, Line 598: awlays
Thanks for the update and your patience.
> Just to confirm we are on the same page. Patchset 14 currently does the following (in chronological order of execution):
>
> 1. Sets the bridge's MPS to its max cap in pciexp_scan_bus.
> 2. Sets device MPS to its max cap in pciexp_tune_dev.
> 3. In pciexp_tune_dev, traverses the topology up to eventually limit the currently configured MPS to the lower MPS of the device and its parent.
Explicitly walking up is probably not necessary, as pciexp_tune_dev()
is already called per level up until the root port. I'll comment on
that inline. Please take it with a grain of salt, I'll look into it
again tomorrow after a night's sleep.
> 4. At the end of pciexp_scan_bus the MPS of root port is programmed to all devices beneath it.
>
> I have removed the state tracking as per your idea:
>
> > On the way down, set every device to its own maximum. On the way up, propagate the minimum from the endpoints up to the root port
> This would work without additional state tracking.
>
> Is there any way to make it simpler? According to your comment:
>
> > With the max_payload_set state, we can also do everything on the way up.
> Then we would have to look at the already set value and the cap maximum
> (like the current implementation does).
>
> it looks like there is such a way. Although, I can't see how "do everything the way up" can be done, so any further suggestions are appreciated.
I see a way, but it wouldn't be simpler, I guess. With `max_payload_set`
we could dynamically decide if we have to read the cap of a bridge or
the current value. But that's another `if` in the code that's probably
better avoided.
File src/device/pciexp_device.c:
https://review.coreboot.org/c/coreboot/+/77338/comment/f3866d3e_7b7a22dd :
PS15, Line 638: pciexp_dev_set_max_payload_size(child, max_payload);
Shouldn't be necessary as that's what we'll do with pciexp_sync_max_payload_size().
https://review.coreboot.org/c/coreboot/+/77338/comment/ca013069_2718eeec :
PS15, Line 641: if (max_payload != child_max_payload)
: printk(BIOS_INFO, "%s: Max_Payload_Size adjusted to %d\n", dev_path(child),
: (1 << (max_payload + 7)));
This too could be dropped then.
https://review.coreboot.org/c/coreboot/+/77338/comment/78200e1a_e3c3bbce :
PS15, Line 691: };
I still don't see why we would need a loop. pciexp_tune_dev() will be called
for each level until the root. So calling pciexp_set_max_payload_size()
in pciexp_tune_dev() directly, should be enough. Unless I miss something?
Now that I looked into pciexp_tune_dev() again, I can't say often enough
how confusing it is that the parent is named 'root' there. Hope that's not
the source of any trouble. That function definitely runs for every PCIe
device beside the root ports, and only on the highest level the parent
(`root`) will be the root port.
https://review.coreboot.org/c/coreboot/+/77338/comment/d474a022_cf3addc0 :
PS15, Line 728: pciexp_dev_set_max_payload_size(dev, pciexp_dev_get_max_payload_size_cap(dev));
If I'm not mistaken, `dev` could be a bridge that already has its
MPS constrained by a downstream device. So this should only happen
at the lowest level, i.e. would need something like an
`if (is_endpoint(dev))`.
https://review.coreboot.org/c/coreboot/+/77338/comment/9310afe1_bc5f5ad7 :
PS15, Line 740: pciexp_dev_set_max_payload_size(bus->dev, max_payload);
This step seems redundant. Because for the first call of
pciexp_sync_max_payload_size() `bus->dev` will be the one device
where we looked up the `max_payload`. And for all recursive calls
we'll have set it right before in line 747.
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Change subject: mb/up/squared: Make mini PCIe port mode configurable
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/80261/comment/f01bfc57_c8992b5a :
PS2, Line 9: Add ENABLE_MSATA config knob and pad configuration to put Mini PCIe port
: into mSATA mode.
> Good point. […]
Hmm, I was about to suggest to disable the PCIe root port based on the
Kconfig setting, would have to be in ramstage something like:
```
#include <static_devices.h>
...
if (CONFIG(ENABLE_MSATA))
_dev_pcie_rp0X_ptr->enabled = 0;
```
I couldn't figure out which root port it is, though (6 are enabled but
datasheet lists only 4 used?). So this might be something for another
patch, iff somebody has the time and hardware to test.
I don't believe it will cause any issue to leave it enabled, btw.
Because FSP should disable the root port anyway if no PCIe is
connected.
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Change subject: libpayload/libc/time: Fix possible overflow in multiplication
......................................................................
Patch Set 11:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/78888/comment/789dfa08_3c25034c :
PS11, Line 15: counter should never be that fast.
> Oh okay, yeah, then we need to do something. Which platform did he see it on? […]
gcd64() would fix the regression, I'm ok with that. Though, in the long run,
we should still fix the original overflow for the general case. I can also
look into that.
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Change subject: arch/x86/ioapic: use uintptr_t for IOAPIC base address
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Patch Set 1: Code-Review+1
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Change subject: arch/x86/mpspec: reduce scope of smp_write_ioapic
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Change subject: brox: Handle GPI_INT pin value lower to GPI_WAKE
......................................................................
Patch Set 2:
(2 comments)
File src/soc/intel/common/block/include/intelblocks/gpio_defs.h:
https://review.coreboot.org/c/coreboot/+/80334/comment/c4c49832_564a221c :
PS2, Line 343: PAD_IRQ_ROUTE(SWAPPED), \
can we push this to the next line? This causes the line to go over the line limit (96 characters). See: https://doc.coreboot.org/contributing/coding_style.htmlhttps://review.coreboot.org/c/coreboot/+/80334/comment/e2a9515e_412a79f3 :
PS2, Line 355: PAD_IRQ_ROUTE(SWAPPED), \
Same here.
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