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Change subject: mb/google/nissa/var/anraggar: Config DP AUX BIAS according to fw_config
......................................................................
Patch Set 11: -Code-Review
(1 comment)
File src/mainboard/google/brya/variants/anraggar/variant.c:
https://review.coreboot.org/c/coreboot/+/80259/comment/9353a04f_8d920e98 :
PS11, Line 26: config->tcss_aux_ori = 4;
You should have two tcss_aux_ori values right?
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Change subject: mb/dell: Add OptiPlex 7020/9020 port
......................................................................
Patch Set 31:
(1 comment)
Patchset:
PS31:
> @nat @Ben you can get around this on newer kernels by first removing the spi-intel-platform module - […]
After removing the module, it works great! I can flash from the original firmware with the service jumper set, and from Coreboot with or without it.
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Change subject: mb/google/nissa: Skip locking for GPP_F15 GPIO
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Patch Set 3:
(1 comment)
File src/mainboard/google/brya/variants/anraggar/gpio.c:
https://review.coreboot.org/c/coreboot/+/80316/comment/927f55f9_b88f3b72 :
PS1, Line 54: PLTRST
> @Eric PLTRST or others, could you give some suggestion?
details here https://doc.coreboot.org/getting_started/gpio.html#id1
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Change subject: mb/google/nissa/var/anraggar: Config DP AUX BIAS according to fw_config
......................................................................
Patch Set 11:
(1 comment)
File src/mainboard/google/brya/variants/anraggar/variant.c:
https://review.coreboot.org/c/coreboot/+/80259/comment/193885a2_98b77c9d :
PS10, Line 32: 0
> Two questions: […]
1. The previous configuration of C1(MB) was wrong, so fixed it.
2. After fixed C1(MB) configuration, the only diff is to add aux_bias_pads for C0(DB), the 'else' only for printing info.
Thanks.
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Change subject: mb/google/nissa/var/yaviks: Enable USE_MTCL and DRIVERS_MTK_WIFI
......................................................................
Patch Set 3: Code-Review+2
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/80305/comment/daffa710_bb9b2ffc :
PS3, Line 7: for YAVIKS
:
> This seems redundant as it’s mentioned in the prefix.
Acknowledged
https://review.coreboot.org/c/coreboot/+/80305/comment/d7c97202_9ab49174 :
PS3, Line 9: Yaviks will be the first model to take advantage of this feature.
> Please mention Mediatek Countly List table or so ones.
done
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Change subject: soc/mediatek/mt8188: Enable CROS_WIDEVINE_SMC
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Change subject: mb/google/brox: Handle GPI_INT pin lower to GPI_WAKE
......................................................................
Patch Set 2:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/80334/comment/ff26bc48_56abd8cc :
PS2, Line 7: brox
> Please always use meaningful topics, e.g. […]
Done
File src/soc/intel/common/block/include/intelblocks/gpio_defs.h:
https://review.coreboot.org/c/coreboot/+/80334/comment/b6a8b797_e8dc080c :
PS2, Line 343: PAD_IRQ_ROUTE(SWAPPED), \
> can we push this to the next line? This causes the line to go over the line limit (96 characters). […]
Done
https://review.coreboot.org/c/coreboot/+/80334/comment/706a9f39_a7ab3595 :
PS2, Line 355: PAD_IRQ_ROUTE(SWAPPED), \
> Same here.
Done
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