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Change subject: mb/google/nissa/var/anraggar: Config DP AUX BIAS according to fw_config
......................................................................
Patch Set 11:
(1 comment)
File src/mainboard/google/brya/variants/anraggar/variant.c:
https://review.coreboot.org/c/coreboot/+/80259/comment/a4cf1911_a1dd78a1 :
PS11, Line 26: config->tcss_aux_ori = 4;
> C1(MB) hasn't retimer IC,so only bit 3 seted to 1: […]
I have submit a new patch to fix.
Thanks.
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Attention is currently required from: Derek Huang, Dolan Liu, Eric Lai, Kapil Porwal, Nick Vaccaro, Subrata Banik, Weimin Wu.
Hello Derek Huang, Dolan Liu, Eric Lai, Kapil Porwal, Nick Vaccaro, Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/80316?usp=email
to look at the new patch set (#4).
The following approvals got outdated and were removed:
Code-Review+2 by Derek Huang, Code-Review+2 by Eric Lai, Code-Review+2 by Subrata Banik, Verified+1 by build bot (Jenkins)
Change subject: mb/google/nissa: Skip locking for GPP_F15 GPIO
......................................................................
mb/google/nissa: Skip locking for GPP_F15 GPIO
There is an existing issue for nissa where wake up from
RTC wake is not working during suspend_stress_test.
The phenomenon of the issue is that after pulling out the
stylus, can see an interrupt storm occurs checking through
"cat /proc/interrupts | grep acpi".
When the counter of interrupt is greater than a certain
value, "Disabling IRQ #9" will occurs, so RTC wake is not
working.
Reference: https://review.coreboot.org/c/coreboot/+/65086
This patch skips the locking for GPP_F15 to allow kernel to
configure it later. The interrupt storm of acpi dispeared.
BUG=b:321348117
TEST=1. cat /proc/interrupts | grep acpi
there isn't interrupt storm of acpi when pulling out stylus.
2. The stylus tools panel will pop up when pulling out it.
3. Inserts stylus can wakeup DUT after powerd_dbus_suspend.
4. Passed:
suspend_stress_test -c 2500 --suspend_min=15 --suspend_max=20
Change-Id: Ie143c43e0555d17d8a290f17637b537fba806144
Signed-off-by: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com>
---
M src/mainboard/google/brya/variants/anraggar/variant.c
M src/mainboard/google/brya/variants/baseboard/nissa/gpio.c
2 files changed, 7 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/80316/4
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Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78888?usp=email )
Change subject: libpayload/libc/time: Fix possible overflow in multiplication
......................................................................
Patch Set 11:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/78888/comment/28bfcee2_5924ad0b :
PS11, Line 15: counter should never be that fast.
> gcd64() would fix the regression, I'm ok with that. Though, in the long run, […]
Okay, uploaded CB:80320 to doo that for now.
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Hello Nico Huber, Yidi Lin,
I'd like you to do a code review.
Please visit
https://review.coreboot.org/c/coreboot/+/80320?usp=email
to review the following change.
Change subject: libpayload: timer: Revert timer_hz() return type to 64-bits
......................................................................
libpayload: timer: Revert timer_hz() return type to 64-bits
It seems that reducing the return type of timer_hz() to uint32_t in
CB:78888 was a bad idea... some Intel platforms actually use their raw
CPU clock for the timestamp counter which can be higher than 4GHz. This
patch reverts it back to uint64_t.
Also remove the redundant assertion in timer/generic.c since timer_us()
itself already does that check.
Change-Id: I471c7de7a28aec5bb965b23525ed579481ac8361
Signed-off-by: Julius Werner <jwerner(a)chromium.org>
---
M payloads/libpayload/drivers/timer/arm64_arch_timer.c
M payloads/libpayload/drivers/timer/generic.c
M payloads/libpayload/drivers/timer/rdtsc.c
M payloads/libpayload/include/libpayload.h
M payloads/libpayload/libc/time.c
5 files changed, 8 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/80320/1
diff --git a/payloads/libpayload/drivers/timer/arm64_arch_timer.c b/payloads/libpayload/drivers/timer/arm64_arch_timer.c
index b4d2b86..087d9e7 100644
--- a/payloads/libpayload/drivers/timer/arm64_arch_timer.c
+++ b/payloads/libpayload/drivers/timer/arm64_arch_timer.c
@@ -32,7 +32,7 @@
#include <arch/lib_helpers.h>
#include <libpayload.h>
-uint32_t timer_hz(void)
+uint64_t timer_hz(void)
{
return raw_read_cntfrq_el0();
}
diff --git a/payloads/libpayload/drivers/timer/generic.c b/payloads/libpayload/drivers/timer/generic.c
index bd5674b..46bc291 100644
--- a/payloads/libpayload/drivers/timer/generic.c
+++ b/payloads/libpayload/drivers/timer/generic.c
@@ -33,10 +33,8 @@
#include <assert.h>
#include <libpayload.h>
-uint32_t timer_hz(void)
+uint64_t timer_hz(void)
{
- /* libc/time.c currently requires all timers to be at least 1MHz. */
- assert(CONFIG_LP_TIMER_GENERIC_HZ >= 1000000);
return CONFIG_LP_TIMER_GENERIC_HZ;
}
diff --git a/payloads/libpayload/drivers/timer/rdtsc.c b/payloads/libpayload/drivers/timer/rdtsc.c
index 952bc0b..d5bf1d2 100644
--- a/payloads/libpayload/drivers/timer/rdtsc.c
+++ b/payloads/libpayload/drivers/timer/rdtsc.c
@@ -35,10 +35,9 @@
#include <arch/rdtsc.h>
#include <assert.h>
-uint32_t timer_hz(void)
+uint64_t timer_hz(void)
{
- assert(UINT32_MAX / 1000 >= lib_sysinfo.cpu_khz);
- return lib_sysinfo.cpu_khz * 1000;
+ return (uint64_t)lib_sysinfo.cpu_khz * 1000;
}
uint64_t timer_raw_value(void)
diff --git a/payloads/libpayload/include/libpayload.h b/payloads/libpayload/include/libpayload.h
index 6da4564..5e34124 100644
--- a/payloads/libpayload/include/libpayload.h
+++ b/payloads/libpayload/include/libpayload.h
@@ -519,7 +519,7 @@
/* Timer functions. */
/* Defined by each architecture. */
-uint32_t timer_hz(void);
+uint64_t timer_hz(void);
uint64_t timer_raw_value(void);
uint64_t timer_us(uint64_t base);
/* Generic. */
diff --git a/payloads/libpayload/libc/time.c b/payloads/libpayload/libc/time.c
index 28f2b3e..64de800 100644
--- a/payloads/libpayload/libc/time.c
+++ b/payloads/libpayload/libc/time.c
@@ -171,14 +171,15 @@
u64 timer_us(u64 base)
{
- static u32 hz, mult = USECS_PER_SEC;
+ static u64 hz;
+ static u32 mult = USECS_PER_SEC;
u32 div;
// Only check timer_hz once. Assume it doesn't change.
if (hz == 0) {
hz = timer_hz();
if (hz < mult) {
- printf("Timer frequency %" PRIu32 " is too low, "
+ printf("Timer frequency %" PRIu64 " is too low, "
"must be at least 1MHz.\n", hz);
halt();
}
--
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Hello Nico Huber, Yidi Lin,
I'd like you to do a code review.
Please visit
https://review.coreboot.org/c/coreboot/+/80319?usp=email
to review the following change.
Change subject: commonlib: Change GCD function to always use 64 bits
......................................................................
commonlib: Change GCD function to always use 64 bits
It seems that we have some applications where we need to calculate a GCD
in 64 bits. Now, we could instantiate the algorithm multiple times for
different bit width combinations to be able to use the most efficient
one for each problem... but considering that the function usually only
gets called once per callsite per stage, and that software emulation of
64-bit division on 32-bit systems doesn't take *that* long either, we
would probably usually be paying more time loading the second instance
of the function than we save with faster divisions. So let's just make
things easy and always do it in 64-bit and then nobody has to spend time
thinking on which version to call.
Change-Id: I028361444c4048a0d76ba4f80c7334a9d9983c87
Signed-off-by: Julius Werner <jwerner(a)chromium.org>
---
M payloads/libpayload/libc/getopt_long.c
M payloads/libpayload/libc/time.c
M src/arch/arm64/arch_timer.c
M src/commonlib/bsd/gcd.c
M src/commonlib/bsd/include/commonlib/bsd/gcd.h
M src/drivers/analogix/anx7625/anx7625.c
M src/northbridge/intel/ironlake/quickpath.c
M src/soc/rockchip/rk3288/clock.c
M src/soc/rockchip/rk3399/clock.c
M tests/commonlib/bsd/gcd-test.c
10 files changed, 28 insertions(+), 23 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/80319/1
diff --git a/payloads/libpayload/libc/getopt_long.c b/payloads/libpayload/libc/getopt_long.c
index 822ce96..c0303cf 100644
--- a/payloads/libpayload/libc/getopt_long.c
+++ b/payloads/libpayload/libc/getopt_long.c
@@ -122,7 +122,7 @@
*/
nnonopts = panonopt_end - panonopt_start;
nopts = opt_end - panonopt_end;
- ncycle = gcd32(nnonopts, nopts);
+ ncycle = gcd(nnonopts, nopts);
cyclelen = (opt_end - panonopt_start) / ncycle;
for (i = 0; i < ncycle; i++) {
diff --git a/payloads/libpayload/libc/time.c b/payloads/libpayload/libc/time.c
index c38dbfd..28f2b3e 100644
--- a/payloads/libpayload/libc/time.c
+++ b/payloads/libpayload/libc/time.c
@@ -182,7 +182,7 @@
"must be at least 1MHz.\n", hz);
halt();
}
- div = gcd32(hz, mult);
+ div = gcd(hz, mult);
hz /= div;
mult /= div;
}
diff --git a/src/arch/arm64/arch_timer.c b/src/arch/arm64/arch_timer.c
index 3eb5656..742b82c 100644
--- a/src/arch/arm64/arch_timer.c
+++ b/src/arch/arm64/arch_timer.c
@@ -19,7 +19,7 @@
if (tfreq == 0) {
tfreq = raw_read_cntfrq_el0();
mult = USECS_PER_SEC;
- div = gcd32(tfreq, mult);
+ div = gcd(tfreq, mult);
tfreq /= div;
mult /= div;
}
diff --git a/src/commonlib/bsd/gcd.c b/src/commonlib/bsd/gcd.c
index 92b601e..fbc8103 100644
--- a/src/commonlib/bsd/gcd.c
+++ b/src/commonlib/bsd/gcd.c
@@ -4,9 +4,9 @@
#include <commonlib/bsd/helpers.h>
#include <stdint.h>
-uint32_t gcd32(uint32_t a, uint32_t b)
+uint64_t gcd(uint64_t a, uint64_t b)
{
- uint32_t c;
+ uint64_t c;
if (a == 0 || b == 0)
return MAX(a, b);
diff --git a/src/commonlib/bsd/include/commonlib/bsd/gcd.h b/src/commonlib/bsd/include/commonlib/bsd/gcd.h
index 20949de..de02eb5 100644
--- a/src/commonlib/bsd/include/commonlib/bsd/gcd.h
+++ b/src/commonlib/bsd/include/commonlib/bsd/gcd.h
@@ -5,6 +5,6 @@
#include <stdint.h>
-uint32_t gcd32(uint32_t a, uint32_t b);
+uint64_t gcd(uint64_t a, uint64_t b);
#endif /* _COMMONLIB_BSD_GCD_H_ */
diff --git a/src/drivers/analogix/anx7625/anx7625.c b/src/drivers/analogix/anx7625/anx7625.c
index 8726ac0..4792d07 100644
--- a/src/drivers/analogix/anx7625/anx7625.c
+++ b/src/drivers/analogix/anx7625/anx7625.c
@@ -160,7 +160,7 @@
u32 a = *_a, b = *_b, old_a, old_b;
u32 denom = 1;
- gcd_num = gcd32(a, b);
+ gcd_num = gcd(a, b);
a /= gcd_num;
b /= gcd_num;
diff --git a/src/northbridge/intel/ironlake/quickpath.c b/src/northbridge/intel/ironlake/quickpath.c
index eb79347..aac852a 100644
--- a/src/northbridge/intel/ironlake/quickpath.c
+++ b/src/northbridge/intel/ironlake/quickpath.c
@@ -19,7 +19,7 @@
static u32 lcm(u32 a, u32 b)
{
- return (a * b) / gcd32(a, b);
+ return (a * b) / gcd(a, b);
}
struct stru1 {
@@ -49,7 +49,7 @@
int freq_max_reduced;
int freq3, freq4;
- g = gcd32(freq1, freq2);
+ g = gcd(freq1, freq2);
freq1_reduced = freq1 / g;
freq2_reduced = freq2 / g;
freq_min_reduced = MIN(freq1_reduced, freq2_reduced);
diff --git a/src/soc/rockchip/rk3288/clock.c b/src/soc/rockchip/rk3288/clock.c
index d52fa2a..5b1350a 100644
--- a/src/soc/rockchip/rk3288/clock.c
+++ b/src/soc/rockchip/rk3288/clock.c
@@ -453,7 +453,7 @@
1 << 15 | 0 << 12 | 1 << 8 | 0 << 0));
/* set frac divider */
- v = gcd32(GPLL_HZ, hz);
+ v = gcd(GPLL_HZ, hz);
n = (GPLL_HZ / v) & (0xffff);
d = (hz / v) & (0xffff);
assert(hz == GPLL_HZ / n * d);
diff --git a/src/soc/rockchip/rk3399/clock.c b/src/soc/rockchip/rk3399/clock.c
index fbff5a7..115d289 100644
--- a/src/soc/rockchip/rk3399/clock.c
+++ b/src/soc/rockchip/rk3399/clock.c
@@ -796,7 +796,7 @@
RK_CLRBITS(1 << 12 | 1 << 5 | 1 << 4 | 1 << 3));
/* set frac divider */
- v = gcd32(CPLL_HZ, hz);
+ v = gcd(CPLL_HZ, hz);
n = (CPLL_HZ / v) & (0xffff);
d = (hz / v) & (0xffff);
assert(hz == (u64)CPLL_HZ * d / n);
diff --git a/tests/commonlib/bsd/gcd-test.c b/tests/commonlib/bsd/gcd-test.c
index 13fad86..852a3fd 100644
--- a/tests/commonlib/bsd/gcd-test.c
+++ b/tests/commonlib/bsd/gcd-test.c
@@ -3,24 +3,29 @@
#include <commonlib/bsd/gcd.h>
#include <tests/test.h>
-static void test_gcd32(void **state)
+static void test_gcd(void **state)
{
- assert_int_equal(gcd32(17, 11), 1);
- assert_int_equal(gcd32(64, 36), 4);
- assert_int_equal(gcd32(90, 123), 3);
- assert_int_equal(gcd32(65536, 339584), 128);
- assert_int_equal(gcd32(1, 1), 1);
- assert_int_equal(gcd32(1, 123), 1);
- assert_int_equal(gcd32(123, 1), 1);
- assert_int_equal(gcd32(1, UINT32_MAX), 1);
- assert_int_equal(gcd32(UINT32_MAX, 1), 1);
- assert_int_equal(gcd32(UINT32_MAX, UINT32_MAX), UINT32_MAX);
+ assert_int_equal(gcd(17, 11), 1);
+ assert_int_equal(gcd(64, 36), 4);
+ assert_int_equal(gcd(90, 123), 3);
+ assert_int_equal(gcd(65536, 339584), 128);
+ assert_int_equal(gcd(1, 1), 1);
+ assert_int_equal(gcd(1, 123), 1);
+ assert_int_equal(gcd(123, 1), 1);
+ assert_int_equal(gcd(1, UINT32_MAX), 1);
+ assert_int_equal(gcd(UINT32_MAX, 1), 1);
+ assert_int_equal(gcd(UINT32_MAX, UINT32_MAX), UINT32_MAX);
+ assert_int_equal(gcd(1, UINT64_MAX), 1);
+ assert_int_equal(gcd(UINT64_MAX, 1), 1);
+ assert_int_equal(gcd(UINT64_MAX, UINT64_MAX), UINT64_MAX);
+ assert_int_equal(gcd((uint64_t)UINT32_MAX + 1, UINT64_MAX / 2 + 1),
+ (uint64_t)UINT32_MAX + 1);
}
int main(void)
{
const struct CMUnitTest tests[] = {
- cmocka_unit_test(test_gcd32),
+ cmocka_unit_test(test_gcd),
};
return cb_run_group_tests(tests, NULL, NULL);
--
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Change subject: mb/google/nissa/var/anraggar: Config DP AUX BIAS according to fw_config
......................................................................
Patch Set 11:
(1 comment)
File src/mainboard/google/brya/variants/anraggar/variant.c:
https://review.coreboot.org/c/coreboot/+/80259/comment/81527c53_0f6e0ab5 :
PS11, Line 26: config->tcss_aux_ori = 4;
> You should have two tcss_aux_ori values right?
C1(MB) hasn't retimer IC,so only bit 3 seted to 1:
b0100 = 4
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Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80300?usp=email )
Change subject: mb/google/brox: Initialize TCHSCR_RST_L to 0
......................................................................
Patch Set 3:
(1 comment)
File src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/80300/comment/896b9c30_54138f4c :
PS2, Line 176: register "generic.detect" = "1"
> As per my discussion with EE team, there is no harm in probing the touchscreen in the firmware. […]
Thanks for your help Karthik. I was able to detect touchscreen after your suggested changed.
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Hello Karthik Ramasubramanian, Nick Vaccaro, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/80300?usp=email
to look at the new patch set (#4).
Change subject: mb/google/brox: Initialize TCHSCR_RST_L to 0
......................................................................
mb/google/brox: Initialize TCHSCR_RST_L to 0
TCHSCR_RST_L signal was originally being configured to 1 in gpio.c but
this was causing some leakage. Configuring it to 0 initially in
romstage should fix this. Also, make sure that EN_PP3300_TCHSCR is
initialized in romstage as well.
BUG=b:322249892
BRANCH=None
TEST=Make brox boots and touchscreen is still working
Change-Id: I5bf1901a3a40a38237b950abcb758f96aebcc1cf
Signed-off-by: Shelley Chen <shchen(a)google.com>
---
M src/mainboard/google/brox/variants/baseboard/brox/gpio.c
1 file changed, 4 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/80300/4
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Hello Karthik Ramasubramanian, Nick Vaccaro, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/80300?usp=email
to look at the new patch set (#3).
The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: mb/google/brox: Initialize TCHSCR_RST_L/EN_PP3300_TCHSCR to 0
......................................................................
mb/google/brox: Initialize TCHSCR_RST_L/EN_PP3300_TCHSCR to 0
TCHSCR_RST_L signal was originally being configured to 1 in gpio.c but
this was causing some leakage. Configuring it to 0 initially in
romstage should fix this.
BUG=b:322249892
BRANCH=None
TEST=Make brox boots and touchscreen is still working
Change-Id: I5bf1901a3a40a38237b950abcb758f96aebcc1cf
Signed-off-by: Shelley Chen <shchen(a)google.com>
---
M src/mainboard/google/brox/variants/baseboard/brox/gpio.c
1 file changed, 4 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/80300/3
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