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Change subject: mb/google/nissa/var/anraggar: Config DP AUX BIAS according to fw_config
......................................................................
Patch Set 13:
(1 comment)
File src/mainboard/google/brya/variants/anraggar/variant.c:
https://review.coreboot.org/c/coreboot/+/80259/comment/9fd7c4b3_14dad013 :
PS12, Line 3: #include <chip.h>
> nit: alphabet order.
Done
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Change subject: mb/google/nissa/var/anraggar: Config DP AUX BIAS according to fw_config
......................................................................
mb/google/nissa/var/anraggar: Config DP AUX BIAS according to fw_config
EVT mini-build changes redriver IC from PS8745 to ANX7493, the
ANX7493 not support DP AUX BIAS, so connects DP AUX BIAS
of DB to SOC directly. Add DB_AUX_BIAS bit field to fw_config
for compatibility.
BUG=b:320235566
TEST=DP function of MB and DB workable
Change-Id: I53974ec7444912a63d0fe0a9303c9e5d6941f68d
Signed-off-by: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com>
---
M src/mainboard/google/brya/variants/anraggar/overridetree.cb
M src/mainboard/google/brya/variants/anraggar/variant.c
2 files changed, 34 insertions(+), 15 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/80259/13
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Change subject: mb/google/nissa/var/anraggar: Config DP AUX BIAS according to fw_config
......................................................................
Patch Set 12: Code-Review+2
(1 comment)
File src/mainboard/google/brya/variants/anraggar/variant.c:
https://review.coreboot.org/c/coreboot/+/80259/comment/881dede8_63f2dc82 :
PS12, Line 3: #include <chip.h>
nit: alphabet order.
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Change subject: mb/google/brox: Initialize TCHSCR_RST_L to 0
......................................................................
Patch Set 4: Code-Review+2
(1 comment)
Patchset:
PS4:
I still like to set all power related pins to DEEP. Since may have S5 leakage issue. But it's okay if PLTRST works.
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Change subject: mb/google/nissa: Skip locking for GPP_F15 GPIO
......................................................................
Patch Set 5:
(1 comment)
File src/mainboard/google/brya/variants/anraggar/gpio.c:
https://review.coreboot.org/c/coreboot/+/80316/comment/f0d08484_1a2c46a1 :
PS1, Line 54: PLTRST
> > @Eric PLTRST or others, could you give some suggestion? […]
got, thanks.
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I'd like you to reexamine a change. Please visit
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Code-Review+1 by Simon Yang, Verified+1 by build bot (Jenkins)
Change subject: mb/google/nissa/var/anraggar: Config DP AUX BIAS according to fw_config
......................................................................
mb/google/nissa/var/anraggar: Config DP AUX BIAS according to fw_config
EVT mini-build changes redriver IC from PS8745 to ANX7493, the
ANX7493 not support DP AUX BIAS, so connects DP AUX BIAS
of DB to SOC directly. Add DB_AUX_BIAS bit field to fw_config
for compatibility.
BUG=b:320235566
TEST=DP function of MB and DB workable
Change-Id: I53974ec7444912a63d0fe0a9303c9e5d6941f68d
Signed-off-by: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com>
---
M src/mainboard/google/brya/variants/anraggar/overridetree.cb
M src/mainboard/google/brya/variants/anraggar/variant.c
2 files changed, 34 insertions(+), 15 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/80259/12
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