coreboot-gerrit December 2024

coreboot-gerrit@coreboot.org

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[XS] Change in coreboot[main]: mb/google/rauru: Initialize PMICs in romstage
by Jarried Lin (Code Review) 25 Dec '24

25 Dec '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yidi Lin, Yu-Ping Wu. Hello Hung-Te Lin, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85755?usp=email to look at the new patch set (#4). Change subject: mb/google/rauru: Initialize PMICs in romstage ...................................................................... mb/google/rauru: Initialize PMICs in romstage BUG=b:317009620 TEST=Build pass, boot ok. Change-Id: Ia220db1d8d6d20e508f5e4d47054922012f6c417 Signed-off-by: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> --- M src/mainboard/google/rauru/romstage.c 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/85755/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/85755?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia220db1d8d6d20e508f5e4d47054922012f6c417 Gerrit-Change-Number: 85755 Gerrit-PatchSet: 4 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com>

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[M] Change in coreboot[main]: soc/mediatek/mt8196: Add MT6685 Clock IC driver
by Jarried Lin (Code Review) 25 Dec '24

25 Dec '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yu-Ping Wu. Hello Hope Wang, Hung-Te Lin, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85734?usp=email to look at the new patch set (#6). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/mediatek/mt8196: Add MT6685 Clock IC driver ...................................................................... soc/mediatek/mt8196: Add MT6685 Clock IC driver Add MT6685 initial settings and ADC init settings to support Thermal Information Acquisition (TIA), TIA will read thermal info in HW. TEST=Build pass BUG=b:317009620 Change-Id: I26ae4f416202f04a8030259c49e009b19a60712e Signed-off-by: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> --- A src/soc/mediatek/common/include/soc/mt6685.h A src/soc/mediatek/common/mt6685.c M src/soc/mediatek/mt8196/Makefile.mk A src/soc/mediatek/mt8196/mt6685.c M src/soc/mediatek/mt8196/pmif_init.c 5 files changed, 198 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/85734/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/85734?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I26ae4f416202f04a8030259c49e009b19a60712e Gerrit-Change-Number: 85734 Gerrit-PatchSet: 6 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com>

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[XS] Change in coreboot[main]: mb/google/rauru: Initialize PMICs in romstage
by Jarried Lin (Code Review) 25 Dec '24

25 Dec '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yidi Lin, Yu-Ping Wu. Hello Hung-Te Lin, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85755?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Code-Review+1 by Yidi Lin, Verified+1 by build bot (Jenkins) Change subject: mb/google/rauru: Initialize PMICs in romstage ...................................................................... mb/google/rauru: Initialize PMICs in romstage BUG=b:317009620 TEST=Build pass, boot ok. Change-Id: Ia220db1d8d6d20e508f5e4d47054922012f6c417 Signed-off-by: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> --- M src/mainboard/google/rauru/romstage.c 1 file changed, 8 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/85755/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/85755?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia220db1d8d6d20e508f5e4d47054922012f6c417 Gerrit-Change-Number: 85755 Gerrit-PatchSet: 3 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com>

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[XL] Change in coreboot[main]: [test] upgrade GCC to 15-20241215 Snapshot
by Elyes Haouas (Code Review) 25 Dec '24

25 Dec '24

Attention is currently required from: Christian Walter, Martin L Roth, Maximilian Brune, Philipp Hug, ron minnich. Hello Christian Walter, Martin L Roth, Maximilian Brune, Philipp Hug, build bot (Jenkins), ron minnich, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85729?usp=email to look at the new patch set (#10). Change subject: [test] upgrade GCC to 15-20241215 Snapshot ...................................................................... [test] upgrade GCC to 15-20241215 Snapshot And remove unmantained riscv & opensbi Change-Id: I644fae70488c26ba833c2332059e805e50764c2a Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M .gitmodules D 3rdparty/opensbi M MAINTAINERS M Makefile.mk D configs/config.emulation_qemu_riscv_rv64 D configs/config.sifive_hifive-unleashed.opensbi M payloads/Kconfig M payloads/external/LinuxBoot/Kconfig M payloads/external/LinuxBoot/Kconfig.name M payloads/external/LinuxBoot/Makefile D payloads/external/LinuxBoot/riscv/defconfig-32 D payloads/external/LinuxBoot/riscv/defconfig-64 D payloads/external/LinuxBoot/riscv/kernel_fdt_lzma.its M payloads/external/LinuxBoot/targets/u-root.mk M payloads/external/Makefile.mk M payloads/external/linux/Kconfig.name D src/arch/riscv/Kconfig D src/arch/riscv/Makefile.mk D src/arch/riscv/arch_timer.c D src/arch/riscv/boot.c D src/arch/riscv/bootblock.S D src/arch/riscv/fit_payload.c D src/arch/riscv/fp_asm.S D src/arch/riscv/include/arch/barrier.h D src/arch/riscv/include/arch/boot.h D src/arch/riscv/include/arch/byteorder.h D src/arch/riscv/include/arch/cache.h D src/arch/riscv/include/arch/cbconfig.h D src/arch/riscv/include/arch/cpu.h D src/arch/riscv/include/arch/encoding.h D src/arch/riscv/include/arch/errno.h D src/arch/riscv/include/arch/exception.h D src/arch/riscv/include/arch/header.ld D src/arch/riscv/include/arch/hlt.h D src/arch/riscv/include/arch/io.h D src/arch/riscv/include/arch/memlayout.h D src/arch/riscv/include/arch/mmio.h D src/arch/riscv/include/arch/pmp.h D src/arch/riscv/include/arch/smp/atomic.h D src/arch/riscv/include/arch/smp/smp.h D src/arch/riscv/include/arch/smp/spinlock.h D src/arch/riscv/include/bits.h D src/arch/riscv/include/mcall.h D src/arch/riscv/include/sbi.h D src/arch/riscv/include/vm.h D src/arch/riscv/mcall.c D src/arch/riscv/misc.c D src/arch/riscv/opensbi.c D src/arch/riscv/payload.c D src/arch/riscv/pmp.c D src/arch/riscv/ramstage.S D src/arch/riscv/romstage.S D src/arch/riscv/sbi.c D src/arch/riscv/smp.c D src/arch/riscv/tables.c D src/arch/riscv/trap_handler.c D src/arch/riscv/trap_util.S D src/arch/riscv/virtual_memory.c M src/commonlib/bsd/lz4_wrapper.c M src/drivers/uart/Kconfig M src/drivers/uart/Makefile.mk D src/drivers/uart/sifive.c M src/include/acpi/acpi.h M src/include/bootmem.h M src/include/program_loading.h M src/include/rules.h M src/lib/bootmem.c M src/lib/libgcc.c M src/mainboard/emulation/Kconfig D src/mainboard/emulation/qemu-riscv/Kconfig D src/mainboard/emulation/qemu-riscv/Kconfig.name D src/mainboard/emulation/qemu-riscv/Makefile.mk D src/mainboard/emulation/qemu-riscv/board_info.txt D src/mainboard/emulation/qemu-riscv/cbmem.c D src/mainboard/emulation/qemu-riscv/chip.c D src/mainboard/emulation/qemu-riscv/clint.c D src/mainboard/emulation/qemu-riscv/devicetree.cb D src/mainboard/emulation/qemu-riscv/include/mainboard/addressmap.h D src/mainboard/emulation/qemu-riscv/mainboard.c D src/mainboard/emulation/qemu-riscv/memlayout.ld D src/mainboard/emulation/qemu-riscv/rom_media.c D src/mainboard/emulation/qemu-riscv/romstage.c D src/mainboard/emulation/qemu-riscv/uart.c D src/mainboard/emulation/spike-riscv/Kconfig D src/mainboard/emulation/spike-riscv/Kconfig.name D src/mainboard/emulation/spike-riscv/Makefile.mk D src/mainboard/emulation/spike-riscv/board_info.txt D src/mainboard/emulation/spike-riscv/clint.c D src/mainboard/emulation/spike-riscv/devicetree.cb D src/mainboard/emulation/spike-riscv/mainboard.c D src/mainboard/emulation/spike-riscv/memlayout.ld D src/mainboard/emulation/spike-riscv/rom_media.c D src/mainboard/emulation/spike-riscv/romstage.c D src/mainboard/emulation/spike-riscv/uart.c D src/mainboard/sifive/Kconfig D src/mainboard/sifive/Kconfig.name D src/mainboard/sifive/hifive-unleashed/Kconfig D src/mainboard/sifive/hifive-unleashed/Kconfig.name D src/mainboard/sifive/hifive-unleashed/Makefile.mk D src/mainboard/sifive/hifive-unleashed/board_info.txt D src/mainboard/sifive/hifive-unleashed/devicetree.cb D src/mainboard/sifive/hifive-unleashed/fixup_fdt.c D src/mainboard/sifive/hifive-unleashed/fu540-c000.dtsi D src/mainboard/sifive/hifive-unleashed/hifive-unleashed-a00.dts D src/mainboard/sifive/hifive-unleashed/mainboard.c D src/mainboard/sifive/hifive-unleashed/media.c D src/mainboard/sifive/hifive-unleashed/romstage.c D src/mainboard/sifive/hifive-unmatched/Kconfig D src/mainboard/sifive/hifive-unmatched/Kconfig.name D src/mainboard/sifive/hifive-unmatched/Makefile.mk D src/mainboard/sifive/hifive-unmatched/board_info.txt D src/mainboard/sifive/hifive-unmatched/cbfs_spi.c D src/mainboard/sifive/hifive-unmatched/devicetree.cb D src/mainboard/sifive/hifive-unmatched/fixup_fdt.c D src/mainboard/sifive/hifive-unmatched/fu740-c000.dtsi D src/mainboard/sifive/hifive-unmatched/hifive-unmatched-a00-mod.dts D src/mainboard/sifive/hifive-unmatched/hifive-unmatched-a00.dts D src/mainboard/sifive/hifive-unmatched/mainboard.c D src/mainboard/sifive/hifive-unmatched/romstage.c D src/soc/sifive/fu540/Kconfig D src/soc/sifive/fu540/Makefile.mk D src/soc/sifive/fu540/bootblock.c D src/soc/sifive/fu540/cbmem.c D src/soc/sifive/fu540/chip.c D src/soc/sifive/fu540/clint.c D src/soc/sifive/fu540/clock.c D src/soc/sifive/fu540/ddrregs.h D src/soc/sifive/fu540/include/soc/addressmap.h D src/soc/sifive/fu540/include/soc/clock.h D src/soc/sifive/fu540/include/soc/otp.h D src/soc/sifive/fu540/include/soc/sdram.h D src/soc/sifive/fu540/include/soc/spi.h D src/soc/sifive/fu540/memlayout.ld D src/soc/sifive/fu540/otp.c D src/soc/sifive/fu540/regconfig-ctl.h D src/soc/sifive/fu540/regconfig-phy.h D src/soc/sifive/fu540/sdram.c D src/soc/sifive/fu540/spi.c D src/soc/sifive/fu540/spi_internal.h D src/soc/sifive/fu540/uart.c D src/soc/sifive/fu540/ux00ddr.h D src/soc/sifive/fu740/Kconfig D src/soc/sifive/fu740/Makefile.mk D src/soc/sifive/fu740/TODO D src/soc/sifive/fu740/cbmem.c D src/soc/sifive/fu740/chip.c D src/soc/sifive/fu740/clint.c D src/soc/sifive/fu740/clock.c D src/soc/sifive/fu740/ddrregs.c D src/soc/sifive/fu740/gpio.c D src/soc/sifive/fu740/include/soc/addressmap.h D src/soc/sifive/fu740/include/soc/clock.h D src/soc/sifive/fu740/include/soc/gpio.h D src/soc/sifive/fu740/include/soc/otp.h D src/soc/sifive/fu740/include/soc/sdram.h D src/soc/sifive/fu740/include/soc/spi.h D src/soc/sifive/fu740/memlayout.ld D src/soc/sifive/fu740/otp.c D src/soc/sifive/fu740/sdram.c D src/soc/sifive/fu740/spi.c D src/soc/sifive/fu740/spi_internal.h D src/soc/sifive/fu740/uart.c D src/soc/ucb/riscv/Kconfig D src/soc/ucb/riscv/Makefile.mk D src/soc/ucb/riscv/cbmem.c D src/soc/ucb/riscv/chip.c M util/crossgcc/buildgcc D util/crossgcc/patches/gcc-14.2.0_rv32iafc.patch R util/crossgcc/patches/gcc-15-20241222_asan_shadow_offset_callback.patch R util/crossgcc/patches/gcc-15-20241222_gnat.patch R util/crossgcc/patches/gcc-15-20241222_libcpp.patch R util/crossgcc/patches/gcc-15-20241222_libgcc.patch R util/crossgcc/patches/gcc-15-20241222_musl_poisoned_calloc.patch D util/crossgcc/sum/gcc-14.2.0.tar.xz.cksum A util/crossgcc/sum/gcc-15-20241222.tar.xz.cksum D util/riscv/description.md D util/riscv/make-spike-elf.sh D util/riscv/sifive-gpt.py D util/riscv/spike-elf.ld 179 files changed, 12 insertions(+), 13,647 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/85729/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/85729?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I644fae70488c26ba833c2332059e805e50764c2a Gerrit-Change-Number: 85729 Gerrit-PatchSet: 10 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: ron minnich <rminnich(a)gmail.com>

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[S] Change in coreboot[main]: Doc/soc/amd/family15h: Fix URLs to AMD documents
by Maxim (Code Review) 25 Dec '24

25 Dec '24

Attention is currently required from: Daniel Maslowski, Felix Singer, Nicholas Sudsgaard. Maxim has posted comments on this change by Daniel Maslowski. ( https://review.coreboot.org/c/coreboot/+/84815?usp=email ) Change subject: Doc/soc/amd/family15h: Fix URLs to AMD documents ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84815?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibb478b56d02842dc05475235b0fe80ab6c4e7d04 Gerrit-Change-Number: 84815 Gerrit-PatchSet: 3 Gerrit-Owner: Daniel Maslowski <info(a)orangecms.org> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Maxim <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Daniel Maslowski <info(a)orangecms.org> Gerrit-Attention: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Comment-Date: Wed, 25 Dec 2024 10:01:56 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in blobs[main]: soc/mediatek/mt8196: Add GPUEB firmware v1.0
by Yidi Lin (Code Review) 25 Dec '24

25 Dec '24

Attention is currently required from: Andy Hsu, Jarried Lin, Yu-Ping Wu. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/blobs/+/85763?usp=email ) Change subject: soc/mediatek/mt8196: Add GPUEB firmware v1.0 ...................................................................... Patch Set 1: Code-Review+1 (2 comments) File soc/mediatek/mt8196/README.md: https://review.coreboot.org/c/blobs/+/85763/comment/fc047411_26a61eca?usp=e… : PS1, Line 203: `tinysys-gpueb-RV33_A.mkpt_fw.img` to the SRAM of GPUEB. move to the next line https://review.coreboot.org/c/blobs/+/85763/comment/f609eb3c_4bd29a3a?usp=e… : PS1, Line 207: reset to trigger GPUEB. move to the next line -- To view, visit https://review.coreboot.org/c/blobs/+/85763?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: blobs Gerrit-Branch: main Gerrit-Change-Id: I470f1575beea481cac2dcb5f3eb77587739ff2dc Gerrit-Change-Number: 85763 Gerrit-PatchSet: 1 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Andy Hsu <andy.hsu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Andy Hsu <andy.hsu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Wed, 25 Dec 2024 09:54:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[XL] Change in coreboot[main]: soc/mediatek/mt8196: Add PMIC MT6316 driver
by Yidi Lin (Code Review) 25 Dec '24

25 Dec '24

Yidi Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85630?usp=email ) Change subject: soc/mediatek/mt8196: Add PMIC MT6316 driver ...................................................................... soc/mediatek/mt8196: Add PMIC MT6316 driver Add MT6316 driver in SoC folder. TEST=Build pass BUG=b:317009620 Change-Id: I39e91d64e77cff03281845dfbea565e6ddf748f6 Signed-off-by: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85630 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Reviewed-by: Yidi Lin <yidilin(a)google.com> --- A src/soc/mediatek/common/include/soc/mt6316.h A src/soc/mediatek/common/mt6316.c M src/soc/mediatek/mt8196/Makefile.mk A src/soc/mediatek/mt8196/mt6316.c 4 files changed, 1,155 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved Yidi Lin: Looks good to me, approved diff --git a/src/soc/mediatek/common/include/soc/mt6316.h b/src/soc/mediatek/common/include/soc/mt6316.h new file mode 100644 index 0000000..920cb34 --- /dev/null +++ b/src/soc/mediatek/common/include/soc/mt6316.h @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +#ifndef __SOC_MEDIATEK_MT6316_H__ +#define __SOC_MEDIATEK_MT6316_H__ + +#include <soc/spmi.h> +#include <types.h> + +struct mt6316_setting { + unsigned short addr; + unsigned short val; + unsigned short mask; + unsigned char shift; +}; + +enum { + MT6316_BUCK_1 = 0, + MT6316_BUCK_2, + MT6316_BUCK_3, + MT6316_BUCK_4, + MT6316_BUCK_MAX, +}; + +enum { + MT6316_PMIC_TOP_RST_MISC = 0x138, + MT6316_PMIC_TOP_RST_MISC_SET = 0x139, + MT6316_PMIC_TOP_RST_MISC_CLR = 0x13A, + MT6316_PMIC_SWCID_H_ADDR = 0x20B, + MT6316_PMIC_TEST_CON9 = 0x222, + MT6316_PMIC_PLT_DIG_WPK = 0x3B1, + MT6316_PMIC_PLT_DIG_WPK_H = 0x3B2, + MT6316_BUCK_TOP_ELR0 = 0x1448, + MT6316_BUCK_TOP_ELR1 = 0x1449, + MT6316_BUCK_TOP_ELR2 = 0x144A, + MT6316_BUCK_TOP_ELR3 = 0x144B, + MT6316_BUCK_TOP_ELR4 = 0x144C, + MT6316_BUCK_TOP_ELR5 = 0x144D, + MT6316_BUCK_TOP_ELR6 = 0x144E, + MT6316_BUCK_TOP_ELR7 = 0x144F, + MT6316_BUCK_VBUCK1_DBG0 = 0x14A0, + MT6316_BUCK_VBUCK1_DBG1 = 0x14A1, + MT6316_BUCK_VBUCK3_DBG0 = 0x15A0, + MT6316_BUCK_VBUCK3_DBG1 = 0x15A1, + MT6316_BUCK_TOP_4PHASE_TOP_ANA_CON0 = 0x1688, +}; + +void mt6316_init(void); +void mt6316_buck_set_voltage(enum spmi_slave slvid, u32 buck_id, u32 buck_uv); +u32 mt6316_buck_get_voltage(enum spmi_slave slvid, u32 buck_id); +void mt6316_init_setting(void); +void mt6316_write_field(enum spmi_slave slvid, u32 reg, u32 val, u32 mask, u32 shift); +void mt6316_buck_enable(enum spmi_slave slvid, u32 buck_id, bool enable); +bool mt6316_buck_is_enabled(enum spmi_slave slvid, u32 buck_id); + +#endif /* __SOC_MEDIATEK_MT6316_H__ */ diff --git a/src/soc/mediatek/common/mt6316.c b/src/soc/mediatek/common/mt6316.c new file mode 100644 index 0000000..797ae3e --- /dev/null +++ b/src/soc/mediatek/common/mt6316.c @@ -0,0 +1,198 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +#include <assert.h> +#include <console/console.h> +#include <delay.h> +#include <soc/mt6316.h> +#include <soc/pmif.h> +#include <soc/pmif_spmi.h> + +static struct pmif *pmif_arb; +static const u32 mt6316_slave_id[] = { + SPMI_SLAVE_6, SPMI_SLAVE_7, SPMI_SLAVE_8, SPMI_SLAVE_15 +}; + +static u8 mt6316_read8(enum spmi_slave slvid, u32 reg) +{ + u32 rdata = 0; + + assert(pmif_arb); + pmif_arb->read(pmif_arb, slvid, reg, &rdata); + + return (u8)rdata; +} + +static void mt6316_write8(enum spmi_slave slvid, u32 reg, u8 data) +{ + assert(pmif_arb); + pmif_arb->write(pmif_arb, slvid, reg, data); +} + +void mt6316_write_field(enum spmi_slave slvid, u32 reg, u32 val, u32 mask, u32 shift) +{ + assert(pmif_arb); + return pmif_arb->write_field(pmif_arb, slvid, reg, val, mask, shift); +} + +static u32 mt6316_read_field(enum spmi_slave slvid, u32 reg, u32 mask, u32 shift) +{ + assert(pmif_arb); + return pmif_arb->read_field(pmif_arb, slvid, reg, mask, shift); +} + +static void mt6316_wdt_enable(enum spmi_slave slvid) +{ + u8 reg_val; + + /* read the current wdt setting */ + reg_val = mt6316_read8(slvid, MT6316_PMIC_TOP_RST_MISC); + printk(BIOS_INFO, "[%s]S%u TOP_RST_MISC=%#x\n", __func__, slvid, reg_val); + mt6316_write8(slvid, MT6316_PMIC_PLT_DIG_WPK, 0xE9); + mt6316_write8(slvid, MT6316_PMIC_PLT_DIG_WPK_H, 0xE6); + mt6316_write8(slvid, MT6316_PMIC_TOP_RST_MISC_SET, 0x2); + mt6316_write8(slvid, MT6316_PMIC_TOP_RST_MISC_SET, 0x1); + mt6316_write8(slvid, MT6316_PMIC_TOP_RST_MISC_SET, 0x8); + udelay(50); + mt6316_write8(slvid, MT6316_PMIC_TOP_RST_MISC_CLR, 0x8); + mt6316_write8(slvid, MT6316_PMIC_PLT_DIG_WPK, 0); + mt6316_write8(slvid, MT6316_PMIC_PLT_DIG_WPK_H, 0); + reg_val = mt6316_read8(slvid, MT6316_PMIC_TOP_RST_MISC); + printk(BIOS_INFO, "[%s]S%u TOP_RST_MISC=%#x\n", __func__, slvid, reg_val); +} + +void mt6316_buck_set_voltage(enum spmi_slave slvid, u32 buck_id, u32 buck_uv) +{ + u32 vol_reg, vol_reg_l, vol_val; + + assert(pmif_arb); + + switch (buck_id) { + case MT6316_BUCK_1: + vol_reg = MT6316_BUCK_TOP_ELR0; + vol_reg_l = MT6316_BUCK_TOP_ELR1; + break; + case MT6316_BUCK_3: + vol_reg = MT6316_BUCK_TOP_ELR4; + vol_reg_l = MT6316_BUCK_TOP_ELR5; + break; + default: + printk(BIOS_ERR, "%s: Unknown buck_id %u\n", __func__, buck_id); + return; + }; + + vol_val = buck_uv / 2500; + mt6316_write8(slvid, vol_reg_l, vol_val & 0x1); + mt6316_write8(slvid, vol_reg, vol_val >> 1); + udelay(200); + printk(BIOS_INFO, "%s: %u, %#x, %u\n", __func__, buck_id, vol_val, buck_uv); +} + +u32 mt6316_buck_get_voltage(enum spmi_slave slvid, u32 buck_id) +{ + u8 vol; + u32 vol_reg, vol_reg_l, vol_l, vol_val; + + assert(pmif_arb); + + switch (buck_id) { + case MT6316_BUCK_1: + vol_reg = MT6316_BUCK_VBUCK1_DBG0; + vol_reg_l = MT6316_BUCK_VBUCK1_DBG1; + break; + case MT6316_BUCK_3: + vol_reg = MT6316_BUCK_VBUCK3_DBG0; + vol_reg_l = MT6316_BUCK_VBUCK3_DBG1; + break; + default: + printk(BIOS_ERR, "%s: Unknown buck_id %u\n", __func__, buck_id); + return 0; + }; + + vol = mt6316_read8(slvid, vol_reg); + vol_l = mt6316_read_field(slvid, vol_reg_l, 0x1, 0); + vol_val = vol * 5000 + vol_l * 2500; + printk(BIOS_INFO, "%s: %u, %#x, %#x, %u\n", __func__, buck_id, vol, vol_l, + vol_val); + return vol_val; +} + +void mt6316_buck_enable(enum spmi_slave slvid, u32 buck_id, bool enable) +{ + u32 mod_shift; + + assert(pmif_arb); + + switch (buck_id) { + case MT6316_BUCK_1: + mod_shift = 0; + break; + case MT6316_BUCK_3: + mod_shift = 2; + break; + default: + printk(BIOS_ERR, "%s: Unknown buck_id %u\n", __func__, buck_id); + return; + }; + + mt6316_write_field(slvid, MT6316_BUCK_TOP_4PHASE_TOP_ANA_CON0, + enable, 0x1, mod_shift); + udelay(100); + printk(BIOS_INFO, "%s: %u, %u\n", __func__, buck_id, enable); +} + +bool mt6316_buck_is_enabled(enum spmi_slave slvid, u32 buck_id) +{ + u32 mod_shift, mod; + + assert(pmif_arb); + + switch (buck_id) { + case MT6316_BUCK_1: + mod_shift = 0; + break; + case MT6316_BUCK_3: + mod_shift = 2; + break; + default: + printk(BIOS_ERR, "%s: Unknown buck_id %u\n", __func__, buck_id); + return false; + }; + + mod = mt6316_read_field(slvid, MT6316_BUCK_TOP_4PHASE_TOP_ANA_CON0, 0x1, mod_shift); + printk(BIOS_INFO, "%s: %u, %u\n", __func__, buck_id, mod); + return !!mod; +} + +static void mt6316_set_all_test_con9(void) +{ + for (int i = 0; i < ARRAY_SIZE(mt6316_slave_id); i++) + mt6316_write8(mt6316_slave_id[i], MT6316_PMIC_TEST_CON9, 0x20); +} + +static void init_pmif_arb(void) +{ + if (!pmif_arb) { + pmif_arb = get_pmif_controller(PMIF_SPMI, SPMI_MASTER_0); + assert(pmif_arb); + } + + if (pmif_arb->is_pmif_init_done(pmif_arb)) + die("ERROR - Failed to initialize pmif spmi"); + + for (int i = 0; i < ARRAY_SIZE(mt6316_slave_id); i++) + printk(BIOS_INFO, "%s: MT6316_%u: CHIP ID = %#x\n", __func__, + mt6316_slave_id[i], + mt6316_read_field(mt6316_slave_id[i], + MT6316_PMIC_SWCID_H_ADDR, 0xFF, 0x0)); +} + +void mt6316_init(void) +{ + init_pmif_arb(); + + for (int i = 0; i < ARRAY_SIZE(mt6316_slave_id); i++) + mt6316_wdt_enable(mt6316_slave_id[i]); + + mt6316_init_setting(); + mt6316_set_all_test_con9(); +} diff --git a/src/soc/mediatek/mt8196/Makefile.mk b/src/soc/mediatek/mt8196/Makefile.mk index e09ea3a..7fe0889 100644 --- a/src/soc/mediatek/mt8196/Makefile.mk +++ b/src/soc/mediatek/mt8196/Makefile.mk @@ -32,6 +32,7 @@ romstage-y += ../common/memory.c memory.c romstage-y += ../common/memory_test.c romstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c +romstage-y += ../common/mt6316.c mt6316.c romstage-y += ../common/mt6363.c mt6363.c romstage-y += ../common/mt6373.c mt6373.c romstage-y += ../common/mtk_fsp.c diff --git a/src/soc/mediatek/mt8196/mt6316.c b/src/soc/mediatek/mt8196/mt6316.c new file mode 100644 index 0000000..2cb0248 --- /dev/null +++ b/src/soc/mediatek/mt8196/mt6316.c @@ -0,0 +1,901 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +/* + * These values are used by MediaTek internally. + * We can find these registers in "MT6316_PMIC_Design_Notice_for_MT8196G_V0.2". + * The setting values are provided by MediaTek designers. + */ + +#include <console/console.h> +#include <soc/mt6316.h> + +static const struct mt6316_setting init_setting_s6[] = { + /* Disable magic key protection */ + {0x3B1, 0xE9, 0xFF, 0}, + {0x3B2, 0xE6, 0xFF, 0}, + {0x3A8, 0xE9, 0xFF, 0}, + {0x3A9, 0xE6, 0xFF, 0}, + {0xA15, 0x29, 0xFF, 0}, + {0xA16, 0x47, 0xFF, 0}, + {0x141C, 0x43, 0xFF, 0}, + {0x141D, 0x55, 0xFF, 0}, + {0x3AA, 0xDC, 0xFF, 0}, + {0x3AB, 0xF1, 0xFF, 0}, + /* Init setting */ + {0x13, 0x7, 0xFF, 0}, + {0x16, 0x12, 0xFF, 0}, + {0x17, 0x0, 0xFF, 0}, + {0x8A, 0x6, 0xF, 0}, + {0xA1, 0xC, 0xC, 0}, + {0xA2, 0x10, 0x10, 0}, + {0x10C, 0xC, 0xC, 0}, + {0x12C, 0x1, 0x1, 0}, + {0x140, 0x30, 0x30, 0}, + {0x142, 0x30, 0xFF, 0}, + {0x991, 0x11, 0xFF, 0}, + {0x196, 0x1, 0x1, 0}, + {0x197, 0x10, 0x10, 0}, + {0x19A, 0x1, 0x1, 0}, + {0x19B, 0x10, 0x10, 0}, + {0x217, 0x22, 0x22, 0}, + {0x219, 0x1F, 0x1F, 0}, + {0x223, 0x20, 0x20, 0}, + {0x413, 0x7, 0xFF, 0}, + {0x416, 0x12, 0xFF, 0}, + {0x417, 0x0, 0x7, 0}, + {0x988, 0x0, 0x20, 0}, + {0x98C, 0xB0, 0xFF, 0}, + {0x994, 0x0, 0xFF, 0}, + {0xA13, 0x10, 0x10, 0}, + {0xA1F, 0x80, 0x80, 0}, + {0x1452, 0x0, 0xFF, 0}, + {0x1457, 0x22, 0xFF, 0}, + {0x1458, 0x22, 0xFF, 0}, + {0x148A, 0x0, 0x3, 0}, + {0x148F, 0x2, 0x3, 0}, + {0x1492, 0x40, 0x70, 0}, + {0x150A, 0x0, 0x3, 0}, + {0x150F, 0x2, 0x3, 0}, + {0x1512, 0x40, 0x70, 0}, + {0x158A, 0x0, 0x3, 0}, + {0x158F, 0x2, 0x3, 0}, + {0x1592, 0x40, 0x70, 0}, + {0x160A, 0x0, 0x3, 0}, + {0x160F, 0x2, 0x3, 0}, + {0x1612, 0x40, 0x70, 0}, + {0x1729, 0x18, 0x18, 0}, + {0x17A9, 0x18, 0x18, 0}, + {0x1829, 0x18, 0x18, 0}, + {0x18A9, 0x18, 0x18, 0}, + {0x98, 0x2, 0x7, 0}, + {0xA1F, 0xC, 0xC, 0}, + {0xA21, 0x21, 0xFF, 0}, + {0xA23, 0xF0, 0xF0, 0}, + {0xA28, 0x21, 0xFF, 0}, + {0xA29, 0x21, 0xFF, 0}, + {0xA2A, 0x1B, 0xFF, 0}, + {0xA2B, 0x21, 0xFF, 0}, + {0x1440, 0x0, 0xA, 0}, + {0x1487, 0x55, 0xFF, 0}, + {0x148A, 0xD, 0xF, 0}, + {0x148C, 0x3, 0x3, 0}, + {0x148D, 0x28, 0x7F, 0}, + {0x148E, 0x7, 0x7F, 0}, + {0x1490, 0x2, 0x3, 0}, + {0x1491, 0x19, 0x7F, 0}, + {0x1507, 0x55, 0xFF, 0}, + {0x150A, 0xD, 0xF, 0}, + {0x150C, 0x3, 0x3, 0}, + {0x150D, 0x28, 0x7F, 0}, + {0x150E, 0x7, 0x7F, 0}, + {0x1510, 0x2, 0x3, 0}, + {0x1511, 0x19, 0x7F, 0}, + {0x1587, 0xD2, 0xFF, 0}, + {0x158A, 0xD, 0xF, 0}, + {0x158D, 0xD, 0x7F, 0}, + {0x158E, 0x7, 0x7F, 0}, + {0x1590, 0x2, 0x3, 0}, + {0x1591, 0x19, 0x7F, 0}, + {0x1607, 0x55, 0xFF, 0}, + {0x160A, 0xD, 0xF, 0}, + {0x160C, 0x3, 0x3, 0}, + {0x160D, 0x28, 0x7F, 0}, + {0x160E, 0x7, 0x7F, 0}, + {0x1610, 0x2, 0x3, 0}, + {0x1611, 0x19, 0x7F, 0}, + {0x1688, 0x0, 0x1F, 0}, + {0x1689, 0x10, 0x7F, 0}, + {0x168A, 0x0, 0xFF, 0}, + {0x168B, 0x1, 0xFF, 0}, + {0x168C, 0x5, 0x3F, 0}, + {0x168D, 0x9, 0xFF, 0}, + {0x168E, 0xA0, 0xFF, 0}, + {0x1708, 0xD1, 0xFF, 0}, + {0x1709, 0xFC, 0xFF, 0}, + {0x170A, 0x92, 0xFF, 0}, + {0x170B, 0x0, 0x3, 0}, + {0x170C, 0x4C, 0x7F, 0}, + {0x170D, 0x0, 0x7F, 0}, + {0x170E, 0x30, 0x3F, 0}, + {0x170F, 0x9F, 0xFF, 0}, + {0x1710, 0x29, 0x3F, 0}, + {0x1711, 0x0, 0x3F, 0}, + {0x1712, 0x0, 0xFF, 0}, + {0x1713, 0x9C, 0x9C, 0}, + {0x1714, 0x1, 0x7F, 0}, + {0x1715, 0xFF, 0xFF, 0}, + {0x1716, 0x8E, 0xFF, 0}, + {0x1717, 0x3B, 0xFF, 0}, + {0x1718, 0x6A, 0xFF, 0}, + {0x1719, 0x80, 0xFF, 0}, + {0x171A, 0x8, 0x7F, 0}, + {0x171B, 0x1, 0x3F, 0}, + {0x171C, 0x3, 0xF, 0}, + {0x171D, 0x58, 0x7F, 0}, + {0x171E, 0xD, 0x1F, 0}, + {0x1738, 0x4, 0x1F, 0}, + {0x173B, 0x7, 0x1F, 0}, + {0x1788, 0xD1, 0xFF, 0}, + {0x1789, 0xFC, 0xFF, 0}, + {0x178A, 0x92, 0xFF, 0}, + {0x178B, 0x0, 0x3, 0}, + {0x178C, 0x4C, 0x7F, 0}, + {0x178D, 0x0, 0x7F, 0}, + {0x178E, 0x30, 0x3F, 0}, + {0x178F, 0x9F, 0xFF, 0}, + {0x1790, 0x29, 0x3F, 0}, + {0x1791, 0x0, 0x3F, 0}, + {0x1792, 0x0, 0xFF, 0}, + {0x1793, 0xDC, 0xDC, 0}, + {0x1794, 0x0, 0x3F, 0}, + {0x1795, 0xFF, 0xFF, 0}, + {0x1796, 0x8E, 0xFF, 0}, + {0x1797, 0x3B, 0xFF, 0}, + {0x1798, 0x6A, 0xFF, 0}, + {0x1799, 0x80, 0xFF, 0}, + {0x179A, 0x8, 0x7F, 0}, + {0x179B, 0x1, 0x3F, 0}, + {0x179C, 0x3, 0xF, 0}, + {0x179D, 0x58, 0x7F, 0}, + {0x179E, 0xD, 0x1F, 0}, + {0x17BB, 0x7, 0x1F, 0}, + {0x1808, 0xB1, 0xFF, 0}, + {0x1809, 0xCC, 0xFF, 0}, + {0x180A, 0x92, 0xFF, 0}, + {0x180B, 0x0, 0x3, 0}, + {0x180C, 0x54, 0x7F, 0}, + {0x180D, 0x0, 0x7F, 0}, + {0x180E, 0x20, 0x3F, 0}, + {0x180F, 0x9F, 0xFF, 0}, + {0x1810, 0x29, 0x3F, 0}, + {0x1811, 0x0, 0x3F, 0}, + {0x1812, 0x0, 0xFF, 0}, + {0x1813, 0xDC, 0xDC, 0}, + {0x1814, 0x0, 0x3F, 0}, + {0x1815, 0xEF, 0xFF, 0}, + {0x1816, 0x8E, 0xFF, 0}, + {0x1817, 0x13, 0xFF, 0}, + {0x1818, 0x62, 0xFF, 0}, + {0x1819, 0x81, 0xFF, 0}, + {0x181A, 0x1, 0x7F, 0}, + {0x181B, 0x0, 0x3F, 0}, + {0x181C, 0x3, 0xF, 0}, + {0x181D, 0x48, 0x7F, 0}, + {0x181E, 0x17, 0x1F, 0}, + {0x1827, 0x3, 0xFF, 0}, + {0x1838, 0x8, 0x1F, 0}, + {0x183A, 0xB, 0x1F, 0}, + {0x1888, 0xD1, 0xFF, 0}, + {0x1889, 0xFC, 0xFF, 0}, + {0x188A, 0x92, 0xFF, 0}, + {0x188B, 0x0, 0x3, 0}, + {0x188C, 0x4C, 0x7F, 0}, + {0x188D, 0x0, 0x7F, 0}, + {0x188E, 0x30, 0x3F, 0}, + {0x188F, 0x9F, 0xFF, 0}, + {0x1890, 0x29, 0x3F, 0}, + {0x1891, 0x0, 0x3F, 0}, + {0x1892, 0x0, 0xFF, 0}, + {0x1893, 0xDC, 0xDC, 0}, + {0x1894, 0x0, 0x3F, 0}, + {0x1895, 0xFF, 0xFF, 0}, + {0x1896, 0x8E, 0xFF, 0}, + {0x1897, 0x3B, 0xFF, 0}, + {0x1898, 0x6A, 0xFF, 0}, + {0x1899, 0x80, 0xFF, 0}, + {0x189A, 0x8, 0x7F, 0}, + {0x189B, 0x1, 0x3F, 0}, + {0x189C, 0x3, 0xF, 0}, + {0x189D, 0x58, 0x7F, 0}, + {0x189E, 0xD, 0x1F, 0}, + {0x18BB, 0x7, 0x1F, 0}, + /* Add UVLO 2.0 setting */ + {0x999, 0x4, 0x7, 5}, + {0x99e, 0x1, 0x7, 3}, + /* Enable SPMI shutdown command */ + {0x136, 0x1, 0x1, 4}, + /* Enable magic key protection */ + {0x3B1, 0, 0xFF, 0}, + {0x3B2, 0, 0xFF, 0}, + {0x3A8, 0, 0xFF, 0}, + {0x3A9, 0, 0xFF, 0}, + {0xA15, 0, 0xFF, 0}, + {0xA16, 0, 0xFF, 0}, + {0x141C, 0, 0xFF, 0}, + {0x141D, 0, 0xFF, 0}, + {0x3AA, 0, 0xFF, 0}, + {0x3AB, 0, 0xFF, 0}, +}; + +static const struct mt6316_setting init_setting_s7[] = { + /* Disable magic key protection */ + {0x3B1, 0xE9, 0xFF, 0}, + {0x3B2, 0xE6, 0xFF, 0}, + {0x3A8, 0xE9, 0xFF, 0}, + {0x3A9, 0xE6, 0xFF, 0}, + {0xA15, 0x29, 0xFF, 0}, + {0xA16, 0x47, 0xFF, 0}, + {0x141C, 0x43, 0xFF, 0}, + {0x141D, 0x55, 0xFF, 0}, + {0x3AA, 0xDC, 0xFF, 0}, + {0x3AB, 0xF1, 0xFF, 0}, + /* Init setting */ + {0x13, 0x7, 0xFF, 0}, + {0x16, 0x12, 0xFF, 0}, + {0x17, 0x0, 0xFF, 0}, + {0x8A, 0x6, 0xF, 0}, + {0xA1, 0xC, 0xC, 0}, + {0xA2, 0x10, 0x10, 0}, + {0x10C, 0xC, 0xC, 0}, + {0x12C, 0x1, 0x1, 0}, + {0x140, 0x30, 0x30, 0}, + {0x142, 0x30, 0xFF, 0}, + {0x991, 0x11, 0xFF, 0}, + {0x196, 0x1, 0x1, 0}, + {0x197, 0x10, 0x10, 0}, + {0x19A, 0x1, 0x1, 0}, + {0x19B, 0x10, 0x10, 0}, + {0x217, 0x22, 0x22, 0}, + {0x219, 0x1F, 0x1F, 0}, + {0x223, 0x20, 0x20, 0}, + {0x413, 0x7, 0xFF, 0}, + {0x416, 0x12, 0xFF, 0}, + {0x417, 0x0, 0x7, 0}, + {0x988, 0x0, 0x20, 0}, + {0x98C, 0xB0, 0xFF, 0}, + {0x994, 0x0, 0xFF, 0}, + {0xA13, 0x10, 0x10, 0}, + {0xA1F, 0x80, 0x80, 0}, + {0x1452, 0x0, 0xFF, 0}, + {0x1457, 0x22, 0xFF, 0}, + {0x1458, 0x22, 0xFF, 0}, + {0x148A, 0x0, 0x3, 0}, + {0x148F, 0x2, 0x3, 0}, + {0x1492, 0x40, 0x70, 0}, + {0x150A, 0x0, 0x3, 0}, + {0x150F, 0x2, 0x3, 0}, + {0x1512, 0x40, 0x70, 0}, + {0x158A, 0x0, 0x3, 0}, + {0x158F, 0x2, 0x3, 0}, + {0x1592, 0x40, 0x70, 0}, + {0x160A, 0x0, 0x3, 0}, + {0x160F, 0x2, 0x3, 0}, + {0x1612, 0x40, 0x70, 0}, + {0x1729, 0x18, 0x18, 0}, + {0x17A9, 0x18, 0x18, 0}, + {0x1829, 0x18, 0x18, 0}, + {0x18A9, 0x18, 0x18, 0}, + {0x98, 0x2, 0x7, 0}, + {0xA1F, 0xC, 0xC, 0}, + {0xA21, 0x21, 0xFF, 0}, + {0xA23, 0xF0, 0xF0, 0}, + {0xA28, 0x20, 0xFF, 0}, + {0xA29, 0x20, 0xFF, 0}, + {0xA2A, 0x20, 0xFF, 0}, + {0xA2B, 0x20, 0xFF, 0}, + {0x1440, 0x0, 0xE, 0}, + {0x1487, 0x96, 0xFF, 0}, + {0x148A, 0xD, 0xF, 0}, + {0x148C, 0x3, 0x3, 0}, + {0x148D, 0x19, 0x7F, 0}, + {0x148E, 0x7, 0x7F, 0}, + {0x1490, 0x2, 0x3, 0}, + {0x1491, 0x19, 0x7F, 0}, + {0x1507, 0x96, 0xFF, 0}, + {0x150A, 0xD, 0xF, 0}, + {0x150C, 0x3, 0x3, 0}, + {0x150D, 0x19, 0x7F, 0}, + {0x150E, 0x7, 0x7F, 0}, + {0x1510, 0x2, 0x3, 0}, + {0x1511, 0x19, 0x7F, 0}, + {0x1587, 0x96, 0xFF, 0}, + {0x158A, 0xD, 0xF, 0}, + {0x158C, 0x3, 0x3, 0}, + {0x158D, 0x19, 0x7F, 0}, + {0x158E, 0x7, 0x7F, 0}, + {0x1590, 0x2, 0x3, 0}, + {0x1591, 0x19, 0x7F, 0}, + {0x1607, 0x96, 0xFF, 0}, + {0x160A, 0xD, 0xF, 0}, + {0x160C, 0x3, 0x3, 0}, + {0x160D, 0x19, 0x7F, 0}, + {0x160E, 0x7, 0x7F, 0}, + {0x1610, 0x2, 0x3, 0}, + {0x1611, 0x19, 0x7F, 0}, + {0x1688, 0x0, 0x1F, 0}, + {0x1689, 0x10, 0x7F, 0}, + {0x168A, 0x0, 0xFF, 0}, + {0x168B, 0x1, 0xFF, 0}, + {0x168C, 0x7, 0x3F, 0}, + {0x168D, 0x9, 0xFF, 0}, + {0x168E, 0xA0, 0xFF, 0}, + {0x1708, 0xD1, 0xFF, 0}, + {0x1709, 0xFC, 0xFF, 0}, + {0x170A, 0x92, 0xFF, 0}, + {0x170B, 0x0, 0x3, 0}, + {0x170C, 0x4C, 0x7F, 0}, + {0x170D, 0x0, 0x7F, 0}, + {0x170E, 0x30, 0x3F, 0}, + {0x170F, 0x9F, 0xFF, 0}, + {0x1710, 0x29, 0x3F, 0}, + {0x1711, 0x0, 0x3F, 0}, + {0x1712, 0x0, 0xFF, 0}, + {0x1713, 0x9C, 0x9C, 0}, + {0x1714, 0x1, 0x7F, 0}, + {0x1715, 0xFF, 0xFF, 0}, + {0x1716, 0x8E, 0xFF, 0}, + {0x1717, 0x3B, 0xFF, 0}, + {0x1718, 0x6A, 0xFF, 0}, + {0x1719, 0x80, 0xFF, 0}, + {0x171A, 0x8, 0x7F, 0}, + {0x171B, 0x1, 0x3F, 0}, + {0x171C, 0x3, 0xF, 0}, + {0x171D, 0x38, 0x7F, 0}, + {0x171E, 0xD, 0x1F, 0}, + {0x173B, 0x7, 0x1F, 0}, + {0x1788, 0xD1, 0xFF, 0}, + {0x1789, 0xFC, 0xFF, 0}, + {0x178A, 0x92, 0xFF, 0}, + {0x178B, 0x0, 0x3, 0}, + {0x178C, 0x4C, 0x7F, 0}, + {0x178D, 0x0, 0x7F, 0}, + {0x178E, 0x30, 0x3F, 0}, + {0x178F, 0x9F, 0xFF, 0}, + {0x1790, 0x29, 0x3F, 0}, + {0x1791, 0x0, 0x3F, 0}, + {0x1792, 0x0, 0xFF, 0}, + {0x1793, 0xDC, 0xDC, 0}, + {0x1794, 0x0, 0x3F, 0}, + {0x1795, 0xFF, 0xFF, 0}, + {0x1796, 0x8E, 0xFF, 0}, + {0x1797, 0x3B, 0xFF, 0}, + {0x1798, 0x6A, 0xFF, 0}, + {0x1799, 0x80, 0xFF, 0}, + {0x179A, 0x8, 0x7F, 0}, + {0x179B, 0x1, 0x3F, 0}, + {0x179C, 0x3, 0xF, 0}, + {0x179D, 0x38, 0x7F, 0}, + {0x179E, 0xD, 0x1F, 0}, + {0x17BB, 0x7, 0x1F, 0}, + {0x1808, 0xD1, 0xFF, 0}, + {0x1809, 0xFC, 0xFF, 0}, + {0x180A, 0x92, 0xFF, 0}, + {0x180B, 0x0, 0x3, 0}, + {0x180C, 0x4C, 0x7F, 0}, + {0x180D, 0x0, 0x7F, 0}, + {0x180E, 0x30, 0x3F, 0}, + {0x180F, 0x9F, 0xFF, 0}, + {0x1810, 0x29, 0x3F, 0}, + {0x1811, 0x0, 0x3F, 0}, + {0x1812, 0x0, 0xFF, 0}, + {0x1813, 0xDC, 0xDC, 0}, + {0x1814, 0x0, 0x3F, 0}, + {0x1815, 0xFF, 0xFF, 0}, + {0x1816, 0x8E, 0xFF, 0}, + {0x1817, 0x3B, 0xFF, 0}, + {0x1818, 0x6A, 0xFF, 0}, + {0x1819, 0x80, 0xFF, 0}, + {0x181A, 0x8, 0x7F, 0}, + {0x181B, 0x1, 0x3F, 0}, + {0x181C, 0x3, 0xF, 0}, + {0x181D, 0x38, 0x7F, 0}, + {0x181E, 0xD, 0x1F, 0}, + {0x183B, 0x7, 0x1F, 0}, + {0x1888, 0xD1, 0xFF, 0}, + {0x1889, 0xFC, 0xFF, 0}, + {0x188A, 0x92, 0xFF, 0}, + {0x188B, 0x0, 0x3, 0}, + {0x188C, 0x4C, 0x7F, 0}, + {0x188D, 0x0, 0x7F, 0}, + {0x188E, 0x30, 0x3F, 0}, + {0x188F, 0x9F, 0xFF, 0}, + {0x1890, 0x29, 0x3F, 0}, + {0x1891, 0x0, 0x3F, 0}, + {0x1892, 0x0, 0xFF, 0}, + {0x1893, 0xDC, 0xDC, 0}, + {0x1894, 0x0, 0x3F, 0}, + {0x1895, 0xFF, 0xFF, 0}, + {0x1896, 0x8E, 0xFF, 0}, + {0x1897, 0x3B, 0xFF, 0}, + {0x1898, 0x6A, 0xFF, 0}, + {0x1899, 0x80, 0xFF, 0}, + {0x189A, 0x8, 0x7F, 0}, + {0x189B, 0x1, 0x3F, 0}, + {0x189C, 0x3, 0xF, 0}, + {0x189D, 0x58, 0x7F, 0}, + {0x189E, 0xD, 0x1F, 0}, + {0x18BB, 0x7, 0x1F, 0}, + /* Add UVLO 2.0 setting */ + {0x999, 0x4, 0x7, 5}, + {0x99e, 0x1, 0x7, 3}, + /* Enable SPMI shutdown command */ + {0x136, 0x1, 0x1, 4}, + /* Enable magic key protection */ + {0x3B1, 0, 0xFF, 0}, + {0x3B2, 0, 0xFF, 0}, + {0x3A8, 0, 0xFF, 0}, + {0x3A9, 0, 0xFF, 0}, + {0xA15, 0, 0xFF, 0}, + {0xA16, 0, 0xFF, 0}, + {0x141C, 0, 0xFF, 0}, + {0x141D, 0, 0xFF, 0}, + {0x3AA, 0, 0xFF, 0}, + {0x3AB, 0, 0xFF, 0}, +}; + +static const struct mt6316_setting init_setting_s8[] = { + /* Disable magic key protection */ + {0x3B1, 0xE9, 0xFF, 0}, + {0x3B2, 0xE6, 0xFF, 0}, + {0x3A8, 0xE9, 0xFF, 0}, + {0x3A9, 0xE6, 0xFF, 0}, + {0xA15, 0x29, 0xFF, 0}, + {0xA16, 0x47, 0xFF, 0}, + {0x141C, 0x43, 0xFF, 0}, + {0x141D, 0x55, 0xFF, 0}, + {0x3AA, 0xDC, 0xFF, 0}, + {0x3AB, 0xF1, 0xFF, 0}, + /* Init setting */ + {0x13, 0x7, 0xFF, 0}, + {0x16, 0x12, 0xFF, 0}, + {0x17, 0x0, 0xFF, 0}, + {0x8A, 0x6, 0xF, 0}, + {0xA1, 0xC, 0xC, 0}, + {0xA2, 0x10, 0x10, 0}, + {0x10C, 0xC, 0xC, 0}, + {0x12C, 0x1, 0x1, 0}, + {0x140, 0x30, 0x30, 0}, + {0x142, 0x30, 0xFF, 0}, + {0x991, 0x11, 0xFF, 0}, + {0x196, 0x1, 0x1, 0}, + {0x197, 0x10, 0x10, 0}, + {0x19A, 0x1, 0x1, 0}, + {0x19B, 0x10, 0x10, 0}, + {0x217, 0x22, 0x22, 0}, + {0x219, 0x1F, 0x1F, 0}, + {0x223, 0x20, 0x20, 0}, + {0x413, 0x7, 0xFF, 0}, + {0x416, 0x12, 0xFF, 0}, + {0x417, 0x0, 0x7, 0}, + {0x988, 0x0, 0x20, 0}, + {0x98C, 0xB0, 0xFF, 0}, + {0x994, 0x0, 0xFF, 0}, + {0xA13, 0x10, 0x10, 0}, + {0xA1F, 0x80, 0x80, 0}, + {0x1452, 0x0, 0xFF, 0}, + {0x1457, 0x22, 0xFF, 0}, + {0x1458, 0x22, 0xFF, 0}, + {0x148A, 0x0, 0x3, 0}, + {0x148F, 0x2, 0x3, 0}, + {0x1492, 0x40, 0x70, 0}, + {0x150A, 0x0, 0x3, 0}, + {0x150F, 0x2, 0x3, 0}, + {0x1512, 0x40, 0x70, 0}, + {0x158A, 0x0, 0x3, 0}, + {0x158F, 0x2, 0x3, 0}, + {0x1592, 0x40, 0x70, 0}, + {0x160A, 0x0, 0x3, 0}, + {0x160F, 0x2, 0x3, 0}, + {0x1612, 0x40, 0x70, 0}, + {0x1729, 0x18, 0x18, 0}, + {0x17A9, 0x18, 0x18, 0}, + {0x1829, 0x18, 0x18, 0}, + {0x18A9, 0x18, 0x18, 0}, + {0xA18, 0x1, 0x1, 0}, + {0xA19, 0x2, 0xFF, 0}, + {0xA1A, 0x0, 0xFF, 0}, + {0xA1B, 0x0, 0xFF, 0}, + {0xA1C, 0x2, 0xFF, 0}, + {0xA1D, 0x2, 0xFF, 0}, + {0xA1F, 0xC, 0xC, 0}, + {0xA21, 0x1E, 0xFF, 0}, + {0xA23, 0xF0, 0xF0, 0}, + {0xA28, 0x1, 0xFF, 0}, + {0xA29, 0x1, 0xFF, 0}, + {0xA2A, 0x1E, 0xFF, 0}, + {0xA2B, 0x1E, 0xFF, 0}, + {0x1440, 0x0, 0xA, 0}, + {0x1487, 0x96, 0xFF, 0}, + {0x148A, 0xF, 0xF, 0}, + {0x148C, 0x3, 0x3, 0}, + {0x148D, 0xD, 0x7F, 0}, + {0x148E, 0x7, 0x7F, 0}, + {0x1490, 0x2, 0x3, 0}, + {0x1491, 0x19, 0x7F, 0}, + {0x1507, 0x96, 0xFF, 0}, + {0x150A, 0xF, 0xF, 0}, + {0x150D, 0xD, 0x7F, 0}, + {0x150E, 0x7, 0x7F, 0}, + {0x1510, 0x2, 0x3, 0}, + {0x1511, 0x19, 0x7F, 0}, + {0x1587, 0x55, 0xFF, 0}, + {0x158A, 0xF, 0xF, 0}, + {0x158C, 0x7, 0x7, 0}, + {0x158D, 0x28, 0x7F, 0}, + {0x158E, 0x7, 0x7F, 0}, + {0x1590, 0x2, 0x3, 0}, + {0x1591, 0x19, 0x7F, 0}, + {0x1607, 0x55, 0xFF, 0}, + {0x160A, 0xF, 0xF, 0}, + {0x160C, 0x7, 0x7, 0}, + {0x160D, 0x28, 0x7F, 0}, + {0x160E, 0x7, 0x7F, 0}, + {0x1610, 0x2, 0x3, 0}, + {0x1611, 0x19, 0x7F, 0}, + {0x1688, 0x0, 0x1F, 0}, + {0x1689, 0x50, 0x7F, 0}, + {0x168A, 0xA2, 0xFF, 0}, + {0x168B, 0x1, 0xFF, 0}, + {0x168C, 0x5, 0x3F, 0}, + {0x168D, 0xF, 0xFF, 0}, + {0x168E, 0x23, 0xFF, 0}, + {0x1708, 0xD1, 0xFF, 0}, + {0x1709, 0xAC, 0xFF, 0}, + {0x170A, 0x92, 0xFF, 0}, + {0x170B, 0x0, 0x3, 0}, + {0x170C, 0x48, 0x7F, 0}, + {0x170D, 0x8, 0x7F, 0}, + {0x170E, 0x30, 0x3F, 0}, + {0x170F, 0x4F, 0xFF, 0}, + {0x1710, 0x24, 0x3F, 0}, + {0x1711, 0x0, 0x3F, 0}, + {0x1712, 0x0, 0xFF, 0}, + {0x1713, 0x9C, 0x9C, 0}, + {0x1714, 0x41, 0x7F, 0}, + {0x1715, 0xEF, 0xFF, 0}, + {0x1716, 0x9C, 0xFF, 0}, + {0x1717, 0x1B, 0xFF, 0}, + {0x1718, 0xDE, 0xFF, 0}, + {0x1719, 0x86, 0xFF, 0}, + {0x171A, 0x8, 0x7F, 0}, + {0x171B, 0xB, 0x3F, 0}, + {0x171C, 0x3, 0xF, 0}, + {0x171D, 0x59, 0x7F, 0}, + {0x171E, 0x19, 0x1F, 0}, + {0x1734, 0x7, 0x3F, 0}, + {0x173A, 0x1A, 0x1F, 0}, + {0x1788, 0xD9, 0xFF, 0}, + {0x1789, 0xBF, 0xFF, 0}, + {0x178A, 0x92, 0xFF, 0}, + {0x178B, 0x0, 0x3, 0}, + {0x178C, 0x54, 0x7F, 0}, + {0x178D, 0x28, 0x7F, 0}, + {0x178E, 0x30, 0x3F, 0}, + {0x178F, 0x9F, 0xFF, 0}, + {0x1790, 0x9, 0x3F, 0}, + {0x1791, 0x0, 0x3F, 0}, + {0x1792, 0x0, 0xFF, 0}, + {0x1793, 0xDC, 0xDC, 0}, + {0x1794, 0x24, 0x3F, 0}, + {0x1795, 0xFF, 0xFF, 0}, + {0x1796, 0x8E, 0xFF, 0}, + {0x1797, 0x1B, 0xFF, 0}, + {0x1798, 0xAA, 0xFF, 0}, + {0x1799, 0x83, 0xFF, 0}, + {0x179A, 0x8, 0x7F, 0}, + {0x179B, 0x1, 0x3F, 0}, + {0x179C, 0x3, 0xF, 0}, + {0x179D, 0x0, 0x7F, 0}, + {0x179E, 0x9, 0x1F, 0}, + {0x17BA, 0x1A, 0x1F, 0}, + {0x1808, 0xD1, 0xFF, 0}, + {0x1809, 0xAC, 0xFF, 0}, + {0x180A, 0x92, 0xFF, 0}, + {0x180B, 0x0, 0x3, 0}, + {0x180C, 0x48, 0x7F, 0}, + {0x180D, 0x8, 0x7F, 0}, + {0x180E, 0x30, 0x3F, 0}, + {0x180F, 0x4F, 0xFF, 0}, + {0x1810, 0x24, 0x3F, 0}, + {0x1811, 0x0, 0x3F, 0}, + {0x1812, 0x0, 0xFF, 0}, + {0x1813, 0xDC, 0xDC, 0}, + {0x1814, 0x20, 0x3F, 0}, + {0x1815, 0xEF, 0xFF, 0}, + {0x1816, 0x9C, 0xFF, 0}, + {0x1817, 0x1B, 0xFF, 0}, + {0x1818, 0xDE, 0xFF, 0}, + {0x1819, 0x86, 0xFF, 0}, + {0x181A, 0x8, 0x7F, 0}, + {0x181B, 0xB, 0x3F, 0}, + {0x181C, 0x3, 0xF, 0}, + {0x181D, 0x59, 0x7F, 0}, + {0x181E, 0x19, 0x1F, 0}, + {0x1834, 0x7, 0x3F, 0}, + {0x183A, 0x1A, 0x1F, 0}, + {0x1888, 0xD9, 0xFF, 0}, + {0x1889, 0xBF, 0xFF, 0}, + {0x188A, 0x92, 0xFF, 0}, + {0x188B, 0x0, 0x3, 0}, + {0x188C, 0x54, 0x7F, 0}, + {0x188D, 0x28, 0x7F, 0}, + {0x188E, 0x30, 0x3F, 0}, + {0x188F, 0x9F, 0xFF, 0}, + {0x1890, 0x9, 0x3F, 0}, + {0x1891, 0x0, 0x3F, 0}, + {0x1892, 0x0, 0xFF, 0}, + {0x1893, 0xDC, 0xDC, 0}, + {0x1894, 0x24, 0x3F, 0}, + {0x1895, 0xFF, 0xFF, 0}, + {0x1896, 0x8E, 0xFF, 0}, + {0x1897, 0x1B, 0xFF, 0}, + {0x1898, 0xAA, 0xFF, 0}, + {0x1899, 0x83, 0xFF, 0}, + {0x189A, 0x8, 0x7F, 0}, + {0x189B, 0x1, 0x3F, 0}, + {0x189C, 0x3, 0xF, 0}, + {0x189D, 0x0, 0x7F, 0}, + {0x189E, 0x9, 0x1F, 0}, + {0x18BA, 0x1A, 0x1F, 0}, + /* Add UVLO 2.0 setting */ + {0x999, 0x4, 0x7, 5}, + {0x99e, 0x1, 0x7, 3}, + /* Enable SPMI shutdown command */ + {0x136, 0x1, 0x1, 4}, + /* Enable magic key protection */ + {0x3B1, 0, 0xFF, 0}, + {0x3B2, 0, 0xFF, 0}, + {0x3A8, 0, 0xFF, 0}, + {0x3A9, 0, 0xFF, 0}, + {0xA15, 0, 0xFF, 0}, + {0xA16, 0, 0xFF, 0}, + {0x141C, 0, 0xFF, 0}, + {0x141D, 0, 0xFF, 0}, + {0x3AA, 0, 0xFF, 0}, + {0x3AB, 0, 0xFF, 0}, +}; + +/* KP(VCPUB + DREQ) */ +static const struct mt6316_setting init_setting_s15[] = { + /* Disable magic key protection */ + {0x3B1, 0xE9, 0xFF, 0}, + {0x3B2, 0xE6, 0xFF, 0}, + {0x3A8, 0xE9, 0xFF, 0}, + {0x3A9, 0xE6, 0xFF, 0}, + {0xA15, 0x29, 0xFF, 0}, + {0xA16, 0x47, 0xFF, 0}, + {0x141C, 0x43, 0xFF, 0}, + {0x141D, 0x55, 0xFF, 0}, + {0x3AA, 0xDC, 0xFF, 0}, + {0x3AB, 0xF1, 0xFF, 0}, + /* Init setting */ + {0x13, 0x7, 0xFF, 0}, + {0x16, 0x12, 0xFF, 0}, + {0x17, 0x0, 0xFF, 0}, + {0x8A, 0x6, 0xF, 0}, + {0xA1, 0xC, 0xC, 0}, + {0xA2, 0x10, 0x10, 0}, + {0x10C, 0xC, 0xC, 0}, + {0x12C, 0x1, 0x1, 0}, + {0x140, 0x30, 0x30, 0}, + {0x142, 0x30, 0xFF, 0}, + {0x991, 0x11, 0xFF, 0}, + {0x196, 0x1, 0x1, 0}, + {0x197, 0x10, 0x10, 0}, + {0x19A, 0x1, 0x1, 0}, + {0x19B, 0x10, 0x10, 0}, + {0x217, 0x22, 0x22, 0}, + {0x219, 0x1F, 0x1F, 0}, + {0x223, 0x20, 0x20, 0}, + {0x413, 0x7, 0xFF, 0}, + {0x416, 0x12, 0xFF, 0}, + {0x417, 0x0, 0x7, 0}, + {0x988, 0x0, 0x20, 0}, + {0x98C, 0xB0, 0xFF, 0}, + {0x994, 0x0, 0xFF, 0}, + {0xA13, 0x10, 0x10, 0}, + {0xA1F, 0x80, 0x80, 0}, + {0x1452, 0x0, 0xFF, 0}, + {0x1457, 0x22, 0xFF, 0}, + {0x1458, 0x22, 0xFF, 0}, + {0x148A, 0x0, 0x3, 0}, + {0x148F, 0x2, 0x3, 0}, + {0x1492, 0x40, 0x70, 0}, + {0x150A, 0x0, 0x3, 0}, + {0x150F, 0x2, 0x3, 0}, + {0x1512, 0x40, 0x70, 0}, + {0x158A, 0x0, 0x3, 0}, + {0x158F, 0x2, 0x3, 0}, + {0x1592, 0x40, 0x70, 0}, + {0x160A, 0x0, 0x3, 0}, + {0x160F, 0x2, 0x3, 0}, + {0x1612, 0x40, 0x70, 0}, + {0x1729, 0x18, 0x18, 0}, + {0x17A9, 0x18, 0x18, 0}, + {0x1829, 0x18, 0x18, 0}, + {0x18A9, 0x18, 0x18, 0}, + {0x98, 0x2, 0x7, 0}, + {0xA1F, 0xC, 0xC, 0}, + {0xA21, 0x21, 0xFF, 0}, + {0xA23, 0xF0, 0xF0, 0}, + {0xA28, 0x1A, 0xFF, 0}, + {0xA29, 0x1A, 0xFF, 0}, + {0xA2A, 0x18, 0xFF, 0}, + {0xA2B, 0x1A, 0xFF, 0}, + {0x1440, 0x0, 0xA, 0}, + {0x1487, 0x55, 0xFF, 0}, + {0x148A, 0xD, 0xF, 0}, + {0x148C, 0x3, 0x3, 0}, + {0x148D, 0x28, 0x7F, 0}, + {0x148E, 0x7, 0x7F, 0}, + {0x1490, 0x2, 0x3, 0}, + {0x1491, 0x19, 0x7F, 0}, + {0x1507, 0x55, 0xFF, 0}, + {0x150A, 0xD, 0xF, 0}, + {0x150C, 0x3, 0x3, 0}, + {0x150D, 0x28, 0x7F, 0}, + {0x150E, 0x7, 0x7F, 0}, + {0x1510, 0x2, 0x3, 0}, + {0x1511, 0x19, 0x7F, 0}, + {0x1587, 0x96, 0xFF, 0}, + {0x158A, 0xD, 0xF, 0}, + {0x158D, 0xD, 0x7F, 0}, + {0x158E, 0x7, 0x7F, 0}, + {0x1590, 0x2, 0x3, 0}, + {0x1591, 0x19, 0x7F, 0}, + {0x1607, 0x55, 0xFF, 0}, + {0x160A, 0xD, 0xF, 0}, + {0x160C, 0x3, 0x3, 0}, + {0x160D, 0x28, 0x7F, 0}, + {0x160E, 0x7, 0x7F, 0}, + {0x1610, 0x2, 0x3, 0}, + {0x1611, 0x19, 0x7F, 0}, + {0x1688, 0x0, 0x1F, 0}, + {0x1689, 0x10, 0x7F, 0}, + {0x168A, 0x0, 0xFF, 0}, + {0x168B, 0x1, 0xFF, 0}, + {0x168C, 0x5, 0x3F, 0}, + {0x168D, 0xB, 0xFF, 0}, + {0x168E, 0xA0, 0xFF, 0}, + {0x1708, 0xD1, 0xFF, 0}, + {0x1709, 0xFC, 0xFF, 0}, + {0x170A, 0x92, 0xFF, 0}, + {0x170B, 0x0, 0x3, 0}, + {0x170C, 0x4C, 0x7F, 0}, + {0x170D, 0x0, 0x7F, 0}, + {0x170E, 0x30, 0x3F, 0}, + {0x170F, 0x9F, 0xFF, 0}, + {0x1710, 0x29, 0x3F, 0}, + {0x1711, 0x0, 0x3F, 0}, + {0x1712, 0x0, 0xFF, 0}, + {0x1713, 0x9C, 0x9C, 0}, + {0x1714, 0x1, 0x7F, 0}, + {0x1715, 0xFF, 0xFF, 0}, + {0x1716, 0x8E, 0xFF, 0}, + {0x1717, 0x3B, 0xFF, 0}, + {0x1718, 0x6A, 0xFF, 0}, + {0x1719, 0x80, 0xFF, 0}, + {0x171A, 0x8, 0x7F, 0}, + {0x171B, 0x1, 0x3F, 0}, + {0x171C, 0x3, 0xF, 0}, + {0x171D, 0x58, 0x7F, 0}, + {0x171E, 0xD, 0x1F, 0}, + {0x173B, 0x7, 0x1F, 0}, + {0x1788, 0xD1, 0xFF, 0}, + {0x1789, 0xFC, 0xFF, 0}, + {0x178A, 0x92, 0xFF, 0}, + {0x178B, 0x0, 0x3, 0}, + {0x178C, 0x4C, 0x7F, 0}, + {0x178D, 0x0, 0x7F, 0}, + {0x178E, 0x30, 0x3F, 0}, + {0x178F, 0x9F, 0xFF, 0}, + {0x1790, 0x29, 0x3F, 0}, + {0x1791, 0x0, 0x3F, 0}, + {0x1792, 0x0, 0xFF, 0}, + {0x1793, 0xDC, 0xDC, 0}, + {0x1794, 0x0, 0x3F, 0}, + {0x1795, 0xFF, 0xFF, 0}, + {0x1796, 0x8E, 0xFF, 0}, + {0x1797, 0x3B, 0xFF, 0}, + {0x1798, 0x6A, 0xFF, 0}, + {0x1799, 0x80, 0xFF, 0}, + {0x179A, 0x8, 0x7F, 0}, + {0x179B, 0x1, 0x3F, 0}, + {0x179C, 0x3, 0xF, 0}, + {0x179D, 0x58, 0x7F, 0}, + {0x179E, 0xD, 0x1F, 0}, + {0x17BB, 0x7, 0x1F, 0}, + {0x1808, 0xF1, 0xFF, 0}, + {0x1809, 0xEC, 0xFF, 0}, + {0x180A, 0x92, 0xFF, 0}, + {0x180B, 0x0, 0x3, 0}, + {0x180C, 0x54, 0x7F, 0}, + {0x180D, 0x0, 0x7F, 0}, + {0x180E, 0x10, 0x3F, 0}, + {0x180F, 0x9F, 0xFF, 0}, + {0x1810, 0x29, 0x3F, 0}, + {0x1811, 0x0, 0x3F, 0}, + {0x1812, 0x0, 0xFF, 0}, + {0x1813, 0xDC, 0xDC, 0}, + {0x1814, 0x0, 0x3F, 0}, + {0x1815, 0xEF, 0xFF, 0}, + {0x1816, 0x8C, 0xFF, 0}, + {0x1817, 0x13, 0xFF, 0}, + {0x1818, 0xE2, 0xFF, 0}, + {0x1819, 0x81, 0xFF, 0}, + {0x181A, 0x1, 0x7F, 0}, + {0x181B, 0x0, 0x3F, 0}, + {0x181C, 0x3, 0xF, 0}, + {0x181D, 0x39, 0x7F, 0}, + {0x181E, 0x15, 0x1F, 0}, + {0x1888, 0xD1, 0xFF, 0}, + {0x1889, 0xFC, 0xFF, 0}, + {0x188A, 0x92, 0xFF, 0}, + {0x188B, 0x0, 0x3, 0}, + {0x188C, 0x4C, 0x7F, 0}, + {0x188D, 0x0, 0x7F, 0}, + {0x188E, 0x30, 0x3F, 0}, + {0x188F, 0x9F, 0xFF, 0}, + {0x1890, 0x29, 0x3F, 0}, + {0x1891, 0x0, 0x3F, 0}, + {0x1892, 0x0, 0xFF, 0}, + {0x1893, 0xDC, 0xDC, 0}, + {0x1894, 0x0, 0x3F, 0}, + {0x1895, 0xFF, 0xFF, 0}, + {0x1896, 0x8E, 0xFF, 0}, + {0x1897, 0x3B, 0xFF, 0}, + {0x1898, 0x6A, 0xFF, 0}, + {0x1899, 0x80, 0xFF, 0}, + {0x189A, 0x8, 0x7F, 0}, + {0x189B, 0x1, 0x3F, 0}, + {0x189C, 0x3, 0xF, 0}, + {0x189D, 0x58, 0x7F, 0}, + {0x189E, 0xD, 0x1F, 0}, + {0x18BB, 0x7, 0x1F, 0}, + /* Add UVLO 2.0 setting */ + {0x999, 0x4, 0x7, 5}, + {0x99e, 0x1, 0x7, 3}, + /* Enable SPMI shutdown command */ + {0x136, 0x1, 0x1, 4}, + /* Enable magic key protection */ + {0x3B1, 0, 0xFF, 0}, + {0x3B2, 0, 0xFF, 0}, + {0x3A8, 0, 0xFF, 0}, + {0x3A9, 0, 0xFF, 0}, + {0xA15, 0, 0xFF, 0}, + {0xA16, 0, 0xFF, 0}, + {0x141C, 0, 0xFF, 0}, + {0x141D, 0, 0xFF, 0}, + {0x3AA, 0, 0xFF, 0}, + {0x3AB, 0, 0xFF, 0}, +}; + +static inline void write_field(enum spmi_slave slvid, const struct mt6316_setting *setting) +{ + mt6316_write_field(slvid, setting->addr, setting->val, setting->mask, setting->shift); +} + +void mt6316_init_setting(void) +{ + for (int i = 0; i < ARRAY_SIZE(init_setting_s6); i++) + write_field(SPMI_SLAVE_6, &init_setting_s6[i]); + + for (int i = 0; i < ARRAY_SIZE(init_setting_s7); i++) + write_field(SPMI_SLAVE_7, &init_setting_s7[i]); + + for (int i = 0; i < ARRAY_SIZE(init_setting_s8); i++) + write_field(SPMI_SLAVE_8, &init_setting_s8[i]); + + for (int i = 0; i < ARRAY_SIZE(init_setting_s15); i++) + write_field(SPMI_SLAVE_15, &init_setting_s15[i]); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/85630?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I39e91d64e77cff03281845dfbea565e6ddf748f6 Gerrit-Change-Number: 85630 Gerrit-PatchSet: 13 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com>

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[S] Change in coreboot[main]: mb/google/fatcat: Limit Power Limit when battery is missing
by Subrata Banik (Code Review) 25 Dec '24

25 Dec '24

Attention is currently required from: Jamie Ryu, Jérémy Compostella, Paul Menzel. Subrata Banik has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/85146?usp=email ) Change subject: mb/google/fatcat: Limit Power Limit when battery is missing ...................................................................... Patch Set 18: (1 comment) Patchset: PS17: > > I would like to of course as I do not enjoy having pending CLs. […] Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/85146?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5d71e9edde0ecbd7aaf316cd754a6ebcff9da77e Gerrit-Change-Number: 85146 Gerrit-PatchSet: 18 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Wed, 25 Dec 2024 07:15:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com>

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[XS] Change in coreboot[main]: mb/google/rauru: Initialize PMICs in romstage
by Yidi Lin (Code Review) 25 Dec '24

25 Dec '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yu-Ping Wu. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85755?usp=email ) Change subject: mb/google/rauru: Initialize PMICs in romstage ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/85755?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia220db1d8d6d20e508f5e4d47054922012f6c417 Gerrit-Change-Number: 85755 Gerrit-PatchSet: 2 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Wed, 25 Dec 2024 07:14:19 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

1 0

[S] Change in coreboot[main]: mb/google/fatcat: Limit Power Limit when battery is missing
by Subrata Banik (Code Review) 25 Dec '24

25 Dec '24

Attention is currently required from: Jamie Ryu, Jérémy Compostella, Paul Menzel, Subrata Banik. Subrata Banik has uploaded a new patch set (#18) to the change originally created by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/85146?usp=email ) The following approvals got outdated and were removed: Code-Review+2 by Subrata Banik, Verified+1 by build bot (Jenkins) Change subject: mb/google/fatcat: Limit Power Limit when battery is missing ...................................................................... mb/google/fatcat: Limit Power Limit when battery is missing Ensure the board can boot by limiting the power limits if the battery is missing. This addresses the factory use case. BUG=b:377798581 TEST=See power limit override log message when the battery is missing on fatcat board Change-Id: I5d71e9edde0ecbd7aaf316cd754a6ebcff9da77e Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- M src/mainboard/google/fatcat/Kconfig M src/mainboard/google/fatcat/variants/baseboard/fatcat/Makefile.mk A src/mainboard/google/fatcat/variants/baseboard/fatcat/ramstage.c 3 files changed, 34 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/85146/18 -- To view, visit https://review.coreboot.org/c/coreboot/+/85146?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5d71e9edde0ecbd7aaf316cd754a6ebcff9da77e Gerrit-Change-Number: 85146 Gerrit-PatchSet: 18 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org>

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