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Hello Andy Hsu,
I'd like you to do a code review.
Please visit
https://review.coreboot.org/c/blobs/+/85763?usp=email
to review the following change.
Change subject: soc/mediatek/mt8196: Add GPUEB firmware v1.0
......................................................................
soc/mediatek/mt8196: Add GPUEB firmware v1.0
Add initial GPUEB firmware.
TEST=Build pass
BUG=b:317009620
Change-Id: I470f1575beea481cac2dcb5f3eb77587739ff2dc
Signed-off-by: Andy.Hsu <andy.hsu(a)mediatek.corp-partner.google.com>
---
M soc/mediatek/mt8196/README.md
A soc/mediatek/mt8196/gpueb_release_notes.txt
A soc/mediatek/mt8196/tinysys-gpueb-RV33_A.mkpt_fw.img
A soc/mediatek/mt8196/tinysys-gpueb-RV33_A.mkpt_fw.img.md5
4 files changed, 23 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/blobs refs/changes/63/85763/1
diff --git a/soc/mediatek/mt8196/README.md b/soc/mediatek/mt8196/README.md
index 9af056e..b6e119b 100644
--- a/soc/mediatek/mt8196/README.md
+++ b/soc/mediatek/mt8196/README.md
@@ -195,3 +195,21 @@
`$ strings spm_firmware.bin | grep "spm firmware"`
--------------------------------------------------------------------------------
+# GPUEB introduction
+GPUEB is a micro-processor used for GPU power management.
+In addition, it is responsible for controlling GPU DVFS and GPU thermal throttling.
+
+## Who uses it
+Coreboot will load GPUEB firmware at ramstage. It will copy `tinysys-gpueb-RV33_A.mkpt_fw.img` to the SRAM of GPUEB.
+
+## How to load `tinysys-gpueb-RV33_A.mkpt_fw.img`
+Use CBFS to load `tinysys-gpueb-RV33_A.mkpt_fw.img`.
+After loading is complete, apply the normal boot settings and release the software reset to trigger GPUEB.
+
+## Return values
+No return value.
+
+## Version
+`$ strings tinysys-gpueb-RV33_A.mkpt_fw.img | grep "gpueb firmware"`
+
+--------------------------------------------------------------------------------
diff --git a/soc/mediatek/mt8196/gpueb_release_notes.txt b/soc/mediatek/mt8196/gpueb_release_notes.txt
new file mode 100644
index 0000000..f3b09fd
--- /dev/null
+++ b/soc/mediatek/mt8196/gpueb_release_notes.txt
@@ -0,0 +1,4 @@
+** Build from MediaTek Internal **
+
+# Version 1.0
+1. Initial release.
diff --git a/soc/mediatek/mt8196/tinysys-gpueb-RV33_A.mkpt_fw.img b/soc/mediatek/mt8196/tinysys-gpueb-RV33_A.mkpt_fw.img
new file mode 100644
index 0000000..0098236
--- /dev/null
+++ b/soc/mediatek/mt8196/tinysys-gpueb-RV33_A.mkpt_fw.img
Binary files differ
diff --git a/soc/mediatek/mt8196/tinysys-gpueb-RV33_A.mkpt_fw.img.md5 b/soc/mediatek/mt8196/tinysys-gpueb-RV33_A.mkpt_fw.img.md5
new file mode 100644
index 0000000..8cbd0d3
--- /dev/null
+++ b/soc/mediatek/mt8196/tinysys-gpueb-RV33_A.mkpt_fw.img.md5
@@ -0,0 +1 @@
+fb1d54260ac0f5a92e115abf81c1bbc9 *tinysys-gpueb-RV33_A.mkpt_fw.img
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Change subject: mb/google/corsola: Refactor mipi_panel_power_on function
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Patch Set 7: Code-Review+2
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Change subject: soc/mediatek/mt8196: Add GPUEB support
......................................................................
Patch Set 3:
(1 comment)
File src/soc/mediatek/mt8196/include/soc/gpueb_priv.h:
https://review.coreboot.org/c/coreboot/+/85654/comment/bf1a491b_d6da81bd?us… :
PS2, Line 10: #define SPM2GPUPM_CON (SPM_BASE + 0x0410) /* 0x1C004410 */
: #define SPM_REQ_STA_9 (SPM_BASE + 0x0884) /* 0x1C004884 */
: #define SPM_MFG0_PWR_CON (SPM_BASE + 0x0EA8)
> After discussing with the designer, he believes that removing it should be okay.
Acknowledged
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Change subject: soc/mediatek/mt8196: Add GPUEB support
......................................................................
Patch Set 3:
(1 comment)
File src/soc/mediatek/mt8196/include/soc/gpueb_priv.h:
https://review.coreboot.org/c/coreboot/+/85654/comment/9e93b37e_c023b2ea?us… :
PS2, Line 10: #define SPM2GPUPM_CON (SPM_BASE + 0x0410) /* 0x1C004410 */
: #define SPM_REQ_STA_9 (SPM_BASE + 0x0884) /* 0x1C004884 */
: #define SPM_MFG0_PWR_CON (SPM_BASE + 0x0EA8)
> Sorry, I leaved the comment accidentally. […]
After discussing with the designer, he believes that removing it should be okay.
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Change subject: arch/x86/fit_payload.c: Supporting loading FIT payloads
......................................................................
Abandoned
pursuing firmware/kernel split instead, see first in the series
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Change subject: arch/*/fit_payload.c: Do not support loading UPL FITs
......................................................................
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Riku Viitanen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85762?usp=email )
Change subject: mb/asrock/b75pro3-m/dt: Clean it up a bit
......................................................................
mb/asrock/b75pro3-m/dt: Clean it up a bit
Remove superfluous comments duplicating the device names. Also when
nothing is inside the device entry, move the "end" statements to the
first line.
Change-Id: I2d244619dc10ec465af19dbfb918b9c37e059586
Signed-off-by: Riku Viitanen <riku.viitanen(a)protonmail.com>
---
M src/mainboard/asrock/b75pro3-m/devicetree.cb
1 file changed, 23 insertions(+), 33 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/85762/1
diff --git a/src/mainboard/asrock/b75pro3-m/devicetree.cb b/src/mainboard/asrock/b75pro3-m/devicetree.cb
index 1cf5015..e0ed2c5 100644
--- a/src/mainboard/asrock/b75pro3-m/devicetree.cb
+++ b/src/mainboard/asrock/b75pro3-m/devicetree.cb
@@ -56,52 +56,44 @@
{ 1, 0, 6 }
}"
- device ref xhci on # USB 3.0 Controller
+ device ref xhci on
subsystemid 0x1849 0x1e31
end
- device ref mei1 on # Management Engine Interface 1
+ device ref mei1 on
subsystemid 0x1849 0x1e3a
end
- device ref mei2 off # Management Engine Interface 2
- end
- device ref me_ide_r off # Management Engine IDE-R
- end
- device ref me_kt off end # Management Engine KT
- device ref gbe off # Intel Gigabit Ethernet
- end
- device ref ehci2 on # USB2 EHCI #2
+ device ref mei2 off end
+ device ref me_ide_r off end
+ device ref me_kt off end
+ device ref gbe off end
+ device ref ehci2 on
subsystemid 0x1849 0x1e2d
end
- device ref hda on # High Definition Audio controller
+ device ref hda on
subsystemid 0x1849 0x8892
end
- device ref pcie_rp1 on # PCIe Port #1
+ device ref pcie_rp1 on
subsystemid 0x1849 0x1e10
end
- device ref pcie_rp2 off # PCIe Port #2
- end
- device ref pcie_rp3 off # PCIe Port #3
- end
- device ref pcie_rp4 off # PCIe Port #4
- end
- device ref pcie_rp5 on # PCIe Port #5, ASMedia ASM1062 SATA Controller
+ device ref pcie_rp2 off end
+ device ref pcie_rp3 off end
+ device ref pcie_rp4 off end
+ device ref pcie_rp5 on # ASMedia ASM1062 SATA Controller
subsystemid 0x1849 0x1e18
end
- device ref pcie_rp6 on # PCIe Port #6, Realtek PCIe GbE Controller
+ device ref pcie_rp6 on # Realtek PCIe GbE Controller
subsystemid 0x1849 0x1e1a
device pci 00.0 on end
end
- device ref pcie_rp7 off # PCIe Port #7
- end
- device ref pcie_rp8 off # PCIe Port #8
- end
- device ref ehci1 on # USB2 EHCI #1
+ device ref pcie_rp7 off end
+ device ref pcie_rp8 off end
+ device ref ehci1 on
subsystemid 0x1849 0x1e26
end
- device ref pci_bridge on # PCI bridge
+ device ref pci_bridge on
subsystemid 0x1849 0x244e
end
- device ref lpc on # LPC bridge
+ device ref lpc on
subsystemid 0x1849 0x1e49
chip superio/nuvoton/nct6776
device pnp 2e.0 off end # Floppy
@@ -156,16 +148,14 @@
device pnp 2e.17 on end # GPIOA
end
end
- device ref sata1 on # SATA Controller 1
+ device ref sata1 on
subsystemid 0x1849 0x1e02
end
- device ref smbus on # SMBus
+ device ref smbus on
subsystemid 0x1849 0x1e22
end
- device ref sata2 off # SATA Controller 2
- end
- device ref thermal off # Thermal
- end
+ device ref sata2 off end
+ device ref thermal off end
end
end
end
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