coreboot-gerrit December 2024

coreboot-gerrit@coreboot.org

1 participants
3018 discussions

[S] Change in coreboot[main]: Doc/soc/amd/family15h: Fix URLs to AMD documents
by Felix Singer (Code Review) 25 Dec '24

25 Dec '24

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84815?usp=email ) Change subject: Doc/soc/amd/family15h: Fix URLs to AMD documents ...................................................................... Doc/soc/amd/family15h: Fix URLs to AMD documents Those documents have been moved to the archive. Previous URLs now point to the documentation hub. Change-Id: Ibb478b56d02842dc05475235b0fe80ab6c4e7d04 Signed-off-by: Daniel Maslowski <info(a)orangecms.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84815 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Maxim <max.senia.poliak(a)gmail.com> Reviewed-by: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> --- M Documentation/soc/amd/family15h.md 1 file changed, 5 insertions(+), 5 deletions(-) Approvals: Maxim: Looks good to me, approved Felix Singer: Looks good to me, approved build bot (Jenkins): Verified Nicholas Sudsgaard: Looks good to me, approved diff --git a/Documentation/soc/amd/family15h.md b/Documentation/soc/amd/family15h.md index 5a8f95d..25ca6fd 100644 --- a/Documentation/soc/amd/family15h.md +++ b/Documentation/soc/amd/family15h.md @@ -42,9 +42,9 @@ ## References -1. [Models 00h-0Fh BKDG](https://www.amd.com/system/files/TechDocs/42301_15h_Mod_00h-0Fh_BKDG.… -2. [Models 10h-1Fh BKDG](https://www.amd.com/system/files/TechDocs/42300_15h_Mod_10h-1Fh_BKDG.… -3. [Models 30h-3Fh BKDG](https://www.amd.com/system/files/TechDocs/49125_15h_Models_30h-3Fh_BK… -4. [Models 60h-6Fh BKDG](https://www.amd.com/system/files/TechDocs/50742_15h_Models_60h-6Fh_BK… -5. [Models 70h-7Fh BKDG](https://www.amd.com/system/files/TechDocs/55072_AMD_Family_15h_Models… +1. [Models 00h-0Fh BKDG](https://www.amd.com/content/dam/amd/en/documents/archived-tech-docs/p… +2. [Models 10h-1Fh BKDG](https://www.amd.com/content/dam/amd/en/documents/archived-tech-docs/p… +3. [Models 30h-3Fh BKDG](https://www.amd.com/content/dam/amd/en/documents/archived-tech-docs/p… +4. [Models 60h-6Fh BKDG](https://www.amd.com/content/dam/amd/en/documents/archived-tech-docs/p… +5. [Models 70h-7Fh BKDG](https://www.amd.com/content/dam/amd/en/documents/archived-tech-docs/p… 6. [PSP Integration](psp_integration.md) -- To view, visit https://review.coreboot.org/c/coreboot/+/84815?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibb478b56d02842dc05475235b0fe80ab6c4e7d04 Gerrit-Change-Number: 84815 Gerrit-PatchSet: 4 Gerrit-Owner: Daniel Maslowski <info(a)orangecms.org> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Maxim <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

[S] Change in coreboot[main]: Doc/soc/amd/family15h: Fix URLs to AMD documents
by Felix Singer (Code Review) 25 Dec '24

25 Dec '24

Attention is currently required from: Daniel Maslowski, Nicholas Sudsgaard. Felix Singer has posted comments on this change by Daniel Maslowski. ( https://review.coreboot.org/c/coreboot/+/84815?usp=email ) Change subject: Doc/soc/amd/family15h: Fix URLs to AMD documents ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84815?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibb478b56d02842dc05475235b0fe80ab6c4e7d04 Gerrit-Change-Number: 84815 Gerrit-PatchSet: 3 Gerrit-Owner: Daniel Maslowski <info(a)orangecms.org> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Maxim <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Daniel Maslowski <info(a)orangecms.org> Gerrit-Attention: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Comment-Date: Wed, 25 Dec 2024 13:32:56 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

1 0

[L] Change in coreboot[main]: mb/asus: Add Maximus VI Gene (Haswell)
by Jan Philipp Groß (Code Review) 25 Dec '24

25 Dec '24

Attention is currently required from: Angel Pons, Máté Kukri, Nicholas Chin. Jan Philipp Groß has posted comments on this change by Jan Philipp Groß. ( https://review.coreboot.org/c/coreboot/+/85767?usp=email ) Change subject: mb/asus: Add Maximus VI Gene (Haswell) ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/85767/comment/04158020_3bdde0bb?us… : PS2, Line 14: not working on vendor firmware, assuming hardware defect) > Can be a single bent pin in the socket Indeed! You can actually see it with the bare eye, a single bent pin. -- To view, visit https://review.coreboot.org/c/coreboot/+/85767?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I31029c78cba65cad96718132235c140c3997c815 Gerrit-Change-Number: 85767 Gerrit-PatchSet: 3 Gerrit-Owner: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Máté Kukri <km(a)mkukri.xyz> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Máté Kukri <km(a)mkukri.xyz> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Wed, 25 Dec 2024 13:30:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

1 0

[L] Change in coreboot[main]: mb/asus: Add Maximus VI Gene (Haswell)
by Angel Pons (Code Review) 25 Dec '24

25 Dec '24

Attention is currently required from: Jan Philipp Groß, Máté Kukri, Nicholas Chin. Angel Pons has posted comments on this change by Jan Philipp Groß. ( https://review.coreboot.org/c/coreboot/+/85767?usp=email ) Change subject: mb/asus: Add Maximus VI Gene (Haswell) ...................................................................... Patch Set 2: Code-Review+1 Copied votes on follow-up patch sets have been updated: * Code-Review+1 has been copied to patch set 3 (copy condition: "changekind:NO_CHANGE OR changekind:NO_CODE_CHANGE OR changekind:TRIVIAL_REBASE OR is:MIN"). (2 comments) Patchset: PS2: Just a quick look Commit Message: https://review.coreboot.org/c/coreboot/+/85767/comment/00cee5d1_bda7a486?us… : PS2, Line 14: not working on vendor firmware, assuming hardware defect) Can be a single bent pin in the socket -- To view, visit https://review.coreboot.org/c/coreboot/+/85767?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I31029c78cba65cad96718132235c140c3997c815 Gerrit-Change-Number: 85767 Gerrit-PatchSet: 2 Gerrit-Owner: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Máté Kukri <km(a)mkukri.xyz> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Máté Kukri <km(a)mkukri.xyz> Gerrit-Attention: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Wed, 25 Dec 2024 13:27:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

1 0

[L] Change in coreboot[main]: mb/asus: Add Maximus VI Gene (Haswell)
by Jan Philipp Groß (Code Review) 25 Dec '24

25 Dec '24

Attention is currently required from: Angel Pons, Máté Kukri, Nicholas Chin. Hello Angel Pons, Máté Kukri, Nicholas Chin, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85767?usp=email to look at the new patch set (#3). Change subject: mb/asus: Add Maximus VI Gene (Haswell) ...................................................................... mb/asus: Add Maximus VI Gene (Haswell) This port was done via autoport and subsequent manual tweaking. Working: - Haswell MRC.bin - DIMM_B1 and DIMM_B2 DDR3/DDR3L DIMM slots (DIMM_A1 and DIMM_A2 also not working on vendor firmware, assuming hardware defect) - HDMI-Out Port - RJ-45 Gigabit LAN Port - All four back panel USB 2.0 Ports - All four back panel ASMedia USB 3.0 Ports - Both back panel USB 3.0 Ports - USB 3.0 Header - All six SATA3 6.0 Gb/s connectors by Intel - PCI Express 3.0 x16 slot (tested with AMD RX 550 dGPU) - PCI Express 2.0 x16 slot (tested with AMD RX 550 dGPU) - PCI Express 2.0 x4 slots (tested with TL-WDN4800 WiFi adapter) - HD Audio Jack (Audio output tested only) - Front Audio Jack (Audio output tested only) not working: - Both SATA3 6.0 GB/s connectors by ASMedia not (yet) tested: - ASUS Extension Board - ASUS mPCIe Combo II connector - USB 2.0 headers - Optical S/PDIF out not (yet) working: - Software fan control: While the Nuvoton chip is correctly discovered, the numbering of the fan connectors is faulty, resulting in the wrong fan being controlled. Change-Id: I31029c78cba65cad96718132235c140c3997c815 Signed-off-by: Jan Philipp Groß <jeangrande(a)mailbox.org> --- A src/mainboard/asus/maximus_vi_gene/Kconfig A src/mainboard/asus/maximus_vi_gene/Kconfig.name A src/mainboard/asus/maximus_vi_gene/Makefile.mk A src/mainboard/asus/maximus_vi_gene/acpi/ec.asl A src/mainboard/asus/maximus_vi_gene/acpi/platform.asl A src/mainboard/asus/maximus_vi_gene/acpi/superio.asl A src/mainboard/asus/maximus_vi_gene/board_info.txt A src/mainboard/asus/maximus_vi_gene/bootblock.c A src/mainboard/asus/maximus_vi_gene/data.vbt A src/mainboard/asus/maximus_vi_gene/devicetree.cb A src/mainboard/asus/maximus_vi_gene/dsdt.asl A src/mainboard/asus/maximus_vi_gene/gma-mainboard.ads A src/mainboard/asus/maximus_vi_gene/gpio.c A src/mainboard/asus/maximus_vi_gene/hda_verb.c A src/mainboard/asus/maximus_vi_gene/romstage.c 15 files changed, 526 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/85767/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/85767?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I31029c78cba65cad96718132235c140c3997c815 Gerrit-Change-Number: 85767 Gerrit-PatchSet: 3 Gerrit-Owner: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Máté Kukri <km(a)mkukri.xyz> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Máté Kukri <km(a)mkukri.xyz> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com>

1 0

[L] Change in coreboot[main]: mb/asus: Add Maximus VI Gene (Haswell)
by Jan Philipp Groß (Code Review) 25 Dec '24

25 Dec '24

Attention is currently required from: Angel Pons, Máté Kukri, Nicholas Chin. Hello Angel Pons, Máté Kukri, Nicholas Chin, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85767?usp=email to look at the new patch set (#2). Change subject: mb/asus: Add Maximus VI Gene (Haswell) ...................................................................... mb/asus: Add Maximus VI Gene (Haswell) This port was done via autoport and subsequent manual tweaking. Working: - Haswell MRC.bin - DIMM_B1 and DIMM_B2 DDR3/DDR3L DIMM slots (DIMM_A1 and DIMM_A2 also not working on vendor firmware, assuming hardware defect) - HDMI-Out Port - RJ-45 Gigabit LAN Port - All four back panel USB 2.0 Ports - All four back panel ASMedia USB 3.0 Ports - Both back panel USB 3.0 Ports - USB 3.0 Header - All six SATA3 6.0 Gb/s connectors by Intel - PCI Express 3.0 x16 slot (tested with AMD RX 550 dGPU) - PCI Express 2.0 x16 slot (tested with AMD RX 550 dGPU) - PCI Express 2.0 x4 slots (tested with TL-WDN4800 WiFi adapter) - HD Audio Jack (Audio output tested only) - Front Audio Jack (Audio output tested only) not working: - Both SATA3 6.0 GB/s connectors by ASMedia not (yet) tested: - ASUS Extension Board - ASUS mPCIe Combo II connector - USB 2.0 headers - Optical S/PDIF out not (yet) working: - Software fan control: While the Nuvoton chip is correctly discovered, the numbering of the fan connectors is faulty, resulting in the wrong fan being controlled. Change-Id: I31029c78cba65cad96718132235c140c3997c815 Signed-off-by: Jan Philipp Groß <jeangrande(a)mailbox.org> --- A src/mainboard/asus/maximus_vi_gene/Kconfig A src/mainboard/asus/maximus_vi_gene/Kconfig.name A src/mainboard/asus/maximus_vi_gene/Makefile.mk A src/mainboard/asus/maximus_vi_gene/acpi/ec.asl A src/mainboard/asus/maximus_vi_gene/acpi/platform.asl A src/mainboard/asus/maximus_vi_gene/acpi/superio.asl A src/mainboard/asus/maximus_vi_gene/board_info.txt A src/mainboard/asus/maximus_vi_gene/bootblock.c A src/mainboard/asus/maximus_vi_gene/data.vbt A src/mainboard/asus/maximus_vi_gene/devicetree.cb A src/mainboard/asus/maximus_vi_gene/dsdt.asl A src/mainboard/asus/maximus_vi_gene/gma-mainboard.ads A src/mainboard/asus/maximus_vi_gene/gpio.c A src/mainboard/asus/maximus_vi_gene/hda_verb.c A src/mainboard/asus/maximus_vi_gene/romstage.c 15 files changed, 526 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/85767/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85767?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I31029c78cba65cad96718132235c140c3997c815 Gerrit-Change-Number: 85767 Gerrit-PatchSet: 2 Gerrit-Owner: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Máté Kukri <km(a)mkukri.xyz> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Máté Kukri <km(a)mkukri.xyz> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com>

1 0

[L] Change in coreboot[main]: mb/asus: Add Maximus VI Gene (Haswell)
by Jan Philipp Groß (Code Review) 25 Dec '24

25 Dec '24

Attention is currently required from: Angel Pons, Máté Kukri, Nicholas Chin. Jan Philipp Groß has posted comments on this change by Jan Philipp Groß. ( https://review.coreboot.org/c/coreboot/+/85767?usp=email ) Change subject: mb/asus: Add Maximus VI Gene (Haswell) ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Hey Guys, got tired of ASRock boards so I tried an ASUS board 😊 Hope you all enjoy your holidays! Best regards -- To view, visit https://review.coreboot.org/c/coreboot/+/85767?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I31029c78cba65cad96718132235c140c3997c815 Gerrit-Change-Number: 85767 Gerrit-PatchSet: 1 Gerrit-Owner: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Máté Kukri <km(a)mkukri.xyz> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Máté Kukri <km(a)mkukri.xyz> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Wed, 25 Dec 2024 13:08:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

1 0

[L] Change in coreboot[main]: mb/asus: Add Maximus VI Gene (Haswell)
by Jan Philipp Groß (Code Review) 25 Dec '24

25 Dec '24

Jan Philipp Groß has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85767?usp=email ) Change subject: mb/asus: Add Maximus VI Gene (Haswell) ...................................................................... mb/asus: Add Maximus VI Gene (Haswell) This port was done via autoport and subsequent manual tweaking. Working: - Haswell MRC.bin - DIMM_B1 and DIMM_B2 DDR3/DDR3L DIMM slots (DIMM_A1 and DIMM_A2 also not working on vendor firmware, assuming hardware defect) - HDMI-Out Port - RJ-45 Gigabit LAN Port - All four back panel USB 2.0 Ports - All four back panel ASMedia USB 3.0 Ports - Both back panel USB 3.0 Ports - USB 3.0 Header - All six SATA3 6.0 Gb/s connectors by Intel - PCI Express 3.0 x16 slot (tested with AMD RX 550 dGPU) - PCI Express 2.0 x16 slot (tested with AMD RX 550 dGPU) - PCI Express 2.0 x4 slots (tested with TL-WDN4800 WiFi adapter) - HD Audio Jack (Audio output tested only) - Front Audio Jack (Audio output tested only) not working: - Both SATA3 6.0 GB/s connectors by ASMedia not (yet) tested: - ASUS Extension Board - ASUS mPCIe Combo II connector - USB 2.0 headers - Optical S/PDIF out not (yet) working: - Software fan control: While the Nuvoton chip is correctly discovered, the numbering of the fan connectors is faulty, resulting in the wrong fan being controlled. Change-Id: I31029c78cba65cad96718132235c140c3997c815 Signed-off-by: Jan Philipp Groß <jeangrande(a)mailbox.org> --- A src/mainboard/asus/maximus_vi_gene/Kconfig A src/mainboard/asus/maximus_vi_gene/Kconfig.name A src/mainboard/asus/maximus_vi_gene/Makefile.mk A src/mainboard/asus/maximus_vi_gene/acpi/ec.asl A src/mainboard/asus/maximus_vi_gene/acpi/platform.asl A src/mainboard/asus/maximus_vi_gene/acpi/superio.asl A src/mainboard/asus/maximus_vi_gene/board_info.txt A src/mainboard/asus/maximus_vi_gene/bootblock.c A src/mainboard/asus/maximus_vi_gene/data.vbt A src/mainboard/asus/maximus_vi_gene/devicetree.cb A src/mainboard/asus/maximus_vi_gene/dsdt.asl A src/mainboard/asus/maximus_vi_gene/gma-mainboard.ads A src/mainboard/asus/maximus_vi_gene/gpio.c A src/mainboard/asus/maximus_vi_gene/hda_verb.c A src/mainboard/asus/maximus_vi_gene/romstage.c 15 files changed, 526 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/85767/1 diff --git a/src/mainboard/asus/maximus_vi_gene/Kconfig b/src/mainboard/asus/maximus_vi_gene/Kconfig new file mode 100644 index 0000000..692a3d0 --- /dev/null +++ b/src/mainboard/asus/maximus_vi_gene/Kconfig @@ -0,0 +1,28 @@ +## SPDX-License-Identifier: GPL-2.0-only + +if BOARD_ASUS_MAXIMUS_VI_GENE + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select DRIVERS_ASMEDIA_ASPM_BLACKLIST + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_GMA_HAVE_VBT + select MAINBOARD_HAS_LIBGFXINIT + select MAINBOARD_USES_IFD_GBE_REGION + select NORTHBRIDGE_INTEL_HASWELL + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_LYNXPOINT + select SUPERIO_NUVOTON_NCT6776 + +config MAINBOARD_DIR + default "asus/maximus_vi_gene" + +config MAINBOARD_PART_NUMBER + default "Maximus VI GENE" + +# FIXME: Currently unable to test. +config USBDEBUG_HCD_INDEX + default 2 +endif diff --git a/src/mainboard/asus/maximus_vi_gene/Kconfig.name b/src/mainboard/asus/maximus_vi_gene/Kconfig.name new file mode 100644 index 0000000..9dbaeec --- /dev/null +++ b/src/mainboard/asus/maximus_vi_gene/Kconfig.name @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config BOARD_ASUS_MAXIMUS_VI_GENE + bool "Maximus VI GENE" diff --git a/src/mainboard/asus/maximus_vi_gene/Makefile.mk b/src/mainboard/asus/maximus_vi_gene/Makefile.mk new file mode 100644 index 0000000..c3cf55d --- /dev/null +++ b/src/mainboard/asus/maximus_vi_gene/Makefile.mk @@ -0,0 +1,6 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += bootblock.c +bootblock-y += gpio.c +romstage-y += gpio.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/asus/maximus_vi_gene/acpi/ec.asl b/src/mainboard/asus/maximus_vi_gene/acpi/ec.asl new file mode 100644 index 0000000..16990d4 --- /dev/null +++ b/src/mainboard/asus/maximus_vi_gene/acpi/ec.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: CC-PDDC */ + +/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/asus/maximus_vi_gene/acpi/platform.asl b/src/mainboard/asus/maximus_vi_gene/acpi/platform.asl new file mode 100644 index 0000000..aff432b --- /dev/null +++ b/src/mainboard/asus/maximus_vi_gene/acpi/platform.asl @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Method(_WAK, 1) +{ + Return(Package() {0, 0}) +} + +Method(_PTS, 1) +{ +} diff --git a/src/mainboard/asus/maximus_vi_gene/acpi/superio.asl b/src/mainboard/asus/maximus_vi_gene/acpi/superio.asl new file mode 100644 index 0000000..73fa78e --- /dev/null +++ b/src/mainboard/asus/maximus_vi_gene/acpi/superio.asl @@ -0,0 +1 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ diff --git a/src/mainboard/asus/maximus_vi_gene/board_info.txt b/src/mainboard/asus/maximus_vi_gene/board_info.txt new file mode 100644 index 0000000..d3b7920 --- /dev/null +++ b/src/mainboard/asus/maximus_vi_gene/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: https://www.asus.com/ROG-Republic-Of-Gamers/MAXIMUS_VI_GENE/ +ROM protocol: SPI +Flashrom support: n +ROM package: DIP-8 (1x) +ROM socketed: y +Release year: 2013 diff --git a/src/mainboard/asus/maximus_vi_gene/bootblock.c b/src/mainboard/asus/maximus_vi_gene/bootblock.c new file mode 100644 index 0000000..9ef1f36 --- /dev/null +++ b/src/mainboard/asus/maximus_vi_gene/bootblock.c @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/pnp_ops.h> +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct6776/nct6776.h> +#include <southbridge/intel/lynxpoint/pch.h> + +#define GLOBAL_DEV PNP_DEV(0x2e, 0) +#define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1) +#define ACPI_DEV PNP_DEV(0x2e, NCT6776_ACPI) + +void mainboard_config_superio(void) +{ + nuvoton_pnp_enter_conf_state(GLOBAL_DEV); + + /* Select SIO pin mux states */ + pnp_write_config(GLOBAL_DEV, 0x1b, 0x76); + pnp_write_config(GLOBAL_DEV, 0x1c, 0x00); + pnp_write_config(GLOBAL_DEV, 0x24, 0x00); + pnp_write_config(GLOBAL_DEV, 0x27, 0x00); + pnp_write_config(GLOBAL_DEV, 0x2a, 0x40); + pnp_write_config(GLOBAL_DEV, 0x2c, 0x00); + pnp_write_config(GLOBAL_DEV, 0x2f, 0x03); + + /* Power RAM in S3 and let the PCH handle power failure actions */ + pnp_set_logical_device(ACPI_DEV); + pnp_write_config(ACPI_DEV, 0xe4, 0x70); + + nuvoton_pnp_exit_conf_state(GLOBAL_DEV); + + /* Enable UART */ + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/asus/maximus_vi_gene/data.vbt b/src/mainboard/asus/maximus_vi_gene/data.vbt new file mode 100644 index 0000000..75ba37b --- /dev/null +++ b/src/mainboard/asus/maximus_vi_gene/data.vbt Binary files differ diff --git a/src/mainboard/asus/maximus_vi_gene/devicetree.cb b/src/mainboard/asus/maximus_vi_gene/devicetree.cb new file mode 100644 index 0000000..3cf0d97 --- /dev/null +++ b/src/mainboard/asus/maximus_vi_gene/devicetree.cb @@ -0,0 +1,132 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +chip northbridge/intel/haswell + register "gpu_dp_d_hotplug" = "4" + register "spd_addresses" = "{0x50, 0x51, 0x52, 0x53}" + + chip cpu/intel/haswell + device cpu_cluster 0 on + ops haswell_cpu_bus_ops + end + end + device domain 0 on + ops haswell_pci_domain_ops + device pci 00.0 on # Desktop Host bridge + subsystemid 0x1043 0x8534 + end + device pci 01.0 on # PEG + subsystemid 0x1043 0x8534 + end + device pci 02.0 on # iGPU + subsystemid 0x1043 0x8534 + end + device pci 03.0 on # Mini-HD audio + subsystemid 0x1043 0x8534 + end + chip southbridge/intel/lynxpoint # Intel Series 8 Lynx Point PCH + register "gen1_dec" = "0x000c0291" + register "gen2_dec" = "0x007c0a01" + register "gen3_dec" = "0x00040069" + register "gpe0_en_1" = "0x40002046" + register "sata_port0_gen3_dtle" = "0x2" + register "sata_port1_gen3_dtle" = "0x2" + register "sata_port_map" = "0x3f" + device pci 14.0 on # xHCI Controller + subsystemid 0x1043 0x8534 + end + device pci 16.0 on # MEI #1 + subsystemid 0x1043 0x8534 + end + device pci 16.1 off end # MEI #2 + device pci 19.0 on # Intel Gigabit Ethernet + subsystemid 0x1043 0x859f + end + device pci 1a.0 on # USB2 EHCI #2 + subsystemid 0x1043 0x8534 + end + device pci 1b.0 on # High Definition Audio + subsystemid 0x1043 0x857f + end + device pci 1c.0 off end # RP #1 + device pci 1c.1 on # RP #2 + end + device pci 1c.2 on # RP #3 + end + device pci 1c.3 on # RP #4: ASM1061 Serial ATA Controller + subsystemid 0x1043 0x8534 + end + device pci 1c.4 on # RP #5: PCIEX4_1 + subsystemid 0x1043 0x8534 + end + device pci 1c.5 off end # RP #6 + device pci 1c.6 off end # RP #7 + device pci 1c.7 off end # RP #8 + device pci 1d.0 on # USB2 EHCI #1 + subsystemid 0x1043 0x8534 + end + device pci 1f.0 on # LPC bridge + subsystemid 0x1043 0x8534 + chip superio/nuvoton/nct6776 + device pnp 2e.0 off end # Floppy + device pnp 2e.1 off end # Parallel + device pnp 2e.2 on # UART A + io 0x60 = 0x03f8 + irq 0x70 = 4 + end + device pnp 2e.3 off end # UART B, IR + device pnp 2e.5 on # PS/2 Keyboard/Mouse + io 0x60 = 0x0060 + io 0x62 = 0x0064 + irq 0x70 = 1 # + Keyboard IRQ + irq 0x72 = 12 # + Mouse IRQ (unused) + end + device pnp 2e.6 off end # CIR + device pnp 2e.7 off end # GPIO8 + device pnp 2e.107 off end # GPIO9 + device pnp 2e.8 off end # WDT + device pnp 2e.108 on # GPIO0 + irq 0xe0 = 0xf9 # + GPIO0 direction + irq 0xe1 = 0xfd # + GPIO0 value + end + device pnp 2e.208 off end # GPIOA + device pnp 2e.308 off end # GPIO base + device pnp 2e.109 on # GPIO1 + irq 0xf0 = 0xf1 # + GPIO1 direction + irq 0xf1 = 0xf1 # + GPIO1 value + end + device pnp 2e.209 off end # GPIO2 + device pnp 2e.309 off end # GPIO3 + device pnp 2e.409 off end # GPIO4 + device pnp 2e.509 off end # GPIO5 + device pnp 2e.609 off end # GPIO6 + device pnp 2e.709 on # GPIO7 + irq 0xe0 = 0xff # + GPIO7 direction + end + device pnp 2e.a on # ACPI + irq 0xe4 = 0x10 # + Power RAM in S3 + irq 0xf0 = 0x20 + end + device pnp 2e.b on # HWM, LED + irq 0x30 = 0xe1 # + Fan RPM sense pins + io 0x60 = 0x0290 # + HWM base address + irq 0x70 = 0 + end + device pnp 2e.d off end # VID + device pnp 2e.e off end # CIR wake-up + device pnp 2e.f off end # GPIO PP/OD + device pnp 2e.14 off end # SVID + device pnp 2e.16 off end # Deep sleep + device pnp 2e.17 off end # GPIOA + end + end + device pci 1f.2 on # SATA Controller (AHCI) + subsystemid 0x1043 0x8534 + end + device pci 1f.3 on # SMBus + subsystemid 0x1043 0x8534 + end + device pci 1f.5 off end # SATA Controller (Legacy) + device pci 1f.6 off end # Thermal + end + end +end diff --git a/src/mainboard/asus/maximus_vi_gene/dsdt.asl b/src/mainboard/asus/maximus_vi_gene/dsdt.asl new file mode 100644 index 0000000..2eb0805 --- /dev/null +++ b/src/mainboard/asus/maximus_vi_gene/dsdt.asl @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 +) +{ + #include <acpi/dsdt_top.asl> + #include "acpi/platform.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/common/acpi/platform.asl> + /* global NVS and variables. */ + #include <southbridge/intel/lynxpoint/acpi/globalnvs.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> + + Device (\_SB.PCI0) + { + #include <northbridge/intel/haswell/acpi/hostbridge.asl> + #include <southbridge/intel/lynxpoint/acpi/pch.asl> + } +} diff --git a/src/mainboard/asus/maximus_vi_gene/gma-mainboard.ads b/src/mainboard/asus/maximus_vi_gene/gma-mainboard.ads new file mode 100644 index 0000000..fe20619 --- /dev/null +++ b/src/mainboard/asus/maximus_vi_gene/gma-mainboard.ads @@ -0,0 +1,18 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + -- FIXME: check this + ports : constant Port_List := + (HDMI1, + HDMI2, + HDMI3, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/asus/maximus_vi_gene/gpio.c b/src/mainboard/asus/maximus_vi_gene/gpio.c new file mode 100644 index 0000000..b82596a --- /dev/null +++ b/src/mainboard/asus/maximus_vi_gene/gpio.c @@ -0,0 +1,196 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_NATIVE, + .gpio3 = GPIO_MODE_NATIVE, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_NATIVE, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_GPIO, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio25 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio8 = GPIO_LEVEL_HIGH, + .gpio15 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio4 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, + .gpio14 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_NATIVE, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_OUTPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, + .gpio35 = GPIO_LEVEL_LOW, + .gpio48 = GPIO_LEVEL_LOW, + .gpio51 = GPIO_LEVEL_HIGH, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio55 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/asus/maximus_vi_gene/hda_verb.c b/src/mainboard/asus/maximus_vi_gene/hda_verb.c new file mode 100644 index 0000000..ae8bc7f --- /dev/null +++ b/src/mainboard/asus/maximus_vi_gene/hda_verb.c @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0900, /* Codec Vendor / Device ID: Realtek */ + 0x1043857f, /* Subsystem ID */ + 11, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x1043857f), + AZALIA_PIN_CFG(0, 0x11, 0x99430130), + AZALIA_PIN_CFG(0, 0x14, 0x01014010), + AZALIA_PIN_CFG(0, 0x15, 0x01011012), + AZALIA_PIN_CFG(0, 0x16, 0x01016011), + AZALIA_PIN_CFG(0, 0x17, 0x01012014), + AZALIA_PIN_CFG(0, 0x18, 0x01a19050), + AZALIA_PIN_CFG(0, 0x19, 0x02a19060), + AZALIA_PIN_CFG(0, 0x1a, 0x0181305f), + AZALIA_PIN_CFG(0, 0x1b, 0x02214020), + AZALIA_PIN_CFG(0, 0x1e, 0x01456140), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/asus/maximus_vi_gene/romstage.c b/src/mainboard/asus/maximus_vi_gene/romstage.c new file mode 100644 index 0000000..bb6978a --- /dev/null +++ b/src/mainboard/asus/maximus_vi_gene/romstage.c @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <stdint.h> +#include <northbridge/intel/haswell/haswell.h> +#include <southbridge/intel/lynxpoint/pch.h> + +void mainboard_config_rcba(void) +{ +} + +const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = { + /* FIXME: Length and Location are computed from IOBP values, may be inaccurate */ + /* Length, Enable, OCn#, Location */ + { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_FLEX }, + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_FLEX }, + { 0x0110, 1, 2, USB_PORT_BACK_PANEL }, + { 0x0140, 1, 2, USB_PORT_BACK_PANEL }, + { 0x0110, 1, 3, USB_PORT_BACK_PANEL }, + { 0x0110, 1, 3, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 4, USB_PORT_BACK_PANEL }, + { 0x0110, 1, 4, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 5, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 5, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 6, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 6, USB_PORT_BACK_PANEL }, +}; + +const struct usb3_port_config mainboard_usb3_ports[MAX_USB3_PORTS] = { + { 1, 0 }, + { 1, 0 }, + { 1, USB_OC_PIN_SKIP }, + { 1, 1 }, + { 1, 2 }, + { 1, 2 }, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/85767?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I31029c78cba65cad96718132235c140c3997c815 Gerrit-Change-Number: 85767 Gerrit-PatchSet: 1 Gerrit-Owner: Jan Philipp Groß <jeangrande(a)mailbox.org>

1 0

[S] Change in coreboot[main]: soc/mediatek: Distinguish pmic_init_setting function name
by Yu-Ping Wu (Code Review) 25 Dec '24

25 Dec '24

Attention is currently required from: Hung-Te Lin, Xi Chen, Yidi Lin. Yu-Ping Wu has posted comments on this change by Yidi Lin. ( https://review.coreboot.org/c/coreboot/+/85764?usp=email ) Change subject: soc/mediatek: Distinguish pmic_init_setting function name ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85764?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id591bf3089aaa2148d34c77d021c17403494a776 Gerrit-Change-Number: 85764 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Wed, 25 Dec 2024 13:06:02 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

1 0

[M] Change in coreboot[main]: soc/mediatek/mt8196: Add MT6685 Clock IC driver
by Hope Wang (Code Review) 25 Dec '24

25 Dec '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yidi Lin, Yu-Ping Wu. Hope Wang has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85734?usp=email ) Change subject: soc/mediatek/mt8196: Add MT6685 Clock IC driver ...................................................................... Patch Set 6: (8 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/85734/comment/85a2435d_afc4c6a3?us… : PS5, Line 7: adc init > Clock IC driver Done https://review.coreboot.org/c/coreboot/+/85734/comment/c1d766dc_f205f640?us… : PS5, Line 8: > > `'intial' may be misspelled - perhaps 'initial'?` […] Done https://review.coreboot.org/c/coreboot/+/85734/comment/68a727b9_7dd1b2cb?us… : PS5, Line 9: and MT6685 ADC SW intial settings > and ADC init settings Done File src/soc/mediatek/common/include/soc/mt6685_adc_init.h: PS5: > mt6685. […] Done File src/soc/mediatek/common/mt6685.c: https://review.coreboot.org/c/coreboot/+/85734/comment/62243bbb_8b7ff75d?us… : PS5, Line 38: > Please also add mt6685_{read/write}8. RTC needs both APIs. Done https://review.coreboot.org/c/coreboot/+/85734/comment/5980a0d3_e09a87d3?us… : PS5, Line 39: mt6685_get_reg_value16 > mt6685_read16 Done https://review.coreboot.org/c/coreboot/+/85734/comment/23ce9720_5f059d84?us… : PS5, Line 48: mt6685_set_reg_value16 > mt6685_write16 Done https://review.coreboot.org/c/coreboot/+/85734/comment/3df75177_7d65ad2c?us… : PS5, Line 80: mt6685_adc_init > mt6685_init Done -- To view, visit https://review.coreboot.org/c/coreboot/+/85734?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I26ae4f416202f04a8030259c49e009b19a60712e Gerrit-Change-Number: 85734 Gerrit-PatchSet: 6 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Wed, 25 Dec 2024 11:12:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com>

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit December 2024