coreboot-gerrit December 2024

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[XS] Change in coreboot[main]: mb/google/rauru: Raise little core CPU frequency from 700MHz to 2.4GHz
by Jarried Lin (Code Review) 26 Dec '24

26 Dec '24

Jarried Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85773?usp=email ) Change subject: mb/google/rauru: Raise little core CPU frequency from 700MHz to 2.4GHz ...................................................................... mb/google/rauru: Raise little core CPU frequency from 700MHz to 2.4GHz To improve boot time, raise little CPU from 700MHz to 2.4GHz at romstage (before DRAM calibration). FW logs: Check CPU freq: 2400120 KHz BUG=b:317009620 TEST=Build pass, boot ok. Change-Id: I14a31f3a51ca246b842cc0ef740c43ff5d857310 Signed-off-by: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> --- M src/mainboard/google/rauru/romstage.c 1 file changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/85773/1 diff --git a/src/mainboard/google/rauru/romstage.c b/src/mainboard/google/rauru/romstage.c index 1d9a03b..e472a70 100644 --- a/src/mainboard/google/rauru/romstage.c +++ b/src/mainboard/google/rauru/romstage.c @@ -9,12 +9,21 @@ #include <soc/mt6685.h> #include <soc/mtk_pwrsel.h> #include <soc/pcie.h> +#include <soc/pll.h> + +static void raise_little_cpu_freq(void) +{ + mt6316_buck_set_voltage(0x8, MT6316_BUCK_3, 1050000); + printk(BIOS_INFO, "get vcpul:%d\n", mt6316_buck_get_voltage(0x8, MT6316_BUCK_3)); + mt_pll_raise_little_cpu_freq(2400U * MHz); +} void platform_romstage_main(void) { irq2axi_disable(); pwrsel_init(); mt6316_init(); + raise_little_cpu_freq(); mt6363_init(); mt6363_init_pmif_arb(); mt6363_enable_vtref18(true); -- To view, visit https://review.coreboot.org/c/coreboot/+/85773?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I14a31f3a51ca246b842cc0ef740c43ff5d857310 Gerrit-Change-Number: 85773 Gerrit-PatchSet: 1 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com>

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[S] Change in blobs[main]: soc/mediatek/mt8196: Add GPUEB firmware v1.0
by Yu-Ping Wu (Code Review) 26 Dec '24

26 Dec '24

Attention is currently required from: Andy Hsu, Jarried Lin. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/blobs/+/85763?usp=email ) Change subject: soc/mediatek/mt8196: Add GPUEB firmware v1.0 ...................................................................... Patch Set 1: (2 comments) File soc/mediatek/mt8196/README.md: https://review.coreboot.org/c/blobs/+/85763/comment/8aacddb9_58a3c7a3?usp=e… : PS1, Line 203: . It will copy `tinysys-gpueb-RV33_A.mkpt_fw.img` to the SRAM of GPUEB. `, parse it, and copy the resulting image to the SRAM of GPUEB` File soc/mediatek/mt8196/tinysys-gpueb-RV33_A.mkpt_fw.img: PS1: Can we have a shorter file name please (such as `gpueb.img`)? If you think "tinysys" or "RV33_A" (I have no idea what that means) are important to mention, please mention them in the README. -- To view, visit https://review.coreboot.org/c/blobs/+/85763?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: blobs Gerrit-Branch: main Gerrit-Change-Id: I470f1575beea481cac2dcb5f3eb77587739ff2dc Gerrit-Change-Number: 85763 Gerrit-PatchSet: 1 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Andy Hsu <andy.hsu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Andy Hsu <andy.hsu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Thu, 26 Dec 2024 02:55:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: mb/google/rauru: Initialize PMICs in romstage
by Yu-Ping Wu (Code Review) 26 Dec '24

26 Dec '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yidi Lin. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85755?usp=email ) Change subject: mb/google/rauru: Initialize PMICs in romstage ...................................................................... Patch Set 4: (1 comment) File src/mainboard/google/rauru/romstage.c: https://review.coreboot.org/c/coreboot/+/85755/comment/f1efdc3a_2ad17a48?us… : PS4, Line 19: mt6363_init_pmif_arb With `mt6363_init`, this can be removed now. -- To view, visit https://review.coreboot.org/c/coreboot/+/85755?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia220db1d8d6d20e508f5e4d47054922012f6c417 Gerrit-Change-Number: 85755 Gerrit-PatchSet: 4 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Thu, 26 Dec 2024 02:49:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: soc/mediatek/mt8196: Set SPMI-P SCL/SDA SoC PD
by Yu-Ping Wu (Code Review) 26 Dec '24

26 Dec '24

Attention is currently required from: Hope Wang, Hung-Te Lin, Jarried Lin. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85751?usp=email ) Change subject: soc/mediatek/mt8196: Set SPMI-P SCL/SDA SoC PD ...................................................................... Patch Set 5: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/85751/comment/3111080a_ff2f5643?us… : PS5, Line 10: clk clock https://review.coreboot.org/c/coreboot/+/85751/comment/9c084ad1_22062ddd?us… : PS5, Line 10: spmi SPMI -- To view, visit https://review.coreboot.org/c/coreboot/+/85751?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idbf8ed8e31850ca81c823db1b25bde4a83a48c4f Gerrit-Change-Number: 85751 Gerrit-PatchSet: 5 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Thu, 26 Dec 2024 02:48:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: soc/mediatek/mt8196: Add MT6685 Clock IC driver
by Yu-Ping Wu (Code Review) 26 Dec '24

26 Dec '24

Attention is currently required from: Hung-Te Lin, Jarried Lin. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85734?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: soc/mediatek/mt8196: Add MT6685 Clock IC driver ...................................................................... Patch Set 6: (6 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/85734/comment/6887e772_d7468a87?us… : PS6, Line 10: , `.` File src/soc/mediatek/common/mt6685.c: https://review.coreboot.org/c/coreboot/+/85734/comment/e3be3939_cd3151aa?us… : PS6, Line 72: 0xFFFF Are you sure this is correct? `pmif_spmi_read` should only read 1 byte of data, so that (when shift is 0) the mask should be at most 0xFF. https://review.coreboot.org/c/coreboot/+/85734/comment/6dc7f126_6acffbb5?us… : PS6, Line 78: key_protect_setting We should use a different struct other than `mt6685_setting` if only `addr` and `val` are used. For example ``` static const struct { u16 addr; u16 val; } key_protect_setting[] = { {0x39E, 0x7A}, ... }; ``` Please also move the key_protect_setting declaration to right above this function (line #74). https://review.coreboot.org/c/coreboot/+/85734/comment/6fcdb22f_478a31f7?us… : PS6, Line 92: [MT6685] Remove "MT6685", as it's already included in the function name. https://review.coreboot.org/c/coreboot/+/85734/comment/5fffbf6a_cd19142f?us… : PS6, Line 103: MT6685 Remove "MT6685", as it's already included in the function name. https://review.coreboot.org/c/coreboot/+/85734/comment/0df96b31_d1f16cb9?us… : PS6, Line 104: 0xFFFF Same here. -- To view, visit https://review.coreboot.org/c/coreboot/+/85734?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I26ae4f416202f04a8030259c49e009b19a60712e Gerrit-Change-Number: 85734 Gerrit-PatchSet: 6 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Thu, 26 Dec 2024 02:35:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[L] Change in coreboot[main]: mb/asus/p8x7x-series: Add SABERTOOTH Z77 as a variant
by Keith Hui (Code Review) 26 Dec '24

26 Dec '24

Attention is currently required from: Keith Hui. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85768?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: mb/asus/p8x7x-series: Add SABERTOOTH Z77 as a variant ...................................................................... mb/asus/p8x7x-series: Add SABERTOOTH Z77 as a variant Copied from p8z77-v variant, then adjusted overridetree, GPIO, HDA verbs and USB port config based on boardview and vendor firmware dumps. It builds, but not hardware tested. Unlike most other variants, this one allows use of MRC raminit, if for testing. It has no serial port, but a debug port allows access to LPC bus, minus LDRQ# signal. Change-Id: I1c26e751a224491c5aa1ce1035c55955ef0ee83c Signed-off-by: Keith Hui <buurin(a)gmail.com> --- A Documentation/mainboard/asus/sabertooth_z77.md M Documentation/mainboard/index.md M src/mainboard/asus/p8x7x-series/Kconfig M src/mainboard/asus/p8x7x-series/Kconfig.name A src/mainboard/asus/p8x7x-series/variants/sabertooth_z77/board_info.txt A src/mainboard/asus/p8x7x-series/variants/sabertooth_z77/cmos.default A src/mainboard/asus/p8x7x-series/variants/sabertooth_z77/cmos.layout A src/mainboard/asus/p8x7x-series/variants/sabertooth_z77/data.vbt A src/mainboard/asus/p8x7x-series/variants/sabertooth_z77/early_init.c A src/mainboard/asus/p8x7x-series/variants/sabertooth_z77/gma-mainboard.ads A src/mainboard/asus/p8x7x-series/variants/sabertooth_z77/gpio.c A src/mainboard/asus/p8x7x-series/variants/sabertooth_z77/hda_verb.c A src/mainboard/asus/p8x7x-series/variants/sabertooth_z77/overridetree.cb 13 files changed, 681 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/85768/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85768?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1c26e751a224491c5aa1ce1035c55955ef0ee83c Gerrit-Change-Number: 85768 Gerrit-PatchSet: 2 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Keith Hui <buurin(a)gmail.com>

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[L] Change in coreboot[main]: WIP: mb/asrock: Add Z77 Extreme4
by Riku Viitanen (Code Review) 26 Dec '24

26 Dec '24

Riku Viitanen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85772?usp=email ) Change subject: WIP: mb/asrock: Add Z77 Extreme4 ...................................................................... WIP: mb/asrock: Add Z77 Extreme4 New port based on logs extracted from a board running OEM firmware. VBT extracted from a running system with "intelvbttool --inlegacy". Tested: - i7-3770K CPU (native raminit) - 2x8GB: G.skill F3-1600C9-8GAR (@1600MHz) - 4x8GB: Corsair CMY16GX3M2A2400C (@1333MHz) - libgfxinit with onboard HDMI and VGA - Gigabit Ethernet - CPU fan - PS/2 keyboard and mouse - SeaBIOS 1.16.3 booting to Linux - Internal SATA ports (ASMedia ports don't work in SeaBIOS) - Rear USB ports - me_cleaner - PCIe x16 slots, including bifurcation - PCI slots Untested: - Onboard DVI - USB headers - Other fans - Audio - eSATA - PCIe x1 slots Not working: - Resuming from S3 Change-Id: Idf028c6d411bd501b73a3c526240d0b1d6ecaa0c Signed-off-by: Riku Viitanen <riku.viitanen(a)protonmail.com> --- A src/mainboard/asrock/z77_extreme4/Kconfig A src/mainboard/asrock/z77_extreme4/Kconfig.name A src/mainboard/asrock/z77_extreme4/Makefile.mk A src/mainboard/asrock/z77_extreme4/acpi/ec.asl A src/mainboard/asrock/z77_extreme4/acpi/platform.asl A src/mainboard/asrock/z77_extreme4/acpi/superio.asl A src/mainboard/asrock/z77_extreme4/board_info.txt A src/mainboard/asrock/z77_extreme4/cmos.default A src/mainboard/asrock/z77_extreme4/cmos.layout A src/mainboard/asrock/z77_extreme4/data.vbt A src/mainboard/asrock/z77_extreme4/devicetree.cb A src/mainboard/asrock/z77_extreme4/dsdt.asl A src/mainboard/asrock/z77_extreme4/early_init.c A src/mainboard/asrock/z77_extreme4/gma-mainboard.ads A src/mainboard/asrock/z77_extreme4/gpio.c A src/mainboard/asrock/z77_extreme4/hda_verb.c A src/mainboard/asrock/z77_extreme4/mainboard.c 17 files changed, 645 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/85772/1 diff --git a/src/mainboard/asrock/z77_extreme4/Kconfig b/src/mainboard/asrock/z77_extreme4/Kconfig new file mode 100644 index 0000000..4b31543 --- /dev/null +++ b/src/mainboard/asrock/z77_extreme4/Kconfig @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: GPL-2.0-only + +if BOARD_ASROCK_Z77_EXTREME4 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select DRIVERS_ASMEDIA_ASPM_BLACKLIST + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_CMOS_DEFAULT + select HAVE_OPTION_TABLE + select INTEL_GMA_HAVE_VBT + select INTEL_INT15 + select MAINBOARD_HAS_LIBGFXINIT + select NORTHBRIDGE_INTEL_SANDYBRIDGE + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_C216 + select SUPERIO_NUVOTON_NCT6776 + select USE_NATIVE_RAMINIT + +config CBFS_SIZE + default 0x600000 + +config DRAM_RESET_GATE_GPIO + int + default 27 + +config MAINBOARD_DIR + default "asrock/z77_extreme4" + +config MAINBOARD_PART_NUMBER + default "Z77 Extreme4" + +endif diff --git a/src/mainboard/asrock/z77_extreme4/Kconfig.name b/src/mainboard/asrock/z77_extreme4/Kconfig.name new file mode 100644 index 0000000..e057b6e --- /dev/null +++ b/src/mainboard/asrock/z77_extreme4/Kconfig.name @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config BOARD_ASROCK_Z77_EXTREME4 + bool "Z77 Extreme4" diff --git a/src/mainboard/asrock/z77_extreme4/Makefile.mk b/src/mainboard/asrock/z77_extreme4/Makefile.mk new file mode 100644 index 0000000..e4b6fbf --- /dev/null +++ b/src/mainboard/asrock/z77_extreme4/Makefile.mk @@ -0,0 +1,8 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += gpio.c +romstage-y += gpio.c + +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/asrock/z77_extreme4/acpi/ec.asl b/src/mainboard/asrock/z77_extreme4/acpi/ec.asl new file mode 100644 index 0000000..16990d4 --- /dev/null +++ b/src/mainboard/asrock/z77_extreme4/acpi/ec.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: CC-PDDC */ + +/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/asrock/z77_extreme4/acpi/platform.asl b/src/mainboard/asrock/z77_extreme4/acpi/platform.asl new file mode 100644 index 0000000..a56d319 --- /dev/null +++ b/src/mainboard/asrock/z77_extreme4/acpi/platform.asl @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Method(_WAK,1) +{ + Return(Package(){0,0}) +} + +Method(_PTS,1) +{ +} diff --git a/src/mainboard/asrock/z77_extreme4/acpi/superio.asl b/src/mainboard/asrock/z77_extreme4/acpi/superio.asl new file mode 100644 index 0000000..1eae4b2 --- /dev/null +++ b/src/mainboard/asrock/z77_extreme4/acpi/superio.asl @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#undef SUPERIO_DEV +#undef SUPERIO_PNP_BASE +#define SUPERIO_DEV SIO0 +#define SUPERIO_PNP_BASE 0x2e + +#define NCT6776_SHOW_SP1 1 +#define NCT6776_SHOW_KBC 1 + +#include "superio/nuvoton/nct6776/acpi/superio.asl" diff --git a/src/mainboard/asrock/z77_extreme4/board_info.txt b/src/mainboard/asrock/z77_extreme4/board_info.txt new file mode 100644 index 0000000..3819c56 --- /dev/null +++ b/src/mainboard/asrock/z77_extreme4/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: https://www.asrock.com/mb/Intel/Z77%20Extreme4/ +ROM protocol: SPI +Flashrom support: y +ROM package: DIP-8 +ROM socketed: y +Release year: 2012 diff --git a/src/mainboard/asrock/z77_extreme4/cmos.default b/src/mainboard/asrock/z77_extreme4/cmos.default new file mode 100644 index 0000000..4501aa4 --- /dev/null +++ b/src/mainboard/asrock/z77_extreme4/cmos.default @@ -0,0 +1,8 @@ +## SPDX-License-Identifier: GPL-2.0-only + +boot_option=Fallback +debug_level=Debug +nmi=Disable +power_on_after_fail=Disable +sata_mode=AHCI +gfx_uma_size=64M diff --git a/src/mainboard/asrock/z77_extreme4/cmos.layout b/src/mainboard/asrock/z77_extreme4/cmos.layout new file mode 100644 index 0000000..557fb1c --- /dev/null +++ b/src/mainboard/asrock/z77_extreme4/cmos.layout @@ -0,0 +1,91 @@ +## SPDX-License-Identifier: GPL-2.0-only + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 2 boot_option +388 4 h 0 reboot_counter + +# ----------------------------------------------------------------- +# coreboot config options: console +395 4 e 3 debug_level + +# coreboot config options: southbridge +408 1 e 1 nmi + +409 2 e 4 power_on_after_fail +411 2 e 5 sata_mode + +# coreboot config options: northbridge +416 5 e 6 gfx_uma_size + +# Sandy Bridge MRC Scrambler Seed values +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 +960 16 r 0 mrc_scrambler_seed_chk + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations +#ID value text + +# Generic on/off enum +1 0 Disable +1 1 Enable + +# boot_option +2 0 Fallback +2 1 Normal + +# debug_level +3 0 Emergency +3 1 Alert +3 2 Critical +3 3 Error +3 4 Warning +3 5 Notice +3 6 Info +3 7 Debug +3 8 Spew + +# power_on_after_fail +4 0 Disable +4 1 Enable +4 2 Keep + +# sata_mode +5 0 AHCI +5 1 Compatible +5 2 Legacy + +# gfx_uma_size (Intel IGP Video RAM size) +6 0 32M +6 1 64M +6 2 96M +6 3 128M +6 4 160M +6 5 192M +6 6 224M +6 7 256M +6 8 288M +6 9 320M +6 10 352M +6 11 384M +6 12 416M +6 13 448M +6 14 480M +6 15 512M +6 16 1024M + +# ----------------------------------------------------------------- +checksums + +checksum 392 423 984 diff --git a/src/mainboard/asrock/z77_extreme4/data.vbt b/src/mainboard/asrock/z77_extreme4/data.vbt new file mode 100644 index 0000000..7c43dcf8 --- /dev/null +++ b/src/mainboard/asrock/z77_extreme4/data.vbt Binary files differ diff --git a/src/mainboard/asrock/z77_extreme4/devicetree.cb b/src/mainboard/asrock/z77_extreme4/devicetree.cb new file mode 100644 index 0000000..053a404 --- /dev/null +++ b/src/mainboard/asrock/z77_extreme4/devicetree.cb @@ -0,0 +1,170 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +chip northbridge/intel/sandybridge + register "gpu_dp_b_hotplug" = "4" + register "gpu_dp_c_hotplug" = "4" + register "gpu_dp_d_hotplug" = "4" + register "spd_addresses" = "{0x50, 0x51, 0x52, 0x53}" + device domain 0 on + device ref host_bridge on + subsystemid 0x1849 0x0150 + end + device ref peg10 on # limited to x8 if peg11 is plugged in + subsystemid 0x1849 0x0151 + smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthLong" "PCIE2" "SlotDataBusWidth16X" + end + device ref peg11 on # bifurcated from peg10 + subsystemid 0x1849 0x0155 + smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthLong" "PCIE3" "SlotDataBusWidth8X" + end + device ref igd on + subsystemid 0x1849 0x0162 + end + chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH + register "gen1_dec" = "0x000c0291" + register "gen2_dec" = "0x000c0241" + register "gen3_dec" = "0x000c0251" + register "pcie_port_coalesce" = "1" + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x3f" + register "spi_lvscc" = "0x2005" + register "spi_uvscc" = "0x2005" + register "superspeed_capable_ports" = "0x0000000f" + register "usb_port_config" = "{ + {1, 6, 0}, + {1, 6, 0}, + {1, 1, 1}, + {1, 1, 1}, + {1, 1, 2}, + {1, 1, 2}, + {1, 6, 3}, + {1, 6, 3}, + {1, 6, 4}, + {1, 6, 4}, + {1, 6, 6}, + {1, 1, 5}, + {1, 1, 5}, + {1, 6, 6}, + }" + register "xhci_overcurrent_mapping" = "0x00000c03" + register "xhci_switchable_ports" = "0x0000000f" + device ref xhci on + subsystemid 0x1849 0x1e31 + end + device ref mei1 on + subsystemid 0x1849 0x1e3a + end + device ref mei2 off end + device ref me_ide_r off end + device ref me_kt off end + device ref gbe off end + device ref ehci2 on + subsystemid 0x1849 0x1e2d + end + device ref hda on + subsystemid 0x1849 0x1898 + end + device ref pcie_rp1 on + subsystemid 0x1849 0x1e10 + smbios_slot_desc "SlotTypePciExpressGen2X1" "SlotLengthShort" "PCIE4" "SlotDataBusWidth1X" + end + device ref pcie_rp2 off end + device ref pcie_rp3 off end + device ref pcie_rp4 on # ASM1061 SATA Controller + subsystemid 0x1849 0x1e16 + end + device ref pcie_rp5 on # BCM57781 GbE NIC + subsystemid 0x1849 0x1e18 + end + device ref pcie_rp6 on # ASM1083 PCI bridge + subsystemid 0x1849 0x1e1a + end + device ref pcie_rp7 on + smbios_slot_desc "SlotTypePciExpressGen2X1" "SlotLengthShort" "PCIE1" "SlotDataBusWidth16X" + end + device ref pcie_rp8 on # ASM1042 USB 3.0 Controller + subsystemid 0x1849 0x1e1e + end + device ref ehci1 on + subsystemid 0x1849 0x1e26 + end + device ref pci_bridge off end + device ref lpc on + subsystemid 0x1849 0x1e44 + chip superio/nuvoton/nct6776 + device pnp 2e.0 off end # Floppy + device pnp 2e.1 off end # Parallel port + device pnp 2e.2 on # COM1 + # global + irq 0x13 = 0xff + irq 0x14 = 0xff + irq 0x1a = 0xf8 + irq 0x1b = 0x0e + irq 0x24 = 0x5c + irq 0x27 = 0xd8 + irq 0x2a = 0x62 + irq 0x2c = 0x80 + # COM1 + io 0x60 = 0x3f8 + end + device pnp 2e.3 on # COM2, IR + io 0x60 = 0x2f8 + irq 0xf1 = 0x5c + end + device pnp 2e.5 on + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 0x01 + irq 0x72 = 0x0c + end + device pnp 2e.6 off end # CIR + device pnp 2e.7 on # GPIO 6-9 + irq 0x30 = 0x00 + irq 0xe8 = 0xff + irq 0xea = 0xff + irq 0xf6 = 0xff + irq 0xf8 = 0xff + end + device pnp 2e.8 on # WDT1, GPIO0-1, GPIOA + irq 0x30 = 0x00 + irq 0xe2 = 0xff + irq 0xf0 = 0xb0 + irq 0xf1 = 0x01 + end + device pnp 2e.9 on # GPIO2-5 + irq 0x30 = 0xb6 + irq 0xe0 = 0xff + irq 0xe6 = 0xff + irq 0xea = 0xff + end + device pnp 2e.a on # ACPI + irq 0xe3 = 0x01 + irq 0xe6 = 0x4c + irq 0xf0 = 0x20 + end + device pnp 2e.b on # HWM, front panel LED + irq 0x30 = 0xe1 + io 0x60 = 0x290 + end + device pnp 2e.d on end # VID + device pnp 2e.e off end # CIR wake-up + device pnp 2e.f on end # GPIO push-pull or open drain + device pnp 2e.14 on end # SVID + device pnp 2e.16 off # Deep Sleep + irq 0x30 = 0x68 + end + device pnp 2e.17 off # GPIOA + end + end + end + device ref sata1 on + subsystemid 0x1849 0x1e02 + end + device ref smbus on + subsystemid 0x1849 0x1e22 + end + device ref sata2 off end + device ref thermal off end + end + end +end diff --git a/src/mainboard/asrock/z77_extreme4/dsdt.asl b/src/mainboard/asrock/z77_extreme4/dsdt.asl new file mode 100644 index 0000000..6203060 --- /dev/null +++ b/src/mainboard/asrock/z77_extreme4/dsdt.asl @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 // OEM revision +) +{ + #include <acpi/dsdt_top.asl> + #include "acpi/platform.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/common/acpi/platform.asl> + /* global NVS and variables. */ + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } + } +} diff --git a/src/mainboard/asrock/z77_extreme4/early_init.c b/src/mainboard/asrock/z77_extreme4/early_init.c new file mode 100644 index 0000000..585b228 --- /dev/null +++ b/src/mainboard/asrock/z77_extreme4/early_init.c @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include <device/pnp_ops.h> +#include <superio/nuvoton/nct6776/nct6776.h> +#include <superio/nuvoton/common/nuvoton.h> + +#define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1) + +void bootblock_mainboard_early_init(void) +{ + /* Enable UART */ + nuvoton_pnp_enter_conf_state(SERIAL_DEV); + pnp_set_logical_device(SERIAL_DEV); + + pnp_write_config(SERIAL_DEV, 0x2a, 0x60); + + nuvoton_pnp_exit_conf_state(SERIAL_DEV); + + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/asrock/z77_extreme4/gma-mainboard.ads b/src/mainboard/asrock/z77_extreme4/gma-mainboard.ads new file mode 100644 index 0000000..3f217ca --- /dev/null +++ b/src/mainboard/asrock/z77_extreme4/gma-mainboard.ads @@ -0,0 +1,17 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (HDMI1, -- mainboard DVI port + HDMI3, -- mainboard HDMI port + Analog, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/asrock/z77_extreme4/gpio.c b/src/mainboard/asrock/z77_extreme4/gpio.c new file mode 100644 index 0000000..7dae62c --- /dev/null +++ b/src/mainboard/asrock/z77_extreme4/gpio.c @@ -0,0 +1,179 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_NATIVE, + .gpio3 = GPIO_MODE_NATIVE, + .gpio4 = GPIO_MODE_NATIVE, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_NATIVE, + .gpio22 = GPIO_MODE_NATIVE, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio12 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_OUTPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio8 = GPIO_LEVEL_HIGH, + .gpio14 = GPIO_LEVEL_HIGH, + .gpio15 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio12 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_NATIVE, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_NATIVE, + .gpio38 = GPIO_MODE_NATIVE, + .gpio39 = GPIO_MODE_NATIVE, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_NATIVE, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_NATIVE, + .gpio51 = GPIO_MODE_NATIVE, + .gpio52 = GPIO_MODE_NATIVE, + .gpio53 = GPIO_MODE_NATIVE, + .gpio54 = GPIO_MODE_NATIVE, + .gpio55 = GPIO_MODE_NATIVE, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio72 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/asrock/z77_extreme4/hda_verb.c b/src/mainboard/asrock/z77_extreme4/hda_verb.c new file mode 100644 index 0000000..73c3ab1 --- /dev/null +++ b/src/mainboard/asrock/z77_extreme4/hda_verb.c @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0899, /* Codec Vendor / Device ID: Realtek */ + 0x18491898, /* Subsystem ID */ + 15, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x18491898), + AZALIA_PIN_CFG(0, 0x11, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x14, 0x01014010), + AZALIA_PIN_CFG(0, 0x15, 0x01011012), + AZALIA_PIN_CFG(0, 0x16, 0x01016011), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x18, 0x01a19840), + AZALIA_PIN_CFG(0, 0x19, 0x02a19950), + AZALIA_PIN_CFG(0, 0x1a, 0x0181304f), + AZALIA_PIN_CFG(0, 0x1b, 0x02214120), + AZALIA_PIN_CFG(0, 0x1c, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1d, 0x4015e601), + AZALIA_PIN_CFG(0, 0x1e, 0x01451130), + AZALIA_PIN_CFG(0, 0x1f, AZALIA_PIN_CFG_NC(0)), + + 0x80862806, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(3, 0x80860101), + AZALIA_PIN_CFG(3, 0x05, 0x18560010), + AZALIA_PIN_CFG(3, 0x06, 0x58560020), + AZALIA_PIN_CFG(3, 0x07, 0x18560030), + +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/asrock/z77_extreme4/mainboard.c b/src/mainboard/asrock/z77_extreme4/mainboard.c new file mode 100644 index 0000000..1feee6b --- /dev/null +++ b/src/mainboard/asrock/z77_extreme4/mainboard.c @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> +#include <southbridge/intel/bd82x6x/pch.h> + +static void mainboard_enable(struct device *dev) +{ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_CRT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/85772?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idf028c6d411bd501b73a3c526240d0b1d6ecaa0c Gerrit-Change-Number: 85772 Gerrit-PatchSet: 1 Gerrit-Owner: Riku Viitanen <riku.viitanen(a)protonmail.com>

1 0

[XS] Change in coreboot[main]: util/lint: Clear syntax warnings in Python 3.12
by Ariel Otilibili (Code Review) 25 Dec '24

25 Dec '24

Ariel Otilibili has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85771?usp=email ) Change subject: util/lint: Clear syntax warnings in Python 3.12 ...................................................................... util/lint: Clear syntax warnings in Python 3.12 Since Python 3.12, invalid escape sequences produce a SyntaxWarning; in the future, they will produce SyntaxError: ``` $ python3 util/lint/checkpatch_json.py util/lint/checkpatch_json.py:42: SyntaxWarning: invalid escape sequence '\d' elif re.search("^\d+:\Z",line) != "None" and line.startswith("#"): HELP: util/lint/checkpatch_json.py <input file> <output file in json> <job-id> <job-url> ``` Using raw strings clear out the warning: ``` $ python3 util/lint/checkpatch_json.py HELP: util/lint/checkpatch_json.py <input file> <output file in json> <job-id> <job-url> ``` Link: https://docs.python.org/3.12/whatsnew/3.12.html#other-language-changes Change-Id: I0177dc7f0d3013759879320afdb6ab548d356bc7 Cc: Martin Roth <gaumless(a)gmail.com> Signed-off-by: Ariel Otilibili <otilibil(a)eurecom.fr> --- M util/lint/checkpatch_json.py 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/85771/1 diff --git a/util/lint/checkpatch_json.py b/util/lint/checkpatch_json.py index 967e898..2960b85 100755 --- a/util/lint/checkpatch_json.py +++ b/util/lint/checkpatch_json.py @@ -39,7 +39,7 @@ file_path = temp[1].split(":")[0] line_number = temp[1].split(":")[1] update_struct( file_path.strip(), msg_output, str(line_number) ) - elif re.search("^\d+:\Z",line) != "None" and line.startswith("#"): + elif re.search(r"^\d+:\Z",line) != "None" and line.startswith("#"): file_path="/COMMIT_MSG" line = line.replace('#', '') line_number = int(line.split(":")[0]) + 2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85771?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0177dc7f0d3013759879320afdb6ab548d356bc7 Gerrit-Change-Number: 85771 Gerrit-PatchSet: 1 Gerrit-Owner: Ariel Otilibili Gerrit-CC: Martin L Roth <gaumless(a)gmail.com>

1 0

[S] Change in coreboot[main]: mb/google/corsola: Add new board variant Wyrdeer
by Yidi Lin (Code Review) 25 Dec '24

25 Dec '24

Yidi Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85742?usp=email ) Change subject: mb/google/corsola: Add new board variant Wyrdeer ...................................................................... mb/google/corsola: Add new board variant Wyrdeer Add a new Staryu follower device 'Wyrdeer'. And add MIPI panel support. BUG=b:379810871 TEST=emerge-staryu coreboot chromeos-bootimage and check FW screen BRANCH=corsola Change-Id: I07b73c97d8d51b32f557e31d834ffc6cfb8420ed Signed-off-by: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85742 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yidi Lin <yidilin(a)google.com> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/mainboard/google/corsola/Kconfig M src/mainboard/google/corsola/Kconfig.name M src/mainboard/google/corsola/Makefile.mk A src/mainboard/google/corsola/panel_wyrdeer.c 4 files changed, 47 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Yidi Lin: Looks good to me, approved Yu-Ping Wu: Looks good to me, approved diff --git a/src/mainboard/google/corsola/Kconfig b/src/mainboard/google/corsola/Kconfig index 41f9845..6977bd4 100644 --- a/src/mainboard/google/corsola/Kconfig +++ b/src/mainboard/google/corsola/Kconfig @@ -23,7 +23,8 @@ config BOARD_GOOGLE_STARYU_COMMON def_bool BOARD_GOOGLE_STARMIE || \ - BOARD_GOOGLE_WUGTRIO + BOARD_GOOGLE_WUGTRIO || \ + BOARD_GOOGLE_WYRDEER if BOARD_GOOGLE_CORSOLA_COMMON @@ -31,7 +32,8 @@ def_bool BOARD_GOOGLE_KINGLER_COMMON || \ BOARD_GOOGLE_MAGIKARP || \ BOARD_GOOGLE_TENTACRUEL || \ - BOARD_GOOGLE_WUGTRIO + BOARD_GOOGLE_WUGTRIO || \ + BOARD_GOOGLE_WYRDEER config BOARD_SPECIFIC_OPTIONS def_bool y @@ -70,6 +72,7 @@ select FW_CONFIG select FW_CONFIG_SOURCE_CHROMEEC_CBI select MIPI_PANEL_KD_KD101NE3_40TI if BOARD_GOOGLE_WUGTRIO + select MIPI_PANEL_KD_KD110N11_51IE if BOARD_GOOGLE_WYRDEER select MIPI_PANEL_LCE_LMFBX101117480 if BOARD_GOOGLE_WUGTRIO select MIPI_PANEL_STA_ER88577 if BOARD_GOOGLE_WUGTRIO select MIPI_PANEL_STA_HIMAX83102_J02 if BOARD_GOOGLE_STARMIE @@ -99,6 +102,7 @@ default "Veluza" if BOARD_GOOGLE_VELUZA default "Voltorb" if BOARD_GOOGLE_VOLTORB default "Wugtrio" if BOARD_GOOGLE_WUGTRIO + default "Wyrdeer" if BOARD_GOOGLE_WYRDEER config BOOT_DEVICE_SPI_FLASH_BUS int diff --git a/src/mainboard/google/corsola/Kconfig.name b/src/mainboard/google/corsola/Kconfig.name index ab6a1328..5de50c3 100644 --- a/src/mainboard/google/corsola/Kconfig.name +++ b/src/mainboard/google/corsola/Kconfig.name @@ -47,3 +47,6 @@ config BOARD_GOOGLE_WUGTRIO bool "-> Wugtrio" + +config BOARD_GOOGLE_WYRDEER + bool "-> Wyrdeer" diff --git a/src/mainboard/google/corsola/Makefile.mk b/src/mainboard/google/corsola/Makefile.mk index 6ff22c6..ef60282 100644 --- a/src/mainboard/google/corsola/Makefile.mk +++ b/src/mainboard/google/corsola/Makefile.mk @@ -29,3 +29,4 @@ ramstage-$(CONFIG_BOARD_GOOGLE_STARMIE) += panel_starmie.c ramstage-$(CONFIG_BOARD_GOOGLE_WUGTRIO) += panel_wugtrio.c +ramstage-$(CONFIG_BOARD_GOOGLE_WYRDEER) += panel_wyrdeer.c diff --git a/src/mainboard/google/corsola/panel_wyrdeer.c b/src/mainboard/google/corsola/panel_wyrdeer.c new file mode 100644 index 0000000..5ae3120 --- /dev/null +++ b/src/mainboard/google/corsola/panel_wyrdeer.c @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <soc/tps65132s.h> + +#include "gpio.h" +#include "panel.h" + +static void mipi_panel_power_on(void) +{ + struct tps65132s_cfg config = { + .i2c_bus = PMIC_I2C_BUS, + .en = GPIO_EN_PP3300_DISP_X, + .sync = GPIO_TCHPAD_INT_ODL, + }; + tps65132s_power_on(&config); +} + +static struct panel_description wyrdeer_panels[] = { + /* K&D Technology panel */ + [6] = { + .configure_backlight = backlight_control, + .power_on = mipi_panel_power_on, + .name = "KD_KD110N11_51IE", + .disp_path = DISP_PATH_MIPI, + .orientation = LB_FB_ORIENTATION_LEFT_UP, + }, +}; + +struct panel_description *get_panel_description(void) +{ + uint32_t id = panel_id() & 0xF; + if (id >= ARRAY_SIZE(wyrdeer_panels)) + return NULL; + + return &wyrdeer_panels[id]; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/85742?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I07b73c97d8d51b32f557e31d834ffc6cfb8420ed Gerrit-Change-Number: 85742 Gerrit-PatchSet: 8 Gerrit-Owner: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Xinxiong Xu <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: mb/google/corsola: Refactor mipi_panel_power_on function
by Yidi Lin (Code Review) 25 Dec '24

25 Dec '24

Yidi Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85745?usp=email ) Change subject: mb/google/corsola: Refactor mipi_panel_power_on function ...................................................................... mb/google/corsola: Refactor mipi_panel_power_on function Refactor mipi_panel_power_on function in panel-starmie.c to reduce code duplication. BUG=b:379810871 TEST=emerge-staryu coreboot chromeos-bootimage and check FW screen BRANCH=corsola Change-Id: Ic0561e57d99ab55e6dcbb7744b2228c4cebb0d88 Signed-off-by: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85745 Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yidi Lin <yidilin(a)google.com> --- M src/mainboard/google/corsola/Makefile.mk M src/mainboard/google/corsola/panel.h M src/mainboard/google/corsola/panel_starmie.c A src/mainboard/google/corsola/panel_tps65132s.c 4 files changed, 49 insertions(+), 33 deletions(-) Approvals: build bot (Jenkins): Verified Yidi Lin: Looks good to me, approved Yu-Ping Wu: Looks good to me, approved diff --git a/src/mainboard/google/corsola/Makefile.mk b/src/mainboard/google/corsola/Makefile.mk index 09e9b91..6ff22c6 100644 --- a/src/mainboard/google/corsola/Makefile.mk +++ b/src/mainboard/google/corsola/Makefile.mk @@ -22,6 +22,8 @@ ramstage-y += panel.c ramstage-y += panel_anx7625.c ramstage-y += panel_ps8640.c +ramstage-y += panel_tps65132s.c + ramstage-y += regulator.c ramstage-y += reset.c diff --git a/src/mainboard/google/corsola/panel.h b/src/mainboard/google/corsola/panel.h index a4198f3..01606f4 100644 --- a/src/mainboard/google/corsola/panel.h +++ b/src/mainboard/google/corsola/panel.h @@ -5,6 +5,7 @@ #include <soc/display.h> #include <soc/i2c.h> +#include <soc/tps65132s.h> #define BRIDGE_I2C I2C0 #define PMIC_AW37503_SLAVE 0x3E @@ -14,6 +15,7 @@ bool is_pmic_aw37503(unsigned int bus); uint32_t panel_id(void); void backlight_control(void); +void tps65132s_power_on(struct tps65132s_cfg *config); /* Return the mipi panel description from given panel id */ struct panel_description *get_panel_description(void); diff --git a/src/mainboard/google/corsola/panel_starmie.c b/src/mainboard/google/corsola/panel_starmie.c index 1de2c61..5a1228c 100644 --- a/src/mainboard/google/corsola/panel_starmie.c +++ b/src/mainboard/google/corsola/panel_starmie.c @@ -1,9 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <console/console.h> -#include <delay.h> -#include <gpio.h> -#include <soc/regulator.h> #include <soc/tps65132s.h> #include "gpio.h" @@ -11,40 +8,12 @@ static void mipi_panel_power_on(void) { - const struct tps65132s_reg_setting reg_settings[] = { - { PMIC_TPS65132_VPOS, 0x14, 0x1F }, - { PMIC_TPS65132_VNEG, 0x14, 0x1F }, - { PMIC_TPS65132_DLYX, 0x95, 0xFF }, - { PMIC_TPS65132_ASSDD, 0x5b, 0xFF }, - }; - const struct tps65132s_cfg cfg = { + struct tps65132s_cfg config = { .i2c_bus = PMIC_I2C_BUS, .en = GPIO_EN_PP3300_DISP_X, .sync = GPIO_EN_PP3300_SDBRDG_X, - .settings = reg_settings, - .setting_counts = ARRAY_SIZE(reg_settings), }; - - mainboard_set_regulator_voltage(MTK_REGULATOR_VIO18, 1800000); - mtk_i2c_bus_init(PMIC_I2C_BUS, I2C_SPEED_FAST); - - if (is_pmic_aw37503(PMIC_I2C_BUS)) { - printk(BIOS_DEBUG, "Initialize and power on PMIC AW37503\n"); - aw37503_init(PMIC_I2C_BUS); - gpio_output(GPIO_EN_PP3300_DISP_X, 1); - mdelay(2); - gpio_output(GPIO_EN_PP3300_SDBRDG_X, 1); - mdelay(3); - } else if (tps65132s_setup(&cfg) != CB_SUCCESS) { - printk(BIOS_ERR, "Failed to setup tps65132s\n"); - } - - /* DISP_RST_1V8_L */ - gpio_output(GPIO_EDPBRDG_RST_L, 1); - mdelay(1); - gpio_output(GPIO_EDPBRDG_RST_L, 0); - udelay(20); - gpio_output(GPIO_EDPBRDG_RST_L, 1); + tps65132s_power_on(&config); } static struct panel_description starmie_panels[] = { diff --git a/src/mainboard/google/corsola/panel_tps65132s.c b/src/mainboard/google/corsola/panel_tps65132s.c new file mode 100644 index 0000000..36933c0 --- /dev/null +++ b/src/mainboard/google/corsola/panel_tps65132s.c @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <delay.h> +#include <gpio.h> +#include <soc/regulator.h> +#include <soc/tps65132s.h> + +#include "gpio.h" +#include "panel.h" + +void tps65132s_power_on(struct tps65132s_cfg *config) +{ + const struct tps65132s_reg_setting reg_settings[] = { + { PMIC_TPS65132_VPOS, 0x14, 0x1F }, + { PMIC_TPS65132_VNEG, 0x14, 0x1F }, + { PMIC_TPS65132_DLYX, 0x95, 0xFF }, + { PMIC_TPS65132_ASSDD, 0x5b, 0xFF }, + }; + config->settings = reg_settings; + config->setting_counts = ARRAY_SIZE(reg_settings); + + mainboard_set_regulator_voltage(MTK_REGULATOR_VIO18, 1800000); + mtk_i2c_bus_init(config->i2c_bus, I2C_SPEED_FAST); + + if (is_pmic_aw37503(config->i2c_bus)) { + printk(BIOS_DEBUG, "Initialize and power on PMIC AW37503\n"); + aw37503_init(config->i2c_bus); + gpio_output(config->en, 1); + mdelay(2); + gpio_output(config->sync, 1); + mdelay(3); + } else if (tps65132s_setup(config) != CB_SUCCESS) { + printk(BIOS_ERR, "Failed to setup tps65132s\n"); + } + + /* DISP_RST_1V8_L */ + gpio_output(GPIO_EDPBRDG_RST_L, 1); + mdelay(1); + gpio_output(GPIO_EDPBRDG_RST_L, 0); + udelay(20); + gpio_output(GPIO_EDPBRDG_RST_L, 1); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/85745?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic0561e57d99ab55e6dcbb7744b2228c4cebb0d88 Gerrit-Change-Number: 85745 Gerrit-PatchSet: 8 Gerrit-Owner: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Xinxiong Xu <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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