coreboot-gerrit December 2024

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[main]: mb/google/rauru: Initialize PMICs in romstage
by Jarried Lin (Code Review) 26 Dec '24

26 Dec '24

Attention is currently required from: Hung-Te Lin, Yidi Lin, Yu-Ping Wu. Hello Hung-Te Lin, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85755?usp=email to look at the new patch set (#6). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/google/rauru: Initialize PMICs in romstage ...................................................................... mb/google/rauru: Initialize PMICs in romstage BUG=b:317009620 TEST=Build pass, boot ok. Change-Id: Ia220db1d8d6d20e508f5e4d47054922012f6c417 Signed-off-by: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> --- M src/mainboard/google/rauru/romstage.c 1 file changed, 10 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/85755/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/85755?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia220db1d8d6d20e508f5e4d47054922012f6c417 Gerrit-Change-Number: 85755 Gerrit-PatchSet: 6 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com>

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[XS] Change in coreboot[main]: mb/google/rauru: Raise little core CPU frequency from 700MHz to 2.4GHz
by Jarried Lin (Code Review) 26 Dec '24

26 Dec '24

Attention is currently required from: Hung-Te Lin, Yidi Lin, Yu-Ping Wu. Hello Hung-Te Lin, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85773?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/google/rauru: Raise little core CPU frequency from 700MHz to 2.4GHz ...................................................................... mb/google/rauru: Raise little core CPU frequency from 700MHz to 2.4GHz To improve boot time, raise little CPU from 700MHz to 2.4GHz at romstage (before DRAM calibration). FW logs: Check CPU freq: 2400120 KHz BUG=b:317009620 TEST=Build pass, boot ok. Change-Id: I14a31f3a51ca246b842cc0ef740c43ff5d857310 Signed-off-by: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> --- M src/mainboard/google/rauru/romstage.c 1 file changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/85773/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/85773?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I14a31f3a51ca246b842cc0ef740c43ff5d857310 Gerrit-Change-Number: 85773 Gerrit-PatchSet: 3 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com>

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[S] Change in coreboot[main]: ec/google/chromeec: Add function to detect barrel charger
by Kapil Porwal (Code Review) 26 Dec '24

26 Dec '24

Attention is currently required from: Boris Mittelberg, Caveh Jalali, Pranava Y N, Subrata Banik. Kapil Porwal has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/85765?usp=email ) Change subject: ec/google/chromeec: Add function to detect barrel charger ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/85765?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9644f0dec057f95bb0a22cdc18edc1a0234ee3a9 Gerrit-Change-Number: 85765 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-Comment-Date: Thu, 26 Dec 2024 06:14:20 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: ec/google/chromeec: Add API to check if battery is critically low
by Kapil Porwal (Code Review) 26 Dec '24

26 Dec '24

Attention is currently required from: Boris Mittelberg, Caveh Jalali, Pranava Y N, Subrata Banik. Kapil Porwal has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/85759?usp=email ) Change subject: ec/google/chromeec: Add API to check if battery is critically low ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/85759?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id1fc1df374fb4c663becc371c69b285d8b9957ff Gerrit-Change-Number: 85759 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-Comment-Date: Thu, 26 Dec 2024 06:14:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: ec/google/chromeec: Add API to check if charger is present
by Kapil Porwal (Code Review) 26 Dec '24

26 Dec '24

Attention is currently required from: Boris Mittelberg, Caveh Jalali, Pranava Y N, Subrata Banik. Kapil Porwal has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/85758?usp=email ) Change subject: ec/google/chromeec: Add API to check if charger is present ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/85758?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iadf81400f71a51c093f71fe995cacc107c50c7af Gerrit-Change-Number: 85758 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-Comment-Date: Thu, 26 Dec 2024 06:12:19 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: soc/mediatek/mt8196: Add power-saving for peripheral clocks
by Jarried Lin (Code Review) 26 Dec '24

26 Dec '24

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85774?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/mediatek/mt8196: Add power-saving for peripheral clocks ...................................................................... soc/mediatek/mt8196: Add power-saving for peripheral clocks CKSYS in MT8196 dynamically controls PERI clocks based on status: - Clock off when idle. - Clock on when busy. This reduces power consumption by turning off clocks when not needed. TEST=Build pass, boot log: mtk_cksys_init = 0x1 BUG=b:317009620 Change-Id: I70f710f068d7d882037691930a90c83adaab15d2 Signed-off-by: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> --- M src/soc/mediatek/mt8196/Makefile.mk M src/soc/mediatek/mt8196/bootblock.c M src/soc/mediatek/mt8196/include/soc/addressmap.h A src/soc/mediatek/mt8196/include/soc/mtk_cksys.h A src/soc/mediatek/mt8196/mtk_cksys.c 5 files changed, 24 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/85774/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85774?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I70f710f068d7d882037691930a90c83adaab15d2 Gerrit-Change-Number: 85774 Gerrit-PatchSet: 2 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: soc/mediatek/mt8196: Add power-saving for peripheral clocks
by Jarried Lin (Code Review) 26 Dec '24

26 Dec '24

Jarried Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85774?usp=email ) Change subject: soc/mediatek/mt8196: Add power-saving for peripheral clocks ...................................................................... soc/mediatek/mt8196: Add power-saving for peripheral clocks CKSYS in MT8196 dynamically controls PERI clocks based on status: - Clock off when idle. - Clock on when busy. This reduces power consumption by turning off clocks when not needed. TEST=Build pass BUG=b:317009620 Change-Id: I70f710f068d7d882037691930a90c83adaab15d2 Signed-off-by: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> --- M src/soc/mediatek/mt8196/Makefile.mk M src/soc/mediatek/mt8196/bootblock.c M src/soc/mediatek/mt8196/include/soc/addressmap.h A src/soc/mediatek/mt8196/include/soc/mtk_cksys.h A src/soc/mediatek/mt8196/mtk_cksys.c 5 files changed, 28 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/85774/1 diff --git a/src/soc/mediatek/mt8196/Makefile.mk b/src/soc/mediatek/mt8196/Makefile.mk index 7fe0889..a63a22f 100644 --- a/src/soc/mediatek/mt8196/Makefile.mk +++ b/src/soc/mediatek/mt8196/Makefile.mk @@ -18,6 +18,7 @@ bootblock-y += mminfra.c bootblock-y += ../common/mmu_operations.c bootblock-y += mtcmos.c +bootblock-y += mtk_cksys.c bootblock-$(CONFIG_PCI) += ../common/pcie.c pcie.c bootblock-y += tracker.c bootblock-y += ../common/wdt.c ../common/wdt_req.c wdt.c diff --git a/src/soc/mediatek/mt8196/bootblock.c b/src/soc/mediatek/mt8196/bootblock.c index 95555d1..0577338 100644 --- a/src/soc/mediatek/mt8196/bootblock.c +++ b/src/soc/mediatek/mt8196/bootblock.c @@ -6,6 +6,7 @@ #include <soc/lastbus_v2.h> #include <soc/mminfra.h> #include <soc/mmu_operations.h> +#include <soc/mtk_cksys.h> #include <soc/pll.h> #include <soc/spm_mtcmos.h> #include <soc/tracker.h> @@ -14,6 +15,7 @@ void bootblock_soc_init(void) { booker_init(); + mtk_cksys_init(); mtk_mmu_init(); bustracker_init(); lastbus_init(); diff --git a/src/soc/mediatek/mt8196/include/soc/addressmap.h b/src/soc/mediatek/mt8196/include/soc/addressmap.h index 8d0a4bb..d3ec4c6 100644 --- a/src/soc/mediatek/mt8196/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8196/include/soc/addressmap.h @@ -134,6 +134,7 @@ I2C14_DMA_BASE = IO_PHYS + 0x06500000, PERI_PAR_BCRM_BASE = IO_PHYS + 0x06610000, PERICFG_AO_SEC_BASE = IO_PHYS + 0x06630000, + PERI_MASK_IDLE_TO_CKSYS = IO_PHYS + 0x06630270, PERICFG_AO_BASE = IO_PHYS + 0x06640000, PERI_PAR_AO_DEBUG_BASE = IO_PHYS + 0x06680000, SSUSB_IPPC_BASE = IO_PHYS + 0x06703E00, diff --git a/src/soc/mediatek/mt8196/include/soc/mtk_cksys.h b/src/soc/mediatek/mt8196/include/soc/mtk_cksys.h new file mode 100644 index 0000000..fd7c485 --- /dev/null +++ b/src/soc/mediatek/mt8196/include/soc/mtk_cksys.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +#ifndef __SOC_MEDIATEK_MT8196_MTK_CKSYS_H__ +#define __SOC_MEDIATEK_MT8196_MTK_CKSYS_H__ + +#include <device/mmio.h> + +void mtk_cksys_init(void); + +#endif /* __SOC_MEDIATEK_MT8196_MTK_CKSYS_H__ */ diff --git a/src/soc/mediatek/mt8196/mtk_cksys.c b/src/soc/mediatek/mt8196/mtk_cksys.c new file mode 100644 index 0000000..9441f98 --- /dev/null +++ b/src/soc/mediatek/mt8196/mtk_cksys.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +#include <console/console.h> +#include <soc/addressmap.h> +#include <soc/mtk_cksys.h> + + +void mtk_cksys_init(void) +{ + printk(BIOS_INFO, "%s %#x\n", __func__, PERI_MASK_IDLE_TO_CKSYS); + printk(BIOS_INFO, "%s before = %#x\n", __func__, read32p(PERI_MASK_IDLE_TO_CKSYS)); + write32p(PERI_MASK_IDLE_TO_CKSYS, 0x1); + printk(BIOS_INFO, "%s after = %#x\n", __func__, read32((u32 *) PERI_MASK_IDLE_TO_CKSYS)); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/85774?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I70f710f068d7d882037691930a90c83adaab15d2 Gerrit-Change-Number: 85774 Gerrit-PatchSet: 1 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com>

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[M] Change in coreboot[main]: soc/mediatek/mt8196: Add MT6685 Clock IC driver
by Jarried Lin (Code Review) 26 Dec '24

26 Dec '24

Attention is currently required from: Hung-Te Lin. Jarried Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85734?usp=email ) Change subject: soc/mediatek/mt8196: Add MT6685 Clock IC driver ...................................................................... Patch Set 6: (2 comments) File src/soc/mediatek/common/include/soc/mt6685.h: https://review.coreboot.org/c/coreboot/+/85734/comment/ad41e54f_191d849f?us… : PS6, Line 1: SPDX-License-Identifier: GPL-2.0-only SPDX-License-Identifier: GPL-2.0-only OR MIT File src/soc/mediatek/common/mt6685.c: https://review.coreboot.org/c/coreboot/+/85734/comment/3c1523fd_92c89edc?us… : PS6, Line 1: /* SPDX-License-Identifier: GPL-2.0-only */ SPDX-License-Identifier: GPL-2.0-only OR MIT -- To view, visit https://review.coreboot.org/c/coreboot/+/85734?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I26ae4f416202f04a8030259c49e009b19a60712e Gerrit-Change-Number: 85734 Gerrit-PatchSet: 6 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Comment-Date: Thu, 26 Dec 2024 04:07:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: mb/google/rauru: Initialize PMICs in romstage
by Jarried Lin (Code Review) 26 Dec '24

26 Dec '24

Attention is currently required from: Hung-Te Lin, Yidi Lin, Yu-Ping Wu. Jarried Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85755?usp=email ) Change subject: mb/google/rauru: Initialize PMICs in romstage ...................................................................... Patch Set 5: (1 comment) File src/mainboard/google/rauru/romstage.c: https://review.coreboot.org/c/coreboot/+/85755/comment/dcd2d998_7bbc78bc?us… : PS4, Line 19: mt6363_init_pmif_arb > With `mt6363_init`, this can be removed now. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/85755?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia220db1d8d6d20e508f5e4d47054922012f6c417 Gerrit-Change-Number: 85755 Gerrit-PatchSet: 5 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Thu, 26 Dec 2024 03:21:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com>

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[XS] Change in coreboot[main]: mb/google/rauru: Initialize PMICs in romstage
by Jarried Lin (Code Review) 26 Dec '24

26 Dec '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yidi Lin. Hello Hung-Te Lin, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85755?usp=email to look at the new patch set (#5). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/google/rauru: Initialize PMICs in romstage ...................................................................... mb/google/rauru: Initialize PMICs in romstage BUG=b:317009620 TEST=Build pass, boot ok. Change-Id: Ia220db1d8d6d20e508f5e4d47054922012f6c417 Signed-off-by: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> --- M src/mainboard/google/rauru/romstage.c 1 file changed, 7 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/85755/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/85755?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia220db1d8d6d20e508f5e4d47054922012f6c417 Gerrit-Change-Number: 85755 Gerrit-PatchSet: 5 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com>

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coreboot-gerrit December 2024