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[L] Change in coreboot[main]: mb/asus/p8x7x-series: Add SABERTOOTH Z77 as a variant
by Keith Hui (Code Review) 25 Dec '24

25 Dec '24

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85768?usp=email ) Change subject: mb/asus/p8x7x-series: Add SABERTOOTH Z77 as a variant ...................................................................... mb/asus/p8x7x-series: Add SABERTOOTH Z77 as a variant Copied from p8z77-v variant, then adjusted overridetree, GPIO, HDA verbs and USB port config based on boardview and vendor firmware dumps. It builds, but not hardware tested. Unlike most other variants, this one allows use of MRC raminit, if for testing. It has no serial port, but a debug port allows access to LPC bus, minus LDRQ# signal. Change-Id: I1c26e751a224491c5aa1ce1035c55955ef0ee83c Signed-off-by: Keith Hui <buurin(a)gmail.com> --- A Documentation/mainboard/asus/sabertooth_z77.md M src/mainboard/asus/p8x7x-series/Kconfig M src/mainboard/asus/p8x7x-series/Kconfig.name A src/mainboard/asus/p8x7x-series/variants/sabertooth_z77/board_info.txt A src/mainboard/asus/p8x7x-series/variants/sabertooth_z77/cmos.default A src/mainboard/asus/p8x7x-series/variants/sabertooth_z77/cmos.layout A src/mainboard/asus/p8x7x-series/variants/sabertooth_z77/data.vbt A src/mainboard/asus/p8x7x-series/variants/sabertooth_z77/early_init.c A src/mainboard/asus/p8x7x-series/variants/sabertooth_z77/gma-mainboard.ads A src/mainboard/asus/p8x7x-series/variants/sabertooth_z77/gpio.c A src/mainboard/asus/p8x7x-series/variants/sabertooth_z77/hda_verb.c A src/mainboard/asus/p8x7x-series/variants/sabertooth_z77/overridetree.cb 12 files changed, 680 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/85768/1 diff --git a/Documentation/mainboard/asus/sabertooth_z77.md b/Documentation/mainboard/asus/sabertooth_z77.md new file mode 100644 index 0000000..0e2e8e2 --- /dev/null +++ b/Documentation/mainboard/asus/sabertooth_z77.md @@ -0,0 +1,119 @@ +# ASUS SABERTOOTH Z77 + +This page describes how to run coreboot on the [ASUS SABERTOOTH Z77]. + +## Flashing coreboot + +```{eval-rst} ++---------------------+----------------+ +| Type | Value | ++=====================+================+ +| Socketed flash | yes | ++---------------------+----------------+ +| Model | W25Q64FVA1Q | ++---------------------+----------------+ +| Size | 8 MiB | ++---------------------+----------------+ +| Package | DIP-8 | ++---------------------+----------------+ +| Write protection | yes | ++---------------------+----------------+ +| Dual BIOS feature | no | ++---------------------+----------------+ +| Internal flashing | no | ++---------------------+----------------+ +``` + +The main SPI flash cannot be written because the vendor firmware disables BIOSWE +and enables BLE/SMM_BWP flags in BIOS_CNTL for their latest BIOSes. An external +programmer is required. You must flash standalone, flashing in-circuit doesn't +work. The flash chip is socketed, so it's easy to remove and reflash. + +See page 2-2 of owners manual for location of the flash chip. + +## Debugging coreboot + +Although its NCT6779D super I/O chip can support two serial ports and there are circuitry on +this board for serial port A, there is no serial port header on it. There is however +a debug port with a 2x5 2.0mm header with this pinout, seen with back panel ports facing +your right: + +```{eval-rst} ++--------+------+------+------+------+ +| FRAME# | LAD3 | LAD2 | LAD1 | LAD0 | ++--------+------+---- -+-------------+ +| No pin | GND | CLK | +3V | +3V | ++--------+------+------+------+------+ +``` + +A cheap LPC POST card can be connected here to get the POST codes from coreboot. + +## Working + +- TBD + +## Untested + +- Everything + +## PCIe config +With Asus vendor firmware, The (black) PCIEX16_3 slot can be configured as x4 or x1. +If configured as x4, all PCIe x1 slots (PCIEX1_1 thru _3) are disabled. + +Configuring PCIEX_16_3 as x4 needs to program 0x3 to the LSB of PCHSTRP9, and configure GPIOs +in the Super I/O chip different than the default config in this board's override tree. + +How coreboot can manage this in software is to be determined. Until then support for this +feature is incomplete - coreboot programs the super I/O chip to match the PCH soft strap. + +## Extra onboard buttons + +- BIOS_FLBK + OEM firmware uses this button to facilitate a simple update mechanism + via a USB drive plugged into the bottom USB port of the USB/LAN stack. + It is connected to the proprietary AI1314 controller, along with the LED that lights + the button up. + +- MemOK! + OEM firmware uses this button for memory tuning related to overclocking. + It is connected to the proprietary EPF036 controller. + +## Extra onboard LEDs + +- SB_PWR + Standby power. Lights up whenever board is receiving power. It's all hardware + and does not concern coreboot. + +- DRAM_LED + Lights up when there is a memory problem or when vendor MemOK! feature is operating. + Connects to EPF036 meaning coreboot probably can't use it for a while. + +- CPU_LED, BOOT_DEVICE_LED, VGA_LED + Lights up when there is a problem with the associated component. In order, + they are connected to GPIOs 48, 22, 38 of Z77 PCH. In theory coreboot could use them. + +## Technology + +```{eval-rst} ++------------------+--------------------------------------------------+ +| Northbridge | :doc:`../../northbridge/intel/sandybridge/index` | ++------------------+--------------------------------------------------+ +| Southbridge | bd82x6x | ++------------------+--------------------------------------------------+ +| CPU | model_206ax | ++------------------+--------------------------------------------------+ +| Super I/O | Nuvoton NCT6779D | ++------------------+--------------------------------------------------+ +| EC | None | ++------------------+--------------------------------------------------+ +| Coprocessor | Intel Management Engine | ++------------------+--------------------------------------------------+ +``` + +## Extra resources + +- [Flash chip datasheet][W25Q64FVA1Q] + +[ASUS SABERTOOTH Z77]: https://www.asus.com/supportonly/p8z77v/helpdesk_knowledge/ +[W25Q64FVA1Q]: https://www.winbond.com/resource-files/w25q64fv%20revs%2007182017.pdf +[flashrom]: https://flashrom.org/Flashrom diff --git a/src/mainboard/asus/p8x7x-series/Kconfig b/src/mainboard/asus/p8x7x-series/Kconfig index e278b56..880254d 100644 --- a/src/mainboard/asus/p8x7x-series/Kconfig +++ b/src/mainboard/asus/p8x7x-series/Kconfig @@ -56,6 +56,13 @@ select SUPERIO_NUVOTON_NCT6779D select SUPERIO_NUVOTON_COMMON_COM_A +config BOARD_ASUS_SABERTOOTH_Z77 + select BOARD_ASUS_P8X7X_SERIES + select BOARD_ROMSIZE_KB_8192 + select DRIVERS_ASMEDIA_ASPM_BLACKLIST # for ASM1061 eSATA + select MAINBOARD_USES_IFD_GBE_REGION + select SUPERIO_NUVOTON_NCT6779D + if BOARD_ASUS_P8X7X_SERIES config MAINBOARD_DIR @@ -68,6 +75,7 @@ default "p8z77-v_lx2" if BOARD_ASUS_P8Z77_V_LX2 default "p8z77-v" if BOARD_ASUS_P8Z77_V default "p8z77-m" if BOARD_ASUS_P8Z77_M + default "sabertooth_z77" if BOARD_ASUS_SABERTOOTH_Z77 config MAINBOARD_PART_NUMBER default "P8C WS" if BOARD_ASUS_P8C_WS @@ -76,6 +84,7 @@ default "P8Z77-V LX2" if BOARD_ASUS_P8Z77_V_LX2 default "P8Z77-V" if BOARD_ASUS_P8Z77_V default "P8Z77-M" if BOARD_ASUS_P8Z77_M + default "SABERTOOTH Z77" if BOARD_ASUS_SABERTOOTH_Z77 config OVERRIDE_DEVICETREE default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" diff --git a/src/mainboard/asus/p8x7x-series/Kconfig.name b/src/mainboard/asus/p8x7x-series/Kconfig.name index a5598ca..a0f40e9 100644 --- a/src/mainboard/asus/p8x7x-series/Kconfig.name +++ b/src/mainboard/asus/p8x7x-series/Kconfig.name @@ -17,3 +17,6 @@ config BOARD_ASUS_P8Z77_M bool "P8Z77-M" + +config BOARD_ASUS_SABERTOOTH_Z77 + bool "SABERTOOTH Z77" diff --git a/src/mainboard/asus/p8x7x-series/variants/sabertooth_z77/board_info.txt b/src/mainboard/asus/p8x7x-series/variants/sabertooth_z77/board_info.txt new file mode 100644 index 0000000..de2951d --- /dev/null +++ b/src/mainboard/asus/p8x7x-series/variants/sabertooth_z77/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: https://www.asus.com/supportonly/sabertooth%20z77/helpdesk_knowledge/ +ROM package: DIP-8 +ROM protocol: SPI +ROM socketed: y +Flashrom support: y +Release year: 2012 diff --git a/src/mainboard/asus/p8x7x-series/variants/sabertooth_z77/cmos.default b/src/mainboard/asus/p8x7x-series/variants/sabertooth_z77/cmos.default new file mode 100644 index 0000000..4501aa4 --- /dev/null +++ b/src/mainboard/asus/p8x7x-series/variants/sabertooth_z77/cmos.default @@ -0,0 +1,8 @@ +## SPDX-License-Identifier: GPL-2.0-only + +boot_option=Fallback +debug_level=Debug +nmi=Disable +power_on_after_fail=Disable +sata_mode=AHCI +gfx_uma_size=64M diff --git a/src/mainboard/asus/p8x7x-series/variants/sabertooth_z77/cmos.layout b/src/mainboard/asus/p8x7x-series/variants/sabertooth_z77/cmos.layout new file mode 100644 index 0000000..493a3fb --- /dev/null +++ b/src/mainboard/asus/p8x7x-series/variants/sabertooth_z77/cmos.layout @@ -0,0 +1,90 @@ +## SPDX-License-Identifier: GPL-2.0-only + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 2 boot_option +388 4 h 0 reboot_counter + +# ----------------------------------------------------------------- +# coreboot config options: console +395 4 e 3 debug_level + +# coreboot config options: southbridge +408 1 e 1 nmi + +409 2 e 4 power_on_after_fail +411 2 e 5 sata_mode + +# coreboot config options: northbridge +416 5 e 6 gfx_uma_size + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations +#ID value text + +# Generic on/off enum +1 0 Disable +1 1 Enable + +# boot_option +2 0 Fallback +2 1 Normal + +# debug_level +3 0 Emergency +3 1 Alert +3 2 Critical +3 3 Error +3 4 Warning +3 5 Notice +3 6 Info +3 7 Debug +3 8 Spew + +# power_on_after_fail +4 0 Disable +4 1 Enable +4 2 Keep + +# sata_mode +5 0 AHCI +5 1 Compatible +5 2 Legacy + +# gfx_uma_size (Intel IGP Video RAM size) +6 0 32M +6 1 64M +6 2 96M +6 3 128M +6 4 160M +6 5 192M +6 6 224M +6 7 256M +6 8 288M +6 9 320M +6 10 352M +6 11 384M +6 12 416M +6 13 448M +6 14 480M +6 15 512M +6 16 1024M + +# Generic yes/no enum +7 0 No +7 1 Yes + +# ----------------------------------------------------------------- +checksums + +checksum 392 423 984 diff --git a/src/mainboard/asus/p8x7x-series/variants/sabertooth_z77/data.vbt b/src/mainboard/asus/p8x7x-series/variants/sabertooth_z77/data.vbt new file mode 100644 index 0000000..625bcdf --- /dev/null +++ b/src/mainboard/asus/p8x7x-series/variants/sabertooth_z77/data.vbt Binary files differ diff --git a/src/mainboard/asus/p8x7x-series/variants/sabertooth_z77/early_init.c b/src/mainboard/asus/p8x7x-series/variants/sabertooth_z77/early_init.c new file mode 100644 index 0000000..9c9c521 --- /dev/null +++ b/src/mainboard/asus/p8x7x-series/variants/sabertooth_z77/early_init.c @@ -0,0 +1,69 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include <device/pnp_ops.h> +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct6779d/nct6779d.h> +#include <southbridge/intel/common/rcba.h> +#include <southbridge/intel/common/gpio.h> +#include <northbridge/intel/sandybridge/raminit.h> +#include <northbridge/intel/sandybridge/pei_data.h> + +#define GLOBAL_DEV PNP_DEV(0x2e, 0) +#define ACPI_DEV PNP_DEV(0x2e, NCT6779D_ACPI) +#define GPIO_DEV PNP_DEV(0x2e, NCT6779D_GPIO12345678_V) + +void bootblock_mainboard_early_init(void) +{ + nuvoton_pnp_enter_conf_state(GLOBAL_DEV); + + /* Enable SIO GPIO5. GP54 controls two ASM1440 PCIe switches that route + * PCH PCIe lanes 2-4 to various places. + * + * [7:5] Unused, set as input + * [4] QSWU5, QSWU6 (PCH PCIe lanes 2-4 assignments) + * 0 = PCIEX1_2, PCIEX1_1, PCIEX1_3 respectively + * 1 = PCIEX16_3 lanes 2-4 + * [3] VCCSA_VID input from CPU + * [2] VCCIO_SEL input from CPU + * [1:0] Connect to BIOS flashback chip, direction unknown, set as input + */ + + pnp_set_logical_device(GPIO_DEV); + pnp_write_config(GPIO_DEV, 0x30, 0x20); + pnp_write_config(GPIO_DEV, 0xf4, 0xef); + + /* PCHSTRP9[PCIEPCS1] soft strap tells us how PCIe lanes 1-4 are configured. */ + u32 pciepcs1 = RCBA32(0x400) & 0x3; + + /* TODO: If we have a way to change PCHSTRP9[PCIEPCS1], sense card presence on + * PCIEX16_3 using PCH GPIO7 and decide how to reconfigure the lanes. */ + + u8 gpio5 = (pciepcs1 == 3) ? 0x10 : 0; + + pnp_write_config(GPIO_DEV, 0xf5, gpio5); + + /* Select SIO pin states */ + pnp_write_config(GLOBAL_DEV, 0x1a, 0x08); + pnp_write_config(GLOBAL_DEV, 0x2c, 0x00); + + /* Power RAM in S3 */ + pnp_set_logical_device(ACPI_DEV); + pnp_write_config(ACPI_DEV, 0xe4, 0x10); + + nuvoton_pnp_exit_conf_state(GLOBAL_DEV); + + /* Board has no serial port. Need to enable console output somewhere else. */ +} + +void mainboard_fill_pei_data(struct pei_data *pei) +{ + /* + * USB 3 mode settings. + * See p8z77-m variant for required changes if you want to configure these + * via nvram options. + */ + pei->usb3.mode = 1; + pei->usb3.preboot_support = 1; + pei->usb3.xhci_streams = 1; +} diff --git a/src/mainboard/asus/p8x7x-series/variants/sabertooth_z77/gma-mainboard.ads b/src/mainboard/asus/p8x7x-series/variants/sabertooth_z77/gma-mainboard.ads new file mode 100644 index 0000000..e6b0407 --- /dev/null +++ b/src/mainboard/asus/p8x7x-series/variants/sabertooth_z77/gma-mainboard.ads @@ -0,0 +1,19 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP1, + HDMI1, + HDMI2, + HDMI3, + Analog, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/asus/p8x7x-series/variants/sabertooth_z77/gpio.c b/src/mainboard/asus/p8x7x-series/variants/sabertooth_z77/gpio.c new file mode 100644 index 0000000..480a166 --- /dev/null +++ b/src/mainboard/asus/p8x7x-series/variants/sabertooth_z77/gpio.c @@ -0,0 +1,185 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_NATIVE, + .gpio3 = GPIO_MODE_NATIVE, + .gpio4 = GPIO_MODE_NATIVE, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, /* PCIEX16_3 card presence, active low */ + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_GPIO, + .gpio21 = GPIO_MODE_NATIVE, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio20 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_OUTPUT, /* BOOT_DEVICE_LED */ + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio15 = GPIO_LEVEL_LOW, + .gpio22 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_HIGH, + .gpio31 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio1 = GPIO_INVERT, + .gpio7 = GPIO_INVERT, + .gpio8 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_NATIVE, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_NATIVE, + .gpio38 = GPIO_MODE_GPIO, /* VGA_LED */ + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, /* CPU_LED */ + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_NATIVE, + .gpio51 = GPIO_MODE_NATIVE, + .gpio52 = GPIO_MODE_NATIVE, + .gpio53 = GPIO_MODE_NATIVE, + .gpio54 = GPIO_MODE_NATIVE, + .gpio55 = GPIO_MODE_NATIVE, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_OUTPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_OUTPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, + .gpio38 = GPIO_LEVEL_LOW, + .gpio48 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, /* SMBus Link 1 to various onboard devices */ +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/asus/p8x7x-series/variants/sabertooth_z77/hda_verb.c b/src/mainboard/asus/p8x7x-series/variants/sabertooth_z77/hda_verb.c new file mode 100644 index 0000000..48e03a5 --- /dev/null +++ b/src/mainboard/asus/p8x7x-series/variants/sabertooth_z77/hda_verb.c @@ -0,0 +1,99 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0892, /* Codec Vendor / Device ID: Realtek ALC892 */ + 0x104384fb, /* Subsystem ID */ + 15, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x104384fb), + AZALIA_PIN_CFG(0, 0x11, AZALIA_PIN_DESC( + AZALIA_INTEGRATED, + AZALIA_ATAPI, + AZALIA_SPDIF_OUT, + AZALIA_ATAPI_INTERNAL, + AZALIA_COLOR_UNKNOWN, + AZALIA_NO_JACK_PRESENCE_DETECT, + 4, 0)), /* SPDIF out 2 */ + AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)), /* Digital mic */ + AZALIA_PIN_CFG(0, 0x14, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_REAR_PANEL, + AZALIA_SPEAKER, + AZALIA_STEREO_MONO_1_8, + AZALIA_BLACK, + 0, 1, 0)), /* Port A */ + AZALIA_PIN_CFG(0, 0x15, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_REAR_PANEL, + AZALIA_MIC_IN, + AZALIA_STEREO_MONO_1_8, + AZALIA_PINK, + 0, 1, 2)), /* Port B */ + AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_REAR_PANEL, + AZALIA_LINE_IN, + AZALIA_STEREO_MONO_1_8, + AZALIA_BLUE, + 0, 1, 1)), /* Port C */ + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_REAR_PANEL, + AZALIA_LINE_OUT, + AZALIA_STEREO_MONO_1_8, + AZALIA_GREEN, + 0, 1, 4)), /* Port D */ + AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_FRONT, + AZALIA_LINE_OUT, + AZALIA_STEREO_MONO_1_8, + AZALIA_GREEN, + 0xc, 5, 0)), /* Port E */ + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_FRONT, + AZALIA_MIC_IN, + AZALIA_STEREO_MONO_1_8, + AZALIA_PINK, + 0xc, 5, 0)), /* Port F */ + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_REAR_PANEL, + AZALIA_SPEAKER, + AZALIA_STEREO_MONO_1_8, + AZALIA_ORANGE, + 0, 5, 15)), /* Port G */ + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_REAR_PANEL, + AZALIA_SPEAKER, + AZALIA_STEREO_MONO_1_8, + AZALIA_GREY, + 0xc, 2, 0)), /* Port H */ + AZALIA_PIN_CFG(0, 0x1c, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1d, 0x4005e601), /* Beep */ + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_REAR_PANEL, + AZALIA_SPDIF_OUT, + AZALIA_OPTICAL, + AZALIA_BLACK, + AZALIA_NO_JACK_PRESENCE_DETECT, + 3, 0)), + AZALIA_PIN_CFG(0, 0x1f, AZALIA_PIN_CFG_NC(0)), /* SPDIF in */ + + 0x80862806, /* Codec Vendor / Device ID: Intel HDMI */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(3, 0x80860101), + AZALIA_PIN_CFG(3, 0x05, 0x58560010), + AZALIA_PIN_CFG(3, 0x06, 0x18560020), + AZALIA_PIN_CFG(3, 0x07, 0x18560030), + +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/asus/p8x7x-series/variants/sabertooth_z77/overridetree.cb b/src/mainboard/asus/p8x7x-series/variants/sabertooth_z77/overridetree.cb new file mode 100644 index 0000000..a26a9c2 --- /dev/null +++ b/src/mainboard/asus/p8x7x-series/variants/sabertooth_z77/overridetree.cb @@ -0,0 +1,72 @@ +## SPDX-License-Identifier: GPL-2.0-only + +chip northbridge/intel/sandybridge + device domain 0 on + subsystemid 0x1043 0x84ca inherit + device ref peg11 on end # PCIEX_16_2 + chip southbridge/intel/bd82x6x + register "usb_port_config" = "{ + { 1, 9, 0 }, + { 1, 9, 0 }, + { 1, 9, 1 }, + { 1, 2, 1 }, + { 1, 2, 2 }, + { 1, 2, 2 }, + { 1, 2, 3 }, + { 1, 2, 3 }, + { 1, 9, 4 }, + { 1, 9, 4 }, + { 1, 8, 5 }, + { 1, 8, 5 }, + { 1, 8, 6 }, + { 1, 8, 6 } + }" + register "gen1_dec" = "0x000c0291" + + device ref gbe on end + device ref pcie_rp1 on end # PCIEX_16_3 (electrical x1 or x4) + device ref pcie_rp2 on end # PCIEX1_2 + device ref pcie_rp3 on end # PCIEX1_1 + device ref pcie_rp4 on end # PCIEX1_3 + device ref pcie_rp5 on end # ASM1042 USB3 + # device ref pcie_rp6 on end 82579 LAN = gbe above + device ref pcie_rp7 on end # ASM1061 SATA (ESATA6G) + device ref pcie_rp8 on end # ASM1061 SATA (SATA6G_E12) + + device ref lpc on + chip superio/nuvoton/nct6779d + device pnp 2e.1 off end # Parallel + device pnp 2e.2 off end # UART A + device pnp 2e.3 off end # UART B, IR + device pnp 2e.5 off end # PS2 KBC + device pnp 2e.6 off end # CIR + device pnp 2e.7 off end # GPIOs 6-8 + device pnp 2e.8 off end # WDT1 GPIO 0-1 + device pnp 2e.109 on end # GPIO1 + device pnp 2e.209 on # GPIO2 + drq 0xe0 = 0xdf + end + device pnp 2e.509 on end # GPIO5 + device pnp 2e.a on # ACPI + drq 0xe3 = 0x04 # Thermal shutdown event issued + drq 0xe7 = 0x11 # Enable 3VSBS to power RAM on S3 + drq 0xf2 = 0x5d # Enable PME + end + device pnp 2e.b on # H/W Monitor, FP LED + io 0x60 = 0x290 + io 0x62 = 0 + irq 0x70 = 0 + end + device pnp 2e.d off end # WDT1 + device pnp 2e.e off end # CIR wake-up + device pnp 2e.f on # Push-pull/Open-drain + drq 0xe4 = 0xfc # GP5 PP + drq 0xe6 = 0x7f # GP7 PP + end + device pnp 2e.14 on end # Port 80 UART + device pnp 2e.16 off end # Deep sleep + end + end + end + end +end -- To view, visit https://review.coreboot.org/c/coreboot/+/85768?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1c26e751a224491c5aa1ce1035c55955ef0ee83c Gerrit-Change-Number: 85768 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com>

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[XL] Change in coreboot[main]: util/intelp2m: Rework platforms and fields packages
by Maxim (Code Review) 25 Dec '24

25 Dec '24

Attention is currently required from: Daniel Maslowski, David Hendricks. Hello Daniel Maslowski, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/71167?usp=email to look at the new patch set (#22). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: util/intelp2m: Rework platforms and fields packages ...................................................................... util/intelp2m: Rework platforms and fields packages - embed the base platform and redefine its methods if they differ; - separate the macro structures from the platform; - move more functions to common; - undo use of a single global instance of the microstructure. TEST: 1) 'make test' = PASS 2) './intelp2m -p cnl -iiii -file inteltool.log' = gpio.h before and after the commit is the same. Change-Id: I2e0aa56efa2430ac6524c6977f8b6fd13113edf9 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M util/intelp2m/fields/cb/cb.go M util/intelp2m/fields/cb/cb_test.go M util/intelp2m/fields/fields.go M util/intelp2m/fields/fsp/fsp.go M util/intelp2m/fields/fsp/fsp_test.go M util/intelp2m/fields/raw/raw.go M util/intelp2m/fields/raw/raw_test.go M util/intelp2m/fields/test/suite.go M util/intelp2m/parser/parser.go M util/intelp2m/platforms/adl/adl_test.go M util/intelp2m/platforms/adl/macro.go M util/intelp2m/platforms/adl/template.go M util/intelp2m/platforms/apl/apl_test.go M util/intelp2m/platforms/apl/macro.go M util/intelp2m/platforms/apl/template.go M util/intelp2m/platforms/cnl/cnl_test.go M util/intelp2m/platforms/cnl/macro.go M util/intelp2m/platforms/cnl/template.go A util/intelp2m/platforms/common/common.go M util/intelp2m/platforms/common/macro.go A util/intelp2m/platforms/common/register/helper.go M util/intelp2m/platforms/ebg/ebg_test.go M util/intelp2m/platforms/ebg/macro.go M util/intelp2m/platforms/ebg/template.go D util/intelp2m/platforms/interfaces.go M util/intelp2m/platforms/jsl/jsl_test.go M util/intelp2m/platforms/jsl/macro.go M util/intelp2m/platforms/jsl/template.go M util/intelp2m/platforms/lbg/lbg_test.go M util/intelp2m/platforms/lbg/macro.go M util/intelp2m/platforms/lbg/template.go M util/intelp2m/platforms/mtl/macro.go M util/intelp2m/platforms/mtl/mtl_test.go M util/intelp2m/platforms/mtl/template.go A util/intelp2m/platforms/platforms.go M util/intelp2m/platforms/snr/macro.go M util/intelp2m/platforms/snr/snr_test.go M util/intelp2m/platforms/snr/template.go M util/intelp2m/platforms/test/suite.go M util/intelp2m/platforms/tgl/macro.go M util/intelp2m/platforms/tgl/template.go M util/intelp2m/platforms/tgl/tgl_test.go 42 files changed, 1,120 insertions(+), 1,569 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/71167/22 -- To view, visit https://review.coreboot.org/c/coreboot/+/71167?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2e0aa56efa2430ac6524c6977f8b6fd13113edf9 Gerrit-Change-Number: 71167 Gerrit-PatchSet: 22 Gerrit-Owner: Maxim <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Daniel Maslowski <info(a)orangecms.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-CC: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Daniel Maslowski <info(a)orangecms.org> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com>

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[L] Change in coreboot[main]: util/intelp2m: Move remapping reset source to common
by Maxim (Code Review) 25 Dec '24

25 Dec '24

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85731?usp=email to look at the new patch set (#5). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: util/intelp2m: Move remapping reset source to common ...................................................................... util/intelp2m: Move remapping reset source to common TEST: 'make test' = PASS Change-Id: I315541b12f5f1fdf7c97c2ff8ddd305e30a447cc Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M util/intelp2m/platforms/adl/macro.go M util/intelp2m/platforms/apl/macro.go M util/intelp2m/platforms/cnl/macro.go M util/intelp2m/platforms/common/common.go M util/intelp2m/platforms/common/macro.go M util/intelp2m/platforms/ebg/macro.go M util/intelp2m/platforms/jsl/macro.go M util/intelp2m/platforms/lbg/macro.go M util/intelp2m/platforms/mtl/macro.go M util/intelp2m/platforms/snr/macro.go M util/intelp2m/platforms/tgl/macro.go 11 files changed, 107 insertions(+), 147 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/85731/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/85731?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I315541b12f5f1fdf7c97c2ff8ddd305e30a447cc Gerrit-Change-Number: 85731 Gerrit-PatchSet: 5 Gerrit-Owner: Maxim <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: util/intelp2m/platforms: Add support for Elkhart Lake
by Maxim (Code Review) 25 Dec '24

25 Dec '24

Attention is currently required from: Alexander Couzens. Maxim has uploaded a new patch set (#5) to the change originally created by Alexander Couzens. ( https://review.coreboot.org/c/coreboot/+/84191?usp=email ) The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: util/intelp2m/platforms: Add support for Elkhart Lake ...................................................................... util/intelp2m/platforms: Add support for Elkhart Lake TEST: - 'make test' = PASS; - 'intelp2m -p ehl -file parser/testlog/inteltool_test.log' = no errors. Change-Id: I0f60d182bc5cc3d0d1d1177fbda0cfe8e2279e46 Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M Documentation/util/intelp2m/index.md M util/intelp2m/cli/options.go M util/intelp2m/config/p2m/config.go A util/intelp2m/platforms/ehl/ehl_test.go A util/intelp2m/platforms/ehl/macro.go A util/intelp2m/platforms/ehl/template.go M util/intelp2m/platforms/platforms.go 7 files changed, 172 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/84191/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/84191?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0f60d182bc5cc3d0d1d1177fbda0cfe8e2279e46 Gerrit-Change-Number: 84191 Gerrit-PatchSet: 5 Gerrit-Owner: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Maxim <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: coreboot org <coreboot.org(a)gmail.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu>

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[S] Change in coreboot[main]: mb/birman: Add A/B flashmap for birman
by Bao Zheng (Code Review) 25 Dec '24

25 Dec '24

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Zheng Bao. Hello Felix Held, Fred Reitberger, Jason Glenesk, Zheng Bao, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85766?usp=email to look at the new patch set (#3). Change subject: mb/birman: Add A/B flashmap for birman ...................................................................... mb/birman: Add A/B flashmap for birman Change-Id: I743a3862791c3a36c1e4fca2334cc7dc2703dfb6 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M src/mainboard/amd/birman/Kconfig A src/mainboard/amd/birman/board_glinda_ab.fmd M src/mainboard/amd/birman_plus/Kconfig A src/mainboard/amd/birman_plus/board_glinda_ab.fmd 4 files changed, 36 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/85766/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/85766?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I743a3862791c3a36c1e4fca2334cc7dc2703dfb6 Gerrit-Change-Number: 85766 Gerrit-PatchSet: 3 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

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[M] Change in coreboot[main]: soc/amd: Add A/B recovery support to AMD SOC
by Bao Zheng (Code Review) 25 Dec '24

25 Dec '24

Attention is currently required from: Bao Zheng, Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, Zheng Bao. Hello Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, Zheng Bao, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85647?usp=email to look at the new patch set (#4). Change subject: soc/amd: Add A/B recovery support to AMD SOC ...................................................................... soc/amd: Add A/B recovery support to AMD SOC Copy the settings from Cezanne. 1. Add A/B data address to command line. 2. Enable CBFS verificatin if A/B recovery is enabled. 3. Do not compress the bootblock binary. Change-Id: Iaa8c4175285c5ceb16972ea57f0c0ca0403d8b84 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M src/soc/amd/glinda/Kconfig M src/soc/amd/glinda/Makefile.mk M src/soc/amd/phoenix/Kconfig M src/soc/amd/phoenix/Makefile.mk 4 files changed, 48 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/85647/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/85647?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iaa8c4175285c5ceb16972ea57f0c0ca0403d8b84 Gerrit-Change-Number: 85647 Gerrit-PatchSet: 4 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

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[M] Change in coreboot[main]: mb/birman: Add A/B flashmap for birman
by Bao Zheng (Code Review) 25 Dec '24

25 Dec '24

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Zheng Bao. Hello Felix Held, Fred Reitberger, Jason Glenesk, Zheng Bao, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85766?usp=email to look at the new patch set (#2). Change subject: mb/birman: Add A/B flashmap for birman ...................................................................... mb/birman: Add A/B flashmap for birman Change-Id: I743a3862791c3a36c1e4fca2334cc7dc2703dfb6 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M src/mainboard/amd/birman/Kconfig A src/mainboard/amd/birman/board_glinda_ab.fmd M src/mainboard/amd/birman/board_phoenix.fmd M src/mainboard/amd/birman_plus/Kconfig A src/mainboard/amd/birman_plus/board_glinda_ab.fmd 5 files changed, 45 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/85766/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85766?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I743a3862791c3a36c1e4fca2334cc7dc2703dfb6 Gerrit-Change-Number: 85766 Gerrit-PatchSet: 2 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

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[M] Change in coreboot[main]: util/intelp2m/platforms: Add support for Elkhart Lake
by Maxim (Code Review) 25 Dec '24

25 Dec '24

Attention is currently required from: Alexander Couzens. Maxim has posted comments on this change by Alexander Couzens. ( https://review.coreboot.org/c/coreboot/+/84191?usp=email ) Change subject: util/intelp2m/platforms: Add support for Elkhart Lake ...................................................................... Patch Set 4: (6 comments) Patchset: PS4: 1) Add unit tests. 2) Rebase to the top of the topic `pad2macro` - https://review.coreboot.org/q/topic:%22pad2macro%22 . 3) Use `Apollo Lake SoC` as the base platform. 4) `make test` = PASS. 5) `./intelp2m -platform ehl -file parser/testlog/inteltool_test.log` = no errors File util/intelp2m/platforms/ehl/macro.go: https://review.coreboot.org/c/coreboot/+/84191/comment/e0a89480_d4a50b8c?us… : PS3, Line 151: func (PlatformSpecific) GpiMacroAdd() { > ```go […] Done https://review.coreboot.org/c/coreboot/+/84191/comment/5c8f5fb3_580efce5?us… : PS3, Line 204: func (PlatformSpecific) GpoMacroAdd() { > ```go […] Done https://review.coreboot.org/c/coreboot/+/84191/comment/98108515_0fce05ba?us… : PS3, Line 236: func (PlatformSpecific) NativeFunctionMacroAdd() { > ```go […] Done https://review.coreboot.org/c/coreboot/+/84191/comment/46c12844_6cc4e85a?us… : PS3, Line 268: func (PlatformSpecific) NoConnMacroAdd() { > ```go […] Done https://review.coreboot.org/c/coreboot/+/84191/comment/d97a7188_680ff074?us… : PS3, Line 302: macro := common.GetInstanceMacro(PlatformSpecific{}, fields.InterfaceGet()) > ```go […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/84191?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0f60d182bc5cc3d0d1d1177fbda0cfe8e2279e46 Gerrit-Change-Number: 84191 Gerrit-PatchSet: 4 Gerrit-Owner: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Maxim <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: coreboot org <coreboot.org(a)gmail.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Comment-Date: Wed, 25 Dec 2024 14:47:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Maxim <max.senia.poliak(a)gmail.com>

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[M] Change in coreboot[main]: util/intelp2m/platforms: Add support for Elkhart Lake
by Maxim (Code Review) 25 Dec '24

25 Dec '24

Attention is currently required from: Alexander Couzens. Maxim has uploaded a new patch set (#4) to the change originally created by Alexander Couzens. ( https://review.coreboot.org/c/coreboot/+/84191?usp=email ) The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: util/intelp2m/platforms: Add support for Elkhart Lake ...................................................................... util/intelp2m/platforms: Add support for Elkhart Lake TEST: - 'make test' = PASS; - 'intelp2m -p ehl -file parser/testlog/inteltool_test.log' = no errors. Change-Id: I0f60d182bc5cc3d0d1d1177fbda0cfe8e2279e46 Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M Documentation/util/intelp2m/index.md M util/intelp2m/cli/options.go M util/intelp2m/config/p2m/config.go A util/intelp2m/platforms/ehl/ehl_test.go A util/intelp2m/platforms/ehl/macro.go A util/intelp2m/platforms/ehl/template.go M util/intelp2m/platforms/platforms.go 7 files changed, 189 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/84191/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/84191?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0f60d182bc5cc3d0d1d1177fbda0cfe8e2279e46 Gerrit-Change-Number: 84191 Gerrit-PatchSet: 4 Gerrit-Owner: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Maxim <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: coreboot org <coreboot.org(a)gmail.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu>

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[S] Change in coreboot[main]: mb/google/nissa/var/telith: Disable stylus function
by Subrata Banik (Code Review) 25 Dec '24

25 Dec '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85738?usp=email ) Change subject: mb/google/nissa/var/telith: Disable stylus function ...................................................................... mb/google/nissa/var/telith: Disable stylus function Disable stylus function based on hardware schematic diagram.Because the external environment is floating, EE requires setting GPIO output to be pulled high or low. BUG=b:372506691 TEST=Local build successfully. Change-Id: I7b72284ab173633405d5de9541f0ea7520d09658 Signed-off-by: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85738 Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Eric Lai <ericllai(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> --- M src/mainboard/google/brya/variants/telith/gpio.c M src/mainboard/google/brya/variants/telith/overridetree.cb 2 files changed, 4 insertions(+), 14 deletions(-) Approvals: Eric Lai: Looks good to me, but someone else must approve Rui Zhou: Looks good to me, but someone else must approve Subrata Banik: Looks good to me, approved build bot (Jenkins): Verified Kapil Porwal: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/telith/gpio.c b/src/mainboard/google/brya/variants/telith/gpio.c index 7570d51..0043111 100644 --- a/src/mainboard/google/brya/variants/telith/gpio.c +++ b/src/mainboard/google/brya/variants/telith/gpio.c @@ -42,8 +42,10 @@ /* F6 : CNV_PA_BLANKING ==> NC */ PAD_NC(GPP_F6, NONE), - /* F15 : GSXSRESET# ==> SOC_PEN_DETECT_ODL */ - PAD_CFG_GPI_SCI_HIGH(GPP_F15, NONE, PLTRST, EDGE_BOTH), + /* F15 : GSXSRESET# ==> GPIO */ + PAD_CFG_GPO(GPP_F15, 0, DEEP), + /* F13 : GSXSLOAD ==> GPIO */ + PAD_CFG_GPO(GPP_F13, 0, DEEP), /* F18 : THC1_SPI2_INT# ==> NC */ PAD_NC(GPP_F18, NONE), /* F23 : V1P05_CTRL ==> NC*/ diff --git a/src/mainboard/google/brya/variants/telith/overridetree.cb b/src/mainboard/google/brya/variants/telith/overridetree.cb index b48d8a6..1d6cd45 100644 --- a/src/mainboard/google/brya/variants/telith/overridetree.cb +++ b/src/mainboard/google/brya/variants/telith/overridetree.cb @@ -388,18 +388,6 @@ register "has_power_resource" = "1" device i2c 10 on end end - chip drivers/generic/gpio_keys - register "name" = ""PENH"" - register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPP_F13)" - register "key.wake_gpe" = "GPE0_DW2_15" - register "key.wakeup_route" = "WAKEUP_ROUTE_SCI" - register "key.wakeup_event_action" = "EV_ACT_ANY" - register "key.dev_name" = ""EJCT"" - register "key.linux_code" = "SW_PEN_INSERTED" - register "key.linux_input_type" = "EV_SW" - register "key.label" = ""pen_eject"" - device generic 0 on end - end end device ref i2c2 on chip drivers/intel/mipi_camera -- To view, visit https://review.coreboot.org/c/coreboot/+/85738?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7b72284ab173633405d5de9541f0ea7520d09658 Gerrit-Change-Number: 85738 Gerrit-PatchSet: 4 Gerrit-Owner: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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