coreboot-gerrit December 2024

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[XS] Change in coreboot[main]: Docs/mb/starlabs/labtop_cml.md: Fix footnote syntax
by Felix Singer (Code Review) 01 Dec '24

01 Dec '24

Felix Singer has posted comments on this change by Nicholas Chin. ( https://review.coreboot.org/c/coreboot/+/85412?usp=email ) Change subject: Docs/mb/starlabs/labtop_cml.md: Fix footnote syntax ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: Thanks for reviewing and merging Elyes, but our Gerrit rules say that patches should stay up for review for at least 24 hours after the last big change. So this one was pushed around 1hr and 15min ago. -- To view, visit https://review.coreboot.org/c/coreboot/+/85412?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I07a85b854a181794f82d8e6a739063d66378d2c7 Gerrit-Change-Number: 85412 Gerrit-PatchSet: 2 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 01 Dec 2024 05:48:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: Docs/mb/starlabs/labtop_cml.md: Fix footnote syntax
by Elyes Haouas (Code Review) 01 Dec '24

01 Dec '24

Elyes Haouas has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85412?usp=email ) Change subject: Docs/mb/starlabs/labtop_cml.md: Fix footnote syntax ...................................................................... Docs/mb/starlabs/labtop_cml.md: Fix footnote syntax Fix the syntax [1] for the footnote about the onboard memory configuration so that it renders properly in the generated html. This also fixes a "Unknown target name" error when building with newer versions of Sphinx (tested with 8.1.3). [1] https://myst-parser.readthedocs.io/en/latest/syntax/typography.html#footnot… Change-Id: I07a85b854a181794f82d8e6a739063d66378d2c7 Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85412 Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Elyes Haouas <ehaouas(a)noos.fr> --- M Documentation/mainboard/starlabs/labtop_cml.md 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: Felix Singer: Looks good to me, approved build bot (Jenkins): Verified Elyes Haouas: Looks good to me, approved diff --git a/Documentation/mainboard/starlabs/labtop_cml.md b/Documentation/mainboard/starlabs/labtop_cml.md index d9fdba5..e50db77 100644 --- a/Documentation/mainboard/starlabs/labtop_cml.md +++ b/Documentation/mainboard/starlabs/labtop_cml.md @@ -18,7 +18,7 @@ - HDMI video - USB-C DisplayPort video - Memory - - 16GB on-board *1 + - 16GB on-board [^1] - Networking - AX201 CNVi WiFi / Bluetooth soldered to PCBA - Sound @@ -37,7 +37,7 @@ - USB 3.1 Gen 2 Type-A (left) - USB 3.1 Gen 1 Type-A (right) -[^1] The Comet Lake PCB supports multiple memory variations that are based on hardware configuration resistors see `src/mainboard/starlabs/labtop/variants/cml/romstage.c` +[^1]: The Comet Lake PCB supports multiple memory variations that are based on hardware configuration resistors see `src/mainboard/starlabs/labtop/variants/cml/romstage.c` ## Building coreboot -- To view, visit https://review.coreboot.org/c/coreboot/+/85412?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I07a85b854a181794f82d8e6a739063d66378d2c7 Gerrit-Change-Number: 85412 Gerrit-PatchSet: 2 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: Docs/mb/starlabs/labtop_cml.md: Fix footnote syntax
by Elyes Haouas (Code Review) 01 Dec '24

01 Dec '24

Attention is currently required from: Nicholas Chin. Elyes Haouas has posted comments on this change by Nicholas Chin. ( https://review.coreboot.org/c/coreboot/+/85412?usp=email ) Change subject: Docs/mb/starlabs/labtop_cml.md: Fix footnote syntax ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85412?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I07a85b854a181794f82d8e6a739063d66378d2c7 Gerrit-Change-Number: 85412 Gerrit-PatchSet: 1 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Sun, 01 Dec 2024 05:43:21 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: mb/asus/p8x7x-series: Blink power LED during suspend
by Keith Hui (Code Review) 01 Dec '24

01 Dec '24

Keith Hui has posted comments on this change by Keith Hui. ( https://review.coreboot.org/c/coreboot/+/82557?usp=email ) Change subject: mb/asus/p8x7x-series: Blink power LED during suspend ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/82557?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie30e5ef79a87a3dca6875b0a6e07ae99d0d79e6e Gerrit-Change-Number: 82557 Gerrit-PatchSet: 2 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 01 Dec 2024 04:39:50 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: mb/asus/p8x7x-series: Mark variants using GPIO8 for power LED
by Keith Hui (Code Review) 01 Dec '24

01 Dec '24

Keith Hui has posted comments on this change by Keith Hui. ( https://review.coreboot.org/c/coreboot/+/82556?usp=email ) Change subject: mb/asus/p8x7x-series: Mark variants using GPIO8 for power LED ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/82556?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4d42cd9ac497a4200ab5c90d09eb4dbab8917b30 Gerrit-Change-Number: 82556 Gerrit-PatchSet: 2 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 01 Dec 2024 04:39:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: mb/asus/p8z77-v: Attempt to correctly route PCIe lanes
by Keith Hui (Code Review) 01 Dec '24

01 Dec '24

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85413?usp=email ) Change subject: mb/asus/p8z77-v: Attempt to correctly route PCIe lanes ...................................................................... mb/asus/p8z77-v: Attempt to correctly route PCIe lanes Bill Xie documented with his initial code drop that he was unsuccessful in reproducing all the PCIe configurations possible with vendor firmware. I obtained a boardview to this board and have identified the PCIe lane topology and the required control signals. There are PCIe slot presence signals wired to GPIOs 34,20,7 for PCIEX1_1,PCIEX1_2,PCIEX16_3 respectively, the last one only sense the presence of a PCIe x4 or larger card. PCIe lanes 1-4 are routed by way of three ASM1440 2-way switches controlled by GP54-GP56 on NCT6779D super I/O chip. PCIe lanes 5-8 are fixed. With these details, it is now possible to attempt to reproduce all the vendor PCIe configurations. 1. Change GPIO20 of PCH to GPIO input so coreboot can detect a card inserted into PCIEX1_2. 2. Add an nvram option to force PCIe lane 4 to serve ASM1061 and its two SATA 6Gbps ports. 3. Add code into bootblock to check the PCIe configuration soft straps and whether (1) is true. There is a sanity check to warn of a PCIe configuration that is not valid on this board. 4. Based on (1) and (2), program SIO GPIO5 as appropriate. Changing PCIEX16_3 from x1 to x4 requires changing the soft straps in the SPI flash descriptor which is highly risky. This is based on boardview only, and is untested because I have no hardware. Change-Id: If41197a1f817a48c209d25fc1ae461ec97ccf16c Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/mainboard/asus/p8x7x-series/variants/p8z77-v/cmos.default M src/mainboard/asus/p8x7x-series/variants/p8z77-v/cmos.layout M src/mainboard/asus/p8x7x-series/variants/p8z77-v/early_init.c M src/mainboard/asus/p8x7x-series/variants/p8z77-v/gpio.c 4 files changed, 74 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/85413/1 diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-v/cmos.default b/src/mainboard/asus/p8x7x-series/variants/p8z77-v/cmos.default index 4501aa4..6b2a5bf 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8z77-v/cmos.default +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-v/cmos.default @@ -6,3 +6,4 @@ power_on_after_fail=Disable sata_mode=AHCI gfx_uma_size=64M +always_use_sata6ge=No diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-v/cmos.layout b/src/mainboard/asus/p8x7x-series/variants/p8z77-v/cmos.layout index 0f9de5e..19907df 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8z77-v/cmos.layout +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-v/cmos.layout @@ -24,6 +24,11 @@ # coreboot config options: northbridge 416 5 e 6 gfx_uma_size +# coreboot config options: mainboard +# Keeps PCIe lane 4 with the ASM1061 chip serving these two +# SATA6G ports. PCIEX1_2 slot will not work. +426 1 e 7 always_use_sata6ge + # coreboot config options: check sums 984 16 h 0 check_sum @@ -80,6 +85,10 @@ 6 15 512M 6 16 1024M +# Generic yes/no enum +7 0 No +7 1 Yes + # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-v/early_init.c b/src/mainboard/asus/p8x7x-series/variants/p8z77-v/early_init.c index bf0ba67..8cd3dbd 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8z77-v/early_init.c +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-v/early_init.c @@ -4,10 +4,72 @@ #include <device/pnp_ops.h> #include <superio/nuvoton/common/nuvoton.h> #include <superio/nuvoton/nct6779d/nct6779d.h> +#include <southbridge/intel/common/rcba.h> +#include <southbridge/intel/common/gpio.h> +#include <console/console.h> +#include <option.h> #define GLOBAL_DEV PNP_DEV(0x2e, 0) #define SERIAL_DEV PNP_DEV(0x2e, NCT6779D_SP1) #define ACPI_DEV PNP_DEV(0x2e, NCT6779D_ACPI) +#define GPIO_DEV PNP_DEV(0x2e, NCT6779D_GPIO12345678_V) + +void bootblock_mainboard_init(void) +{ + nuvoton_pnp_enter_conf_state(GPIO_DEV); + + /* Enable SIO GPIO5. GP54-GP56 control three ASM1440 PCIe switches that route + * PCH PCIe lanes 2-4 to various places. + * + * [7] Unused, set as input + * [6:5] QSWU7+QSWU6 (PCH PCIe lane 4) + * x0 = ASM1061 SATA + * 01 = PCIEX1_2 + * 11 = PCIEX16_3 lane 4 + * [4] QSWU5 (PCH PCIe lanes 3 & 2) + * 0 = lane 3 disconnected, lane 2 to PCIEX1_1 + * 1 = PCIEX16_3 lanes 3 & 2 + * [3] VCCSA_VID input from CPU + * [2] VCCIO_SEL input from CPU + * [1:0] Connect to BIOS flashback chip, direction unknown, set as input + */ + + pnp_set_logical_device(GPIO_DEV); + pnp_write_config(GPIO_DEV, 0x30, 0x20); + pnp_write_config(GPIO_DEV, 0xf4, 0x8f); + + u8 gpio5 = 0; + unsigned int force_asm1061 = get_uint_option("always_use_sata6ge", 0); + + /* PCHSTRP9[PCIEPCS1] soft strap tells us how PCIe lanes 1-4 are configured. */ + u32 pciepcs1 = RCBA32(0x400) & 0x3; + + /* TODO: If we have a way to change PCHSTRP9[PCIEPCS1], sense card presence on + * PCIEX16_3 using PCH GPIO7 and PCIEX1_1 using PCH GPIO34 and decide how to + * reconfigure the lanes. */ + + switch (pciepcs1) { + case 2: + printk(BIOS_ERR, "2 x2 PCH PCIe lane configuration is invalid!\n"); + __fallthrough; + /* Send everything to PCIEX16_3; it will at least allow + * whatever is there to run as x2. */ + case 3: /* 1 x4 */ + gpio5 = 0x70; + break; + default: /* 4 x1 or ... */ + gpio5 = (pciepcs1 == 1) ? 0x10 : 0; /* ... 1 x2, 2 x1 */ + + /* If a card is in PCIEX1_2 and user is not forcing the extra SATA ports, + * give lane 4 to the slot. + */ + if (!force_asm1061 && !get_gpio(20)) + gpio5 |= 0x20; + } + + pnp_write_config(GPIO_DEV, 0xf5, gpio5); + nuvoton_pnp_exit_conf_state(GPIO_DEV); +} void bootblock_mainboard_early_init(void) { diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-v/gpio.c b/src/mainboard/asus/p8x7x-series/variants/p8z77-v/gpio.c index 5d5e4e7..a313092 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8z77-v/gpio.c +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-v/gpio.c @@ -23,7 +23,7 @@ .gpio17 = GPIO_MODE_GPIO, .gpio18 = GPIO_MODE_NATIVE, .gpio19 = GPIO_MODE_NATIVE, - .gpio20 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_GPIO, .gpio21 = GPIO_MODE_NATIVE, .gpio22 = GPIO_MODE_GPIO, .gpio23 = GPIO_MODE_NATIVE, @@ -47,6 +47,7 @@ .gpio15 = GPIO_DIR_OUTPUT, .gpio16 = GPIO_DIR_INPUT, .gpio17 = GPIO_DIR_INPUT, + .gpio20 = GPIO_DIR_INPUT, .gpio22 = GPIO_DIR_INPUT, .gpio24 = GPIO_DIR_OUTPUT, .gpio27 = GPIO_DIR_INPUT, -- To view, visit https://review.coreboot.org/c/coreboot/+/85413?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If41197a1f817a48c209d25fc1ae461ec97ccf16c Gerrit-Change-Number: 85413 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com>

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[XS] Change in coreboot[main]: Docs/mb/starlabs/labtop_cml.md: Fix footnote syntax
by Felix Singer (Code Review) 01 Dec '24

01 Dec '24

Attention is currently required from: Nicholas Chin. Felix Singer has posted comments on this change by Nicholas Chin. ( https://review.coreboot.org/c/coreboot/+/85412?usp=email ) Change subject: Docs/mb/starlabs/labtop_cml.md: Fix footnote syntax ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85412?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I07a85b854a181794f82d8e6a739063d66378d2c7 Gerrit-Change-Number: 85412 Gerrit-PatchSet: 1 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Sun, 01 Dec 2024 04:37:42 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: Docs/mb/starlabs/labtop_cml.md: Fix footnote syntax
by Nicholas Chin (Code Review) 01 Dec '24

01 Dec '24

Nicholas Chin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85412?usp=email ) Change subject: Docs/mb/starlabs/labtop_cml.md: Fix footnote syntax ...................................................................... Docs/mb/starlabs/labtop_cml.md: Fix footnote syntax Fix the syntax [1] for the footnote about the onboard memory configuration so that it renders properly in the generated html. This also fixes a "Unknown target name" error when building with newer versions of Sphinx (tested with 8.1.3). [1] https://myst-parser.readthedocs.io/en/latest/syntax/typography.html#footnot… Change-Id: I07a85b854a181794f82d8e6a739063d66378d2c7 Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com> --- M Documentation/mainboard/starlabs/labtop_cml.md 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/85412/1 diff --git a/Documentation/mainboard/starlabs/labtop_cml.md b/Documentation/mainboard/starlabs/labtop_cml.md index d9fdba5..e50db77 100644 --- a/Documentation/mainboard/starlabs/labtop_cml.md +++ b/Documentation/mainboard/starlabs/labtop_cml.md @@ -18,7 +18,7 @@ - HDMI video - USB-C DisplayPort video - Memory - - 16GB on-board *1 + - 16GB on-board [^1] - Networking - AX201 CNVi WiFi / Bluetooth soldered to PCBA - Sound @@ -37,7 +37,7 @@ - USB 3.1 Gen 2 Type-A (left) - USB 3.1 Gen 1 Type-A (right) -[^1] The Comet Lake PCB supports multiple memory variations that are based on hardware configuration resistors see `src/mainboard/starlabs/labtop/variants/cml/romstage.c` +[^1]: The Comet Lake PCB supports multiple memory variations that are based on hardware configuration resistors see `src/mainboard/starlabs/labtop/variants/cml/romstage.c` ## Building coreboot -- To view, visit https://review.coreboot.org/c/coreboot/+/85412?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I07a85b854a181794f82d8e6a739063d66378d2c7 Gerrit-Change-Number: 85412 Gerrit-PatchSet: 1 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com>

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coreboot-gerrit December 2024