coreboot-gerrit December 2024

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[M] Change in coreboot[main]: Documentation: Add information about the deguard utility
by Felix Singer (Code Review) 02 Dec '24

02 Dec '24

Attention is currently required from: Elyes Haouas, Máté Kukri, Nicholas Chin. Felix Singer has posted comments on this change by Máté Kukri. ( https://review.coreboot.org/c/coreboot/+/84825?usp=email ) Change subject: Documentation: Add information about the deguard utility ...................................................................... Patch Set 3: (1 comment) File Documentation/soc/intel/index.md: https://review.coreboot.org/c/coreboot/+/84825/comment/7ccfbc35_bead2746?us… : PS3, Line 19: Skylake/Kaby Lake BootGuard bypass <deguard.md> Not sure if soc/intel is the appropriate section for that. @nic.c3.14@gmail.com Do you have any better idea? -- To view, visit https://review.coreboot.org/c/coreboot/+/84825?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idba0f461d31db31cbc9c35ee3da70c116d5493ce Gerrit-Change-Number: 84825 Gerrit-PatchSet: 3 Gerrit-Owner: Máté Kukri <km(a)mkukri.xyz> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Máté Kukri <km(a)mkukri.xyz> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Mon, 02 Dec 2024 00:07:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: doc/release/24.05: Add toolchain updates
by Felix Singer (Code Review) 01 Dec '24

01 Dec '24

Felix Singer has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/81998?usp=email ) Change subject: doc/release/24.05: Add toolchain updates ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/81998?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: abandon Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6b80513cc547e9a9f9e2dce28262536b1e079ffe Gerrit-Change-Number: 81998 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>

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[M] Change in coreboot[main]: Docs: Convert bare URLs into hyperlinks
by Felix Singer (Code Review) 01 Dec '24

01 Dec '24

Attention is currently required from: Angel Pons, Jason Glenesk, Martin L Roth, Nicholas Chin. Felix Singer has posted comments on this change by Nicholas Chin. ( https://review.coreboot.org/c/coreboot/+/85433?usp=email ) Change subject: Docs: Convert bare URLs into hyperlinks ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85433?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I234d395cddd58f3d3dfb4b4ddccb6efc70d4dd9e Gerrit-Change-Number: 85433 Gerrit-PatchSet: 1 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Sun, 01 Dec 2024 22:16:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: mb/purism/librem_l1um_v2/ramstage.c: Use DEV_PTR macro
by Felix Singer (Code Review) 01 Dec '24

01 Dec '24

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85093?usp=email ) Change subject: mb/purism/librem_l1um_v2/ramstage.c: Use DEV_PTR macro ...................................................................... mb/purism/librem_l1um_v2/ramstage.c: Use DEV_PTR macro Use the DEV_PTR macro to resolve devicetree aliases instead of using the autogenerated reference names from sconfig directly. TEST=Timeless build did not change Change-Id: I4ff06bb3a8256d5fe215cab659f33ec404264e21 Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85093 Reviewed-by: Jonathon Hall <jonathon.hall(a)puri.sm> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> --- M src/mainboard/purism/librem_l1um_v2/ramstage.c 1 file changed, 5 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved Jonathon Hall: Looks good to me, approved diff --git a/src/mainboard/purism/librem_l1um_v2/ramstage.c b/src/mainboard/purism/librem_l1um_v2/ramstage.c index 87b7822..39c078c 100644 --- a/src/mainboard/purism/librem_l1um_v2/ramstage.c +++ b/src/mainboard/purism/librem_l1um_v2/ramstage.c @@ -26,13 +26,13 @@ * Control Register), but we have to use one of the LDNs as the device * because the chip ops are only assigned to the LDNs. */ - pnp_enter_conf_mode(_dev_nvt_superio_gpio1_ptr); + pnp_enter_conf_mode(DEV_PTR(nvt_superio_gpio1)); printk(BIOS_DEBUG, "GCR 0x2f was: %02X\n", - pnp_read_config(_dev_nvt_superio_gpio1_ptr, 0x2f)); - pnp_write_config(_dev_nvt_superio_gpio1_ptr, 0x2f, 0x00); + pnp_read_config(DEV_PTR(nvt_superio_gpio1), 0x2f)); + pnp_write_config(DEV_PTR(nvt_superio_gpio1), 0x2f, 0x00); printk(BIOS_DEBUG, "GCR 0x2f is now: %02X\n", - pnp_read_config(_dev_nvt_superio_gpio1_ptr, 0x2f)); - pnp_exit_conf_mode(_dev_nvt_superio_gpio1_ptr); + pnp_read_config(DEV_PTR(nvt_superio_gpio1), 0x2f)); + pnp_exit_conf_mode(DEV_PTR(nvt_superio_gpio1)); } struct chip_operations mainboard_ops = { -- To view, visit https://review.coreboot.org/c/coreboot/+/85093?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4ff06bb3a8256d5fe215cab659f33ec404264e21 Gerrit-Change-Number: 85093 Gerrit-PatchSet: 3 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: mb/purism/librem_l1um_v2/ramstage.c: Use DEV_PTR macro
by Felix Singer (Code Review) 01 Dec '24

01 Dec '24

Attention is currently required from: Nicholas Chin. Felix Singer has posted comments on this change by Nicholas Chin. ( https://review.coreboot.org/c/coreboot/+/85093?usp=email ) Change subject: mb/purism/librem_l1um_v2/ramstage.c: Use DEV_PTR macro ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85093?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4ff06bb3a8256d5fe215cab659f33ec404264e21 Gerrit-Change-Number: 85093 Gerrit-PatchSet: 2 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Sun, 01 Dec 2024 22:16:05 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: Docs: Convert bare URLs into hyperlinks
by Nicholas Chin (Code Review) 01 Dec '24

01 Dec '24

Nicholas Chin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85433?usp=email ) Change subject: Docs: Convert bare URLs into hyperlinks ...................................................................... Docs: Convert bare URLs into hyperlinks Format bare URLs as links so that they are rendered as hyperlinks instead of plain text. Change-Id: I234d395cddd58f3d3dfb4b4ddccb6efc70d4dd9e Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com> --- M Documentation/getting_started/kconfig.md M Documentation/infrastructure/services.md M Documentation/mainboard/emulation/qemu-sbsa.md M Documentation/mainboard/ocp/deltalake.md M Documentation/mainboard/starlabs/byte_adl.md M Documentation/mainboard/starlabs/labtop_cml.md M Documentation/mainboard/starlabs/labtop_kbl.md M Documentation/mainboard/starlabs/lite_adl.md M Documentation/mainboard/starlabs/lite_glk.md M Documentation/mainboard/starlabs/lite_glkr.md M Documentation/mainboard/starlabs/starbook_adl.md M Documentation/mainboard/starlabs/starbook_tgl.md M Documentation/mainboard/starlabs/starfighter_rpl.md M Documentation/mainboard/system76/gaze15.md M Documentation/mainboard/system76/lemp9.md M Documentation/mainboard/system76/oryp5.md M Documentation/mainboard/system76/oryp6.md M Documentation/releases/coreboot-24.02-relnotes.md M Documentation/releases/coreboot-24.05-relnotes.md M Documentation/releases/coreboot-24.11-relnotes.md M Documentation/releases/coreboot-4.1-relnotes.md M Documentation/releases/coreboot-4.10-relnotes.md M Documentation/releases/coreboot-4.14-relnotes.md M Documentation/releases/coreboot-4.16-relnotes.md M Documentation/releases/coreboot-4.17-relnotes.md M Documentation/releases/coreboot-4.18-relnotes.md M Documentation/releases/coreboot-4.19-relnotes.md M Documentation/releases/coreboot-4.2-relnotes.md M Documentation/releases/coreboot-4.20.1-relnotes.md M Documentation/releases/coreboot-4.21-relnotes.md M Documentation/releases/coreboot-4.22-relnotes.md M Documentation/releases/coreboot-4.3-relnotes.md M Documentation/releases/coreboot-4.4-relnotes.md M Documentation/releases/coreboot-4.5-relnotes.md M Documentation/releases/coreboot-4.6-relnotes.md M Documentation/releases/coreboot-4.8.1-relnotes.md M Documentation/soc/intel/xeon_sp/community_preview_guide.md M Documentation/technotes/2015-11-rebuilding-coreboot-image-generation.md M Documentation/technotes/console.md 39 files changed, 91 insertions(+), 90 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/85433/1 diff --git a/Documentation/getting_started/kconfig.md b/Documentation/getting_started/kconfig.md index 8965458..4aa00a2 100644 --- a/Documentation/getting_started/kconfig.md +++ b/Documentation/getting_started/kconfig.md @@ -1172,13 +1172,13 @@ ### ultraedit: -https://github.com/martinlroth/wordfiles/blob/master/kconfig.uew +<https://github.com/martinlroth/wordfiles/blob/master/kconfig.uew> ### atom: -https://github.com/martinlroth/language-kconfig +<https://github.com/martinlroth/language-kconfig> ## Syntax Checking: @@ -1217,7 +1217,7 @@ ## License: This work is licensed under the Creative Commons Attribution 4.0 International License. To view a copy of this license, visit -https://creativecommons.org/licenses/by/4.0/ or send a letter to Creative +<https://creativecommons.org/licenses/by/4.0/> or send a letter to Creative Commons, PO Box 1866, Mountain View, CA 94042, USA. Code examples snippets are licensed under GPLv2, and are used here under fair diff --git a/Documentation/infrastructure/services.md b/Documentation/infrastructure/services.md index 6d7ddd9..6b2b1c7 100644 --- a/Documentation/infrastructure/services.md +++ b/Documentation/infrastructure/services.md @@ -41,7 +41,7 @@ ### Gerrit user avatar To setup an avatar to show in Gerrit, clone the avatars repository at -https://review.coreboot.org/gerrit-avatars.git and add a file named +<https://review.coreboot.org/gerrit-avatars.git> and add a file named $your-user-ID.jpg (the user ID is a number shown on the [settings screen](https://review.coreboot.org/settings)). The image must be provided in JPEG format, must be square and have at most 50000 bytes. diff --git a/Documentation/mainboard/emulation/qemu-sbsa.md b/Documentation/mainboard/emulation/qemu-sbsa.md index abbd189..e7eee24 100644 --- a/Documentation/mainboard/emulation/qemu-sbsa.md +++ b/Documentation/mainboard/emulation/qemu-sbsa.md @@ -39,4 +39,4 @@ arm and 9elements worked together in order to create a LBBR compliant bootflow consisting of ```TF-A```, ```coreboot```, ```leanefi``` and ```LinuxBoot```. A proof of concept -can be found here https://gitlab.arm.com/systemready/firmware-build/linuxboot/lbbr-coreboot-p… +can be found here <https://gitlab.arm.com/systemready/firmware-build/linuxboot/lbbr-coreboot-p…> diff --git a/Documentation/mainboard/ocp/deltalake.md b/Documentation/mainboard/ocp/deltalake.md index 404052c..05df4f2 100644 --- a/Documentation/mainboard/ocp/deltalake.md +++ b/Documentation/mainboard/ocp/deltalake.md @@ -32,7 +32,7 @@ ## How to build OSF code base is publicly available at -https://github.com/opencomputeproject/OpenSystemFirmware +<https://github.com/opencomputeproject/OpenSystemFirmware> Run following commands to build Delta Lake OSF image from scratch: git clone https://github.com/opencomputeproject/OpenSystemFirmware.git @@ -44,10 +44,11 @@ Besides coreboot, the Delta Lake OSF solution includes following components: - FSP blob: The blobs (Intel Cooper Lake Scalable Processor Firmware Support Package) - is downloaded from https://github.com/intel/FSP/tree/master/CedarIslandFspBinPkg. -- Microcode: downloaded from github.com/intel/Intel-Linux-Processor-Microcode-Data-Files. + is downloaded from <https://github.com/intel/FSP/tree/master/CedarIslandFspBinPkg>. +- Microcode: downloaded from + <https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files>. - ME ignition binary: downloaded from - https://github.com/tianocore/edk2-non-osi/tree/master/Silicon/Intel/PurleyS… + <https://github.com/tianocore/edk2-non-osi/tree/master/Silicon/Intel/PurleyS…> - ACM binaries: only required for CBnT enablement. Available under NDA with Intel. - Payload: LinuxBoot is necessary when LinuxBoot is used as the coreboot payload. U-root as initramfs, is used in the joint development. It is built diff --git a/Documentation/mainboard/starlabs/byte_adl.md b/Documentation/mainboard/starlabs/byte_adl.md index 11bed26..7805bb5 100644 --- a/Documentation/mainboard/starlabs/byte_adl.md +++ b/Documentation/mainboard/starlabs/byte_adl.md @@ -2,7 +2,7 @@ ## Specs -- CPU (full processor specs available at https://ark.intel.com) +- CPU (full processor specs available at <https://ark.intel.com>) - Intel N200 (Alder Lake) - EC - ITE IT5570E diff --git a/Documentation/mainboard/starlabs/labtop_cml.md b/Documentation/mainboard/starlabs/labtop_cml.md index e50db77..e8d846b 100644 --- a/Documentation/mainboard/starlabs/labtop_cml.md +++ b/Documentation/mainboard/starlabs/labtop_cml.md @@ -2,7 +2,7 @@ ## Specs -- CPU (full processor specs available at https://ark.intel.com) +- CPU (full processor specs available at <https://ark.intel.com>) - Intel i7-10710U (Comet Lake) - Intel i3-10110U (Comet Lake) - EC diff --git a/Documentation/mainboard/starlabs/labtop_kbl.md b/Documentation/mainboard/starlabs/labtop_kbl.md index eb68938..2b3b2cc 100644 --- a/Documentation/mainboard/starlabs/labtop_kbl.md +++ b/Documentation/mainboard/starlabs/labtop_kbl.md @@ -2,7 +2,7 @@ ## Specs -- CPU (full processor specs available at https://ark.intel.com) +- CPU (full processor specs available at <https://ark.intel.com>) - Intel i7-8550u (Kaby Lake Refresh) - EC - ITE IT8987E diff --git a/Documentation/mainboard/starlabs/lite_adl.md b/Documentation/mainboard/starlabs/lite_adl.md index 821c755..b6e7cb3 100644 --- a/Documentation/mainboard/starlabs/lite_adl.md +++ b/Documentation/mainboard/starlabs/lite_adl.md @@ -2,7 +2,7 @@ ## Specs -- CPU (full processor specs available at https://ark.intel.com) +- CPU (full processor specs available at <https://ark.intel.com>) - Intel N200 (Alder Lake) - EC - ITE IT5570E diff --git a/Documentation/mainboard/starlabs/lite_glk.md b/Documentation/mainboard/starlabs/lite_glk.md index d31b680..79aad0c 100644 --- a/Documentation/mainboard/starlabs/lite_glk.md +++ b/Documentation/mainboard/starlabs/lite_glk.md @@ -1,7 +1,7 @@ # StarLite Mk III ## Specs -- CPU (full processor specs available at https://ark.intel.com) +- CPU (full processor specs available at <https://ark.intel.com>) - Intel N5000 (Gemini Lake) - EC - ITE IT8987E diff --git a/Documentation/mainboard/starlabs/lite_glkr.md b/Documentation/mainboard/starlabs/lite_glkr.md index bf36281..e1ffe21 100644 --- a/Documentation/mainboard/starlabs/lite_glkr.md +++ b/Documentation/mainboard/starlabs/lite_glkr.md @@ -1,7 +1,7 @@ # StarLite Mk III ## Specs -- CPU (full processor specs available at https://ark.intel.com) +- CPU (full processor specs available at <https://ark.intel.com>) - Intel N5030 (Gemini Lake Refresh) - EC - Nuvoton NPCE985P/G diff --git a/Documentation/mainboard/starlabs/starbook_adl.md b/Documentation/mainboard/starlabs/starbook_adl.md index cce9cbe..3840bc9 100644 --- a/Documentation/mainboard/starlabs/starbook_adl.md +++ b/Documentation/mainboard/starlabs/starbook_adl.md @@ -2,7 +2,7 @@ ## Specs -- CPU (full processor specs available at https://ark.intel.com) +- CPU (full processor specs available at <https://ark.intel.com>) - Intel i7-1260P (Alder Lake) - Intel i3-1220P (Alder Lake) - Intel i3-1315U (Raptor Lake) diff --git a/Documentation/mainboard/starlabs/starbook_tgl.md b/Documentation/mainboard/starlabs/starbook_tgl.md index 30810dd..db447cf 100644 --- a/Documentation/mainboard/starlabs/starbook_tgl.md +++ b/Documentation/mainboard/starlabs/starbook_tgl.md @@ -2,7 +2,7 @@ ## Specs -- CPU (full processor specs available at https://ark.intel.com) +- CPU (full processor specs available at <https://ark.intel.com>) - Intel i7-1165G7 (Tiger Lake) - Intel i3-1110G4 (Tiger Lake) - EC diff --git a/Documentation/mainboard/starlabs/starfighter_rpl.md b/Documentation/mainboard/starlabs/starfighter_rpl.md index d386fb3..2468fae 100644 --- a/Documentation/mainboard/starlabs/starfighter_rpl.md +++ b/Documentation/mainboard/starlabs/starfighter_rpl.md @@ -2,7 +2,7 @@ ## Specs -- CPU (full processor specs available at https://ark.intel.com) +- CPU (full processor specs available at <https://ark.intel.com>) - Intel i3-1315U (Raptor Lake) - Intel i7-13700H (Raptor Lake) - Intel i9-13900H (Raptor Lake) diff --git a/Documentation/mainboard/system76/gaze15.md b/Documentation/mainboard/system76/gaze15.md index 45e4e26..01af254 100644 --- a/Documentation/mainboard/system76/gaze15.md +++ b/Documentation/mainboard/system76/gaze15.md @@ -5,7 +5,7 @@ - CPU - Intel Core i7 10750H - EC - - ITE5570E running https://github.com/system76/ec + - ITE5570E running <https://github.com/system76/ec> - Graphics - Intel UHD Graphics - NVIDIA GeForce GTX 1650/1650 Ti/1660 Ti diff --git a/Documentation/mainboard/system76/lemp9.md b/Documentation/mainboard/system76/lemp9.md index c216188..548cfa5 100644 --- a/Documentation/mainboard/system76/lemp9.md +++ b/Documentation/mainboard/system76/lemp9.md @@ -6,7 +6,7 @@ - Intel i7-10510U - Intel i5-10210U - EC - - ITE IT5570E running https://github.com/system76/ec + - ITE IT5570E running <https://github.com/system76/ec> - Backlit Keyboard, with standard PS/2 keycodes and SCI hotkeys - Battery - Charger, using AC adapter or USB-C PD diff --git a/Documentation/mainboard/system76/oryp5.md b/Documentation/mainboard/system76/oryp5.md index bfde6c0..902e7ce 100644 --- a/Documentation/mainboard/system76/oryp5.md +++ b/Documentation/mainboard/system76/oryp5.md @@ -6,7 +6,7 @@ - Intel Core i7-8750H - Intel Core i7-9750H - EC - - ITE8587E running https://github.com/system76/ec + - ITE8587E running <https://github.com/system76/ec> - Graphics - Intel UHD Graphics 630 - NVIDIA GeForce RTX 2080/2070/2060 diff --git a/Documentation/mainboard/system76/oryp6.md b/Documentation/mainboard/system76/oryp6.md index 6a52c54..0050ead 100644 --- a/Documentation/mainboard/system76/oryp6.md +++ b/Documentation/mainboard/system76/oryp6.md @@ -7,7 +7,7 @@ - Chipset - Intel HM470 - EC - - ITE IT5570E running https://github.com/system76/ec + - ITE IT5570E running <https://github.com/system76/ec> - GPU - NVIDIA GeForce RTX 2080 Super (Max-Q) - or NVIDIA GeForce RTX 2070 (Max-Q) diff --git a/Documentation/releases/coreboot-24.02-relnotes.md b/Documentation/releases/coreboot-24.02-relnotes.md index 4b98d57..90bd138 100644 --- a/Documentation/releases/coreboot-24.02-relnotes.md +++ b/Documentation/releases/coreboot-24.02-relnotes.md @@ -113,7 +113,7 @@ from 128060 bytes decompressed (64121 bytes after LZMA) to 172304 bytes decompressed (82734 bytes after LZMA). -[0] https://github.com/google/wuffs +[0] <https://github.com/google/wuffs> @@ -197,7 +197,7 @@ the version of verstage used in coreboot 24.02. -Issues from the coreboot bugtracker: https://ticket.coreboot.org/ +Issues from the coreboot bugtracker: <https://ticket.coreboot.org/> ### coreboot-wide or architecture-wide issues @@ -282,9 +282,9 @@ coreboot Links and Contact Information -------------------------------------- -* Main Web site: https://www.coreboot.org -* Downloads: https://coreboot.org/downloads.html -* Source control: https://review.coreboot.org -* Documentation: https://doc.coreboot.org -* Issue tracker: https://ticket.coreboot.org/projects/coreboot -* Donations: https://coreboot.org/donate.html +* Main Web site: <https://www.coreboot.org> +* Downloads: <https://coreboot.org/downloads.html> +* Source control: <https://review.coreboot.org> +* Documentation: <https://doc.coreboot.org> +* Issue tracker: <https://ticket.coreboot.org/projects/coreboot> +* Donations: <https://coreboot.org/donate.html> diff --git a/Documentation/releases/coreboot-24.05-relnotes.md b/Documentation/releases/coreboot-24.05-relnotes.md index 86910b8..6d34e5b 100644 --- a/Documentation/releases/coreboot-24.05-relnotes.md +++ b/Documentation/releases/coreboot-24.05-relnotes.md @@ -70,7 +70,7 @@ * Numerous fixes for clang support * Ongoing code cleanup * Docs: Replace Recommonmark with MyST Parser. For changes, see the commit - message in https://review.coreboot.org/73158 + message in <https://review.coreboot.org/73158> @@ -257,9 +257,9 @@ coreboot Links and Contact Information -------------------------------------- -* Main Website: https://www.coreboot.org -* Downloads: https://coreboot.org/downloads.html -* Source control: https://review.coreboot.org -* Documentation: https://doc.coreboot.org -* Issue tracker: https://ticket.coreboot.org/projects/coreboot -* Donations: https://coreboot.org/donate.html +* Main Website: <https://www.coreboot.org> +* Downloads: <https://coreboot.org/downloads.html> +* Source control: <https://review.coreboot.org> +* Documentation: <https://doc.coreboot.org> +* Issue tracker: <https://ticket.coreboot.org/projects/coreboot> +* Donations: <https://coreboot.org/donate.html> diff --git a/Documentation/releases/coreboot-24.11-relnotes.md b/Documentation/releases/coreboot-24.11-relnotes.md index 6416b87..9ff9036 100644 --- a/Documentation/releases/coreboot-24.11-relnotes.md +++ b/Documentation/releases/coreboot-24.11-relnotes.md @@ -83,7 +83,7 @@ Significant Known and Open Issues --------------------------------- -Issues from the coreboot bugtracker: https://ticket.coreboot.org/ +Issues from the coreboot bugtracker: <https://ticket.coreboot.org/> * To be filled in immediately before the release by the release team @@ -91,9 +91,9 @@ coreboot Links and Contact Information -------------------------------------- -* Main Web site: https://www.coreboot.org -* Downloads: https://coreboot.org/downloads.html -* Source control: https://review.coreboot.org -* Documentation: https://doc.coreboot.org -* Issue tracker: https://ticket.coreboot.org/projects/coreboot -* Donations: https://coreboot.org/donate.html +* Main Web site: <https://www.coreboot.org> +* Downloads: <https://coreboot.org/downloads.html> +* Source control: <https://review.coreboot.org> +* Documentation: <https://doc.coreboot.org> +* Issue tracker: <https://ticket.coreboot.org/projects/coreboot> +* Donations: <https://coreboot.org/donate.html> diff --git a/Documentation/releases/coreboot-4.1-relnotes.md b/Documentation/releases/coreboot-4.1-relnotes.md index d269688..dcc1f8d 100644 --- a/Documentation/releases/coreboot-4.1-relnotes.md +++ b/Documentation/releases/coreboot-4.1-relnotes.md @@ -31,7 +31,7 @@ overwhelming. With the release of coreboot 4.1, you get an announcement (this email), -a git tag (4.1), and tar archives at http://www.coreboot.org/releases/, +a git tag (4.1), and tar archives at <http://www.coreboot.org/releases/>, for the coreboot sources and the redistributable blobs. Starting with coreboot 4.1, we will maintain a high level changelog and diff --git a/Documentation/releases/coreboot-4.10-relnotes.md b/Documentation/releases/coreboot-4.10-relnotes.md index 0f935c2..e4c9b26 100644 --- a/Documentation/releases/coreboot-4.10-relnotes.md +++ b/Documentation/releases/coreboot-4.10-relnotes.md @@ -59,7 +59,7 @@ If you want to use Google Cyan with the release (or if you're tracking the master branch), please keep an eye on -https://review.coreboot.org/c/coreboot/+/34304 where a solution for this +<https://review.coreboot.org/c/coreboot/+/34304> where a solution for this issue is sought. Deprecations diff --git a/Documentation/releases/coreboot-4.14-relnotes.md b/Documentation/releases/coreboot-4.14-relnotes.md index 4f2b00e..8a78b40 100644 --- a/Documentation/releases/coreboot-4.14-relnotes.md +++ b/Documentation/releases/coreboot-4.14-relnotes.md @@ -147,7 +147,7 @@ With this release, the codebase for multiple generations of Xeon-SP were unified and optimized: -* SKX-SP SoC code is used in OCP TiogaPass mainboard [3]. Support for +* SKX-SP SoC code is used in [OCP TiogaPass mainboard][3]. Support for this board is in Proof Of Concept Status. * CPX-SP SoC code is used in OCP DeltaLake mainboard. Support for this board is in DVT (Design Validation Test) exit equivalent status. @@ -155,7 +155,7 @@ features gaps are described in [4]. -[1] https://www.intel.com/content/www/us/en/products/details/processors/xeon/sc… -[2] https://www.intel.com/content/www/us/en/products/docs/processors/xeon/3rd-g… -[3] ../mainboard/ocp/tiogapass.md -[4] ../mainboard/ocp/deltalake.md +[1]: <https://www.intel.com/content/www/us/en/products/details/processors/xeon/sc…> +[2]: <https://www.intel.com/content/www/us/en/products/docs/processors/xeon/3rd-g…> +[3]: <../mainboard/ocp/tiogapass.md> +[4]: <../mainboard/ocp/deltalake.md> diff --git a/Documentation/releases/coreboot-4.16-relnotes.md b/Documentation/releases/coreboot-4.16-relnotes.md index bf60d53..c9d6705 100644 --- a/Documentation/releases/coreboot-4.16-relnotes.md +++ b/Documentation/releases/coreboot-4.16-relnotes.md @@ -115,7 +115,7 @@ the BSP CPU. - Support SMM in the legacy ASEG (0xa0000 - 0xb0000) region. A POC showed that it's not that hard to do with PARALLEL_MP - https://review.coreboot.org/c/coreboot/+/58700 + <https://review.coreboot.org/c/coreboot/+/58700> No platforms in the tree have any hardware limitations that would block migrating to PARALLEL_MP / a simple !CONFIG_SMP codebase. diff --git a/Documentation/releases/coreboot-4.17-relnotes.md b/Documentation/releases/coreboot-4.17-relnotes.md index eb136f4..dbfff40 100644 --- a/Documentation/releases/coreboot-4.17-relnotes.md +++ b/Documentation/releases/coreboot-4.17-relnotes.md @@ -239,7 +239,7 @@ profiler-like output, and thus can be feed to flame graph generation tools. -Generating flame graph using https://github.com/brendangregg/FlameGraph: +Generating flame graph using <https://github.com/brendangregg/FlameGraph>: ``` cbmem -S > trace.txt FlameGraph/flamegraph.pl --flamechart trace.txt > output.svg diff --git a/Documentation/releases/coreboot-4.18-relnotes.md b/Documentation/releases/coreboot-4.18-relnotes.md index a779192..73fc445 100644 --- a/Documentation/releases/coreboot-4.18-relnotes.md +++ b/Documentation/releases/coreboot-4.18-relnotes.md @@ -78,7 +78,7 @@ version) of the firmware. Further reference: -https://web.archive.org/web/20220310104905/https://blogs.gnome.org/hughsie/2022/03/10/firmware-software-bill-of-materials/ +<https://web.archive.org/web/20220310104905/https://blogs.gnome.org/hughsie/…> - Add Makefile.inc to generate and build coswid tags - Add templates for most payloads, coreboot, intel-microcode, diff --git a/Documentation/releases/coreboot-4.19-relnotes.md b/Documentation/releases/coreboot-4.19-relnotes.md index 09e99f6..b69abe9 100644 --- a/Documentation/releases/coreboot-4.19-relnotes.md +++ b/Documentation/releases/coreboot-4.19-relnotes.md @@ -220,7 +220,7 @@ Significant Known and Open Issues --------------------------------- -Issues from the coreboot bugtracker: https://ticket.coreboot.org/ +Issues from the coreboot bugtracker: <https://ticket.coreboot.org/> ```{eval-rst} +-----+-----------------------------------------------------------------+ | # | Subject | diff --git a/Documentation/releases/coreboot-4.2-relnotes.md b/Documentation/releases/coreboot-4.2-relnotes.md index 08a0175..dfde115 100644 --- a/Documentation/releases/coreboot-4.2-relnotes.md +++ b/Documentation/releases/coreboot-4.2-relnotes.md @@ -12,7 +12,7 @@ helped shape this release. As with 4.1, the release tarballs are available at -http://www.coreboot.org/releases/. There's also a 4.2 tag and branch in +<http://www.coreboot.org/releases/>. There's also a 4.2 tag and branch in the git repository. This marks the first release that features a changelog comparing it to diff --git a/Documentation/releases/coreboot-4.20.1-relnotes.md b/Documentation/releases/coreboot-4.20.1-relnotes.md index 6f41100..d0c537d 100644 --- a/Documentation/releases/coreboot-4.20.1-relnotes.md +++ b/Documentation/releases/coreboot-4.20.1-relnotes.md @@ -62,11 +62,11 @@ transition per port. More details can be found in -https://web.archive.org/web/20230116084819/https://learn.microsoft.com/en-us/windows-hardware/drivers/bringup/usb-device-specific-method---dsm- +<https://web.archive.org/web/20230116084819/https://learn.microsoft.com/en-u…> The ACPI and USB driver of linux kernel need corresponding functions to support this feature. Please see -https://git.kernel.org/pub/scm/linux/kernel/git/mnyman/xhci.git/log/?h=port_check_acpi_dsm +<https://git.kernel.org/pub/scm/linux/kernel/git/mnyman/xhci.git/log/?h=port…> ### drivers/efi: Add EFI variable store option support @@ -229,7 +229,7 @@ Significant Known and Open Issues --------------------------------- -Issues from the coreboot bugtracker: https://ticket.coreboot.org/ +Issues from the coreboot bugtracker: <https://ticket.coreboot.org/> ```{eval-rst} +-----+-----------------------------------------------------------------+ | # | Subject | diff --git a/Documentation/releases/coreboot-4.21-relnotes.md b/Documentation/releases/coreboot-4.21-relnotes.md index 05d334f..661c019 100644 --- a/Documentation/releases/coreboot-4.21-relnotes.md +++ b/Documentation/releases/coreboot-4.21-relnotes.md @@ -19,7 +19,7 @@ repository was named ‘master’. In line with many other projects, coreboot has decided to switch away from this name and use the name ‘main’ instead. You can read about the initial reasoning on the SFC’s -website: https://sfconservancy.org/news/2020/jun/23/gitbranchname/ +website: <https://sfconservancy.org/news/2020/jun/23/gitbranchname/> At some point before the 4.22 release, coreboot will be switching from the master branch to the main branch. This shouldn’t be a difficult @@ -355,7 +355,7 @@ --------------------------------- -Issues from the coreboot bugtracker: https://ticket.coreboot.org/ +Issues from the coreboot bugtracker: <https://ticket.coreboot.org/> ```{eval-rst} +-----+-----------------------------------------------------------------+ | # | Subject | @@ -398,10 +398,10 @@ coreboot Links and Contact Information -------------------------------------- -* Main Web site: https://www.coreboot.org -* IRC: https://web.libera.chat/#coreboot -* Downloads: https://coreboot.org/downloads.html -* Source control: https://review.coreboot.org -* Documentation: https://doc.coreboot.org -* Issue tracker: https://ticket.coreboot.org/projects/coreboot -* Donations: https://coreboot.org/donate.html +* Main Web site: <https://www.coreboot.org> +* IRC: <https://web.libera.chat/#coreboot> +* Downloads: <https://coreboot.org/downloads.html> +* Source control: <https://review.coreboot.org> +* Documentation: <https://doc.coreboot.org> +* Issue tracker: <https://ticket.coreboot.org/projects/coreboot> +* Donations: <https://coreboot.org/donate.html> diff --git a/Documentation/releases/coreboot-4.22-relnotes.md b/Documentation/releases/coreboot-4.22-relnotes.md index 8d0cc7a..f5ca7e8 100644 --- a/Documentation/releases/coreboot-4.22-relnotes.md +++ b/Documentation/releases/coreboot-4.22-relnotes.md @@ -263,7 +263,7 @@ Significant Known and Open Issues --------------------------------- -Issues from the coreboot bugtracker: https://ticket.coreboot.org/ +Issues from the coreboot bugtracker: <https://ticket.coreboot.org/> ### Payload-specific issues @@ -341,9 +341,9 @@ coreboot Links and Contact Information -------------------------------------- -* Main Website: https://www.coreboot.org -* Downloads: https://coreboot.org/downloads.html -* Source control: https://review.coreboot.org -* Documentation: https://doc.coreboot.org -* Issue tracker: https://ticket.coreboot.org/projects/coreboot -* Donations: https://coreboot.org/donate.html +* Main Website: <https://www.coreboot.org> +* Downloads: <https://coreboot.org/downloads.html> +* Source control: <https://review.coreboot.org> +* Documentation: <https://doc.coreboot.org> +* Issue tracker: <https://ticket.coreboot.org/projects/coreboot> +* Donations: <https://coreboot.org/donate.html> diff --git a/Documentation/releases/coreboot-4.3-relnotes.md b/Documentation/releases/coreboot-4.3-relnotes.md index c0dda6e..d8e8f35 100644 --- a/Documentation/releases/coreboot-4.3-relnotes.md +++ b/Documentation/releases/coreboot-4.3-relnotes.md @@ -10,7 +10,7 @@ authors added a net total of 17500 lines to the source code. Thank you to all who contributed! -The release tarballs are available at http://www.coreboot.org/releases/. +The release tarballs are available at <http://www.coreboot.org/releases/>. There's also a 4.3 tag and branch in the git repository. Besides the usual addition of new mainboards (14) and chipsets diff --git a/Documentation/releases/coreboot-4.4-relnotes.md b/Documentation/releases/coreboot-4.4-relnotes.md index 2207c7f..ee3f8d4 100644 --- a/Documentation/releases/coreboot-4.4-relnotes.md +++ b/Documentation/releases/coreboot-4.4-relnotes.md @@ -5,7 +5,7 @@ fourth quarterly release. Since the last release, we've had 850 commits by 90 authors adding 59000 lines to the codebase. -The release tarballs are available at https://www.coreboot.org/releases/ +The release tarballs are available at <https://www.coreboot.org/releases/> There is a 4.4 tag and branch in the git repository. Log of commit 3141eac900 to commit 588ccaa9a7 diff --git a/Documentation/releases/coreboot-4.5-relnotes.md b/Documentation/releases/coreboot-4.5-relnotes.md index 12230b2..5b971a2 100644 --- a/Documentation/releases/coreboot-4.5-relnotes.md +++ b/Documentation/releases/coreboot-4.5-relnotes.md @@ -13,7 +13,7 @@ commits by 119 authors. The release tarballs and gpg signatures are available in the usual place -at https://www.coreboot.org/downloads +at <https://www.coreboot.org/downloads> There is a 4.5 tag in the git repository, and a branch will be created as needed. diff --git a/Documentation/releases/coreboot-4.6-relnotes.md b/Documentation/releases/coreboot-4.6-relnotes.md index 13af7e4..9f4d826 100644 --- a/Documentation/releases/coreboot-4.6-relnotes.md +++ b/Documentation/releases/coreboot-4.6-relnotes.md @@ -8,7 +8,7 @@ Since the last release in October 2016, the coreboot project had 1708 commits by 121 authors. The release tarballs and gpg signatures are -available in the usual place at https://www.coreboot.org/downloads +available in the usual place at <https://www.coreboot.org/downloads> There is a pgp signed 4.6 tag in the git repository, and a branch will be created as needed. @@ -22,7 +22,7 @@ console now persists between reboots and is able to be used on some platforms via late init. Also there is a new Linux kernel driver which removes the need for the old cbmem tool to read from the cbmem area. You -can find the patch here https://patchwork.kernel.org/patch/9641997/ and +can find the patch here <https://patchwork.kernel.org/patch/9641997/> and it can be enabled via GOOGLE_MEMCONSOLE_COREBOOT kconfig option in your kernel - Note that this name may change going forward. @@ -51,7 +51,7 @@ cbui and is based on the nuklear graphics library including keyboard and mouse support. The cbui payload is currently expected to be merged into the main coreboot tree before the next release. The upstream repository -is here: https://github.com/siro20/coreboot/tree/cbui/payloads/cbui +is here: <https://github.com/siro20/coreboot/tree/cbui/payloads/cbui> ### UEFI support: A long road to go @@ -65,7 +65,7 @@ We started to make progress with the integration into our sources and the hope is that by the end of the summer, we finally support the edk2 payload out-of-the- box. See the current patch state at -http://review.coreboot.org/#/c/15057/ +<http://review.coreboot.org/#/c/15057/> ### Fighting blobs and proprietary HW components @@ -76,7 +76,7 @@ run in a functional error state and reduce it from 1.5/5MB to 80KB. It's not perfect but it works from Nehalem up to Skylake based Intel systems. The tool is now integrated into the coreboot build system. The upstream -repository is https://github.com/corna/me_cleaner +repository is <https://github.com/corna/me_cleaner> Another ongoing improvement is the new utility blobtool. It is currently used for generating the flash descriptor and GbE configuration data on diff --git a/Documentation/releases/coreboot-4.8.1-relnotes.md b/Documentation/releases/coreboot-4.8.1-relnotes.md index f96e2cc..05fb590 100644 --- a/Documentation/releases/coreboot-4.8.1-relnotes.md +++ b/Documentation/releases/coreboot-4.8.1-relnotes.md @@ -63,7 +63,7 @@ * qemu-i440fx: Fix ACPI checksum corruption * intelmetool: Fix crash, support ME11+ platforms, fix bootguard detection -* tpm: Fix TPM software stack vulnerability in tlcl_read() for TPM 1.2 (https://github.com/nccgroup/TPMGenie) +* tpm: Fix TPM software stack vulnerability in tlcl_read() for TPM 1.2 ()<https://github.com/nccgroup/TPMGenie>) * asrock/b75pro3-m: Fixed HDMI * Intel/ibexpeak: Fix missing ACPI PIRQ entries * Intel/nehalem: Fix freeze during chipset lockdown @@ -86,7 +86,7 @@ Documentation ------------- * Switch from Hugo to Sphinx for the Documentation -* Working on markdown documentation for https://doc.coreboot.org +* Working on markdown documentation for <https://doc.coreboot.org> Added 17 mainboards ------------------- diff --git a/Documentation/soc/intel/xeon_sp/community_preview_guide.md b/Documentation/soc/intel/xeon_sp/community_preview_guide.md index 96ff86f..9e01d52 100644 --- a/Documentation/soc/intel/xeon_sp/community_preview_guide.md +++ b/Documentation/soc/intel/xeon_sp/community_preview_guide.md @@ -4,10 +4,10 @@ ## Background Xeon 6 basic boot supports are initially upstreamed at -https://review.coreboot.org/q/topic:%22Xeon6-Basic-Boot%22. +<https://review.coreboot.org/q/topic:%22Xeon6-Basic-Boot%22>. Full feature supports are previewed at -https://review.coreboot.org/admin/repos/intel-dev-pub,general +<https://review.coreboot.org/admin/repos/intel-dev-pub,general> The supported platform status are as below, diff --git a/Documentation/technotes/2015-11-rebuilding-coreboot-image-generation.md b/Documentation/technotes/2015-11-rebuilding-coreboot-image-generation.md index a3f81bf..7abfab1 100644 --- a/Documentation/technotes/2015-11-rebuilding-coreboot-image-generation.md +++ b/Documentation/technotes/2015-11-rebuilding-coreboot-image-generation.md @@ -136,8 +136,8 @@ By having a global picture of the final image’s requirements, we can also avoid issues where files added earlier may prevent later additions that have stricter constraints - without resorting to hacks like -https://chromium-review.googlesource.com/289491 that reorder the file addition -manually. +<https://chromium-review.googlesource.com/289491> that reorder the file +addition manually. Example ------- diff --git a/Documentation/technotes/console.md b/Documentation/technotes/console.md index a125728..363dfa5 100644 --- a/Documentation/technotes/console.md +++ b/Documentation/technotes/console.md @@ -1,7 +1,7 @@ # coreboot Console coreboot supports multiple ways to access its console. -https://www.coreboot.org/Console_and_outputs +<https://www.coreboot.org/Console_and_outputs> ## SMBus Console -- To view, visit https://review.coreboot.org/c/coreboot/+/85433?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I234d395cddd58f3d3dfb4b4ddccb6efc70d4dd9e Gerrit-Change-Number: 85433 Gerrit-PatchSet: 1 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com>

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[XL] Change in coreboot[main]: ec/hp: Add Nuvoton NPCE586H
by Nicholas Sudsgaard (Code Review) 01 Dec '24

01 Dec '24

Nicholas Sudsgaard has posted comments on this change by Nicholas Sudsgaard. ( https://review.coreboot.org/c/coreboot/+/85279?usp=email ) Change subject: ec/hp: Add Nuvoton NPCE586H ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/85279?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7294492baedcc983e3c751f1cf31d6656cfd7b14 Gerrit-Change-Number: 85279 Gerrit-PatchSet: 5 Gerrit-Owner: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 01 Dec 2024 13:20:42 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[L] Change in coreboot[main]: mainboard/hp: Add ProBook 450 G3
by Nicholas Sudsgaard (Code Review) 01 Dec '24

01 Dec '24

Nicholas Sudsgaard has posted comments on this change by Nicholas Sudsgaard. ( https://review.coreboot.org/c/coreboot/+/83433?usp=email ) Change subject: mainboard/hp: Add ProBook 450 G3 ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/83433?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic1cee48b4b187ac8b5fcda099a99956658821920 Gerrit-Change-Number: 83433 Gerrit-PatchSet: 16 Gerrit-Owner: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Comment-Date: Sun, 01 Dec 2024 13:20:36 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

1 0

[S] Change in coreboot[main]: mb/asus/p8x7x-series: Blink power LED during suspend
by Paul Menzel (Code Review) 01 Dec '24

01 Dec '24

Attention is currently required from: Keith Hui. Paul Menzel has posted comments on this change by Keith Hui. ( https://review.coreboot.org/c/coreboot/+/82557?usp=email ) Change subject: mb/asus/p8x7x-series: Blink power LED during suspend ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/82557?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie30e5ef79a87a3dca6875b0a6e07ae99d0d79e6e Gerrit-Change-Number: 82557 Gerrit-PatchSet: 2 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Comment-Date: Sun, 01 Dec 2024 11:17:40 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/asus/p8x7x-series: Mark variants using GPIO8 for power LED
by Paul Menzel (Code Review) 01 Dec '24

01 Dec '24

Attention is currently required from: Keith Hui. Paul Menzel has posted comments on this change by Keith Hui. ( https://review.coreboot.org/c/coreboot/+/82556?usp=email ) Change subject: mb/asus/p8x7x-series: Mark variants using GPIO8 for power LED ...................................................................... Patch Set 2: Code-Review+1 (1 comment) File src/mainboard/asus/p8x7x-series/Kconfig: https://review.coreboot.org/c/coreboot/+/82556/comment/2424b2f5_b211b93d?us… : PS2, Line 66: If power LED doesn't blink when entering S3 suspend, try setting this. It’d be great if you elaborate and added the information from the commit message regarding the GPIOs. Maybe even add, if this can only be deduced from the board view, but also from a running system or the ASL/ACPI code. -- To view, visit https://review.coreboot.org/c/coreboot/+/82556?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4d42cd9ac497a4200ab5c90d09eb4dbab8917b30 Gerrit-Change-Number: 82556 Gerrit-PatchSet: 2 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Comment-Date: Sun, 01 Dec 2024 11:17:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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coreboot-gerrit December 2024