coreboot-gerrit December 2024

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[XS] Change in coreboot[main]: .checkpatch.conf: Set max line length to 96
by Yu-Ping Wu (Code Review) 02 Dec '24

02 Dec '24

Yu-Ping Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85435?usp=email ) Change subject: .checkpatch.conf: Set max line length to 96 ...................................................................... .checkpatch.conf: Set max line length to 96 Linux upstream's checkpatch.pl has a default max line length of 100. Since coreboot uses 96, add --max-line-length=96 to the config file. Change-Id: I7737f3d2e0d016b0f0dd82df2865a6b51b667066 Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org> --- M .checkpatch.conf 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/85435/1 diff --git a/.checkpatch.conf b/.checkpatch.conf index ac261a4..f57474d 100644 --- a/.checkpatch.conf +++ b/.checkpatch.conf @@ -1,3 +1,6 @@ +# Override checkpatch's default max line length 100 +--max-line-length=96 + # Not Linux, so don't expect a Linux tree. --no-tree -- To view, visit https://review.coreboot.org/c/coreboot/+/85435?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7737f3d2e0d016b0f0dd82df2865a6b51b667066 Gerrit-Change-Number: 85435 Gerrit-PatchSet: 1 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com>

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[XS] Change in coreboot[main]: soc/intel/xeon_xp: Fix lower ram range bug
by Name of user not set (Code Review) 02 Dec '24

02 Dec '24

yuchi.chen(a)intel.com has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85434?usp=email ) Change subject: soc/intel/xeon_xp: Fix lower ram range bug ...................................................................... soc/intel/xeon_xp: Fix lower ram range bug Generally the base address of FSP output is already aligned so there is no need to minus 1. The current code loses 1 byte in the lower DRAM address space. Change-Id: Ia8147702aad496c431cf10b896d68a826c9e45b1 Signed-off-by: Yuchi Chen <yuchi.chen(a)intel.com> --- M src/soc/intel/xeon_sp/uncore.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/85434/1 diff --git a/src/soc/intel/xeon_sp/uncore.c b/src/soc/intel/xeon_sp/uncore.c index 1d77675..93677b9 100644 --- a/src/soc/intel/xeon_sp/uncore.c +++ b/src/soc/intel/xeon_sp/uncore.c @@ -268,7 +268,7 @@ /* 1MB -> top_of_ram */ fsp_find_reserved_memory(&fsp_mem); - top_of_ram = range_entry_base(&fsp_mem) - 1; + top_of_ram = range_entry_base(&fsp_mem); res = ram_from_to(dev, index++, 1 * MiB, top_of_ram); LOG_RESOURCE("low_ram", dev, res); -- To view, visit https://review.coreboot.org/c/coreboot/+/85434?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia8147702aad496c431cf10b896d68a826c9e45b1 Gerrit-Change-Number: 85434 Gerrit-PatchSet: 1 Gerrit-Owner: yuchi.chen(a)intel.com

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[L] Change in coreboot[main]: mb/google/nissa: Create pujjogatwin variant
by Luca Lai (Code Review) 02 Dec '24

02 Dec '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Luca Lai, Matt DeVillier, Nick Vaccaro, Paul Menzel, Roger Wang, Subrata Banik. Luca Lai has uploaded a new patch set (#17) to the change originally created by Roger Wang. ( https://review.coreboot.org/c/coreboot/+/85329?usp=email ) The following approvals got outdated and were removed: Code-Review+2 by Eric Lai, Code-Review+2 by Matt DeVillier, Code-Review+2 by Subrata Banik, Verified+1 by build bot (Jenkins) The change is no longer submittable: Code-Review and Verified are unsatisfied now. Change subject: mb/google/nissa: Create pujjogatwin variant ...................................................................... mb/google/nissa: Create pujjogatwin variant Create the pujjogatwin variant of nissa reference board by copying the pujjoga files to a new directory named for the variant. The difference between pujjoga and pujjogatwin is that pujjogatwin use TwinLake CPU and firmware config, so copying the pujjoga setting files to create new variant. BUG=b:381152086 TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_PUJJOGATWIN Change-Id: I345ce463699840b10016555bb104a16968e7a8c1 Signed-off-by: Roger Wang <roger2.wang(a)lcfc.corp-partner.google.com> Signed-off-by: Luca Lai <luca.lai(a)lcfc.corp-partner.google.com> --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/Kconfig.name M src/mainboard/google/brya/variants/pujjoga/memory/Makefile.mk M src/mainboard/google/brya/variants/pujjoga/memory/dram_id.generated.txt M src/mainboard/google/brya/variants/pujjoga/memory/mem_parts_used.txt A src/mainboard/google/brya/variants/pujjoga/overridetree_pujjogatwin.cb 6 files changed, 502 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/85329/17 -- To view, visit https://review.coreboot.org/c/coreboot/+/85329?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I345ce463699840b10016555bb104a16968e7a8c1 Gerrit-Change-Number: 85329 Gerrit-PatchSet: 17 Gerrit-Owner: Roger Wang <roger2.wang(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Luca Lai <luca.lai(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jerry2 Huang <jerry2.huang(a)lcfc.corp-partner.google.com> Gerrit-CC: Lauren Ting <lauren.ting(a)lcfc.corp-partner.google.com> Gerrit-CC: Lucien Kao <lucien.kao(a)lcfc.corp-partner.google.com> Gerrit-CC: Mike Lee <mike.lee(a)lcfc.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Luca Lai <luca.lai(a)lcfc.corp-partner.google.com> Gerrit-Attention: Roger Wang <roger2.wang(a)lcfc.corp-partner.google.com>

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[L] Change in coreboot[main]: mb/google/nissa: Create pujjogatwin variant
by Eric Lai (Code Review) 02 Dec '24

02 Dec '24

Attention is currently required from: Dinesh Gehlot, Jayvik Desai, Kapil Porwal, Luca Lai, Nick Vaccaro, Paul Menzel, Roger Wang. Eric Lai has posted comments on this change by Roger Wang. ( https://review.coreboot.org/c/coreboot/+/85329?usp=email ) Change subject: mb/google/nissa: Create pujjogatwin variant ...................................................................... Patch Set 16: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85329?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I345ce463699840b10016555bb104a16968e7a8c1 Gerrit-Change-Number: 85329 Gerrit-PatchSet: 16 Gerrit-Owner: Roger Wang <roger2.wang(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Luca Lai <luca.lai(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jerry2 Huang <jerry2.huang(a)lcfc.corp-partner.google.com> Gerrit-CC: Lauren Ting <lauren.ting(a)lcfc.corp-partner.google.com> Gerrit-CC: Lucien Kao <lucien.kao(a)lcfc.corp-partner.google.com> Gerrit-CC: Mike Lee <mike.lee(a)lcfc.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Luca Lai <luca.lai(a)lcfc.corp-partner.google.com> Gerrit-Attention: Roger Wang <roger2.wang(a)lcfc.corp-partner.google.com> Gerrit-Comment-Date: Mon, 02 Dec 2024 02:11:10 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: drivers/usb/intel_bluetooth: Fix GBTE return value
by Nicholas Sudsgaard (Code Review) 02 Dec '24

02 Dec '24

Attention is currently required from: Sean Rhodes. Nicholas Sudsgaard has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/84989?usp=email ) Change subject: drivers/usb/intel_bluetooth: Fix GBTE return value ...................................................................... Patch Set 1: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/84989/comment/a3be5de5_f4efdc48?us… : PS1, Line 9: `acpigen_soc_get_tx_gpio` will put the result into LOCAL0, rather than nit: Local0 File src/drivers/usb/acpi/intel_bluetooth.c: https://review.coreboot.org/c/coreboot/+/84989/comment/57add2c5_a97fb81c?us… : PS1, Line 329: This is not needed as you use `acpigen_write_return_*` instead. -- To view, visit https://review.coreboot.org/c/coreboot/+/84989?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I13263d479d1a4520abaf1b6b38514d021e7d4dc9 Gerrit-Change-Number: 84989 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Mon, 02 Dec 2024 01:45:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: mb/purism/librem_cnl: Add ramtop to cmos.layout for librem_mini
by Felix Singer (Code Review) 02 Dec '24

02 Dec '24

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/77670?usp=email ) Change subject: mb/purism/librem_cnl: Add ramtop to cmos.layout for librem_mini ...................................................................... mb/purism/librem_cnl: Add ramtop to cmos.layout for librem_mini Since commit e633d370 (soc/intel/cometlake: Enable early caching of RAMTOP region), cmos.layout for Cannon Lake boards must have a ramtop entry, add it. Change-Id: I2bf71f2dd79f2e1e2e13f62a3e08103336bbad61 Signed-off-by: Jonathon Hall <jonathon.hall(a)puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77670 Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/purism/librem_cnl/variants/librem_mini/cmos.layout 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Felix Singer: Looks good to me, approved diff --git a/src/mainboard/purism/librem_cnl/variants/librem_mini/cmos.layout b/src/mainboard/purism/librem_cnl/variants/librem_mini/cmos.layout index 454ea8b..1c5b536 100644 --- a/src/mainboard/purism/librem_cnl/variants/librem_mini/cmos.layout +++ b/src/mainboard/purism/librem_cnl/variants/librem_mini/cmos.layout @@ -4,6 +4,7 @@ # start-bit length config config-ID name 0 112 r 0 reserved_memory +400 80 r 0 ramtop 1352 8 e 1 power_on_after_fail enumerations -- To view, visit https://review.coreboot.org/c/coreboot/+/77670?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2bf71f2dd79f2e1e2e13f62a3e08103336bbad61 Gerrit-Change-Number: 77670 Gerrit-PatchSet: 7 Gerrit-Owner: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: mb/purism/librem_cnl: Add ramtop to cmos.layout for librem_mini
by Felix Singer (Code Review) 02 Dec '24

02 Dec '24

Attention is currently required from: Angel Pons, Felix Held, Jonathon Hall, Paul Menzel. Felix Singer has posted comments on this change by Jonathon Hall. ( https://review.coreboot.org/c/coreboot/+/77670?usp=email ) Change subject: mb/purism/librem_cnl: Add ramtop to cmos.layout for librem_mini ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/77670?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2bf71f2dd79f2e1e2e13f62a3e08103336bbad61 Gerrit-Change-Number: 77670 Gerrit-PatchSet: 6 Gerrit-Owner: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 02 Dec 2024 01:03:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: Documentation: Add information about the deguard utility
by Nicholas Chin (Code Review) 02 Dec '24

02 Dec '24

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[M] Change in coreboot[main]: Documentation: Add information about the deguard utility
by Nicholas Chin (Code Review) 02 Dec '24

02 Dec '24

Attention is currently required from: Elyes Haouas, Felix Singer, Máté Kukri. Nicholas Chin has posted comments on this change by Máté Kukri. ( https://review.coreboot.org/c/coreboot/+/84825?usp=email ) Change subject: Documentation: Add information about the deguard utility ...................................................................... Patch Set 3: (1 comment) File Documentation/soc/intel/index.md: https://review.coreboot.org/c/coreboot/+/84825/comment/fb3e80ca_199449be?us… : PS3, Line 19: Skylake/Kaby Lake BootGuard bypass <deguard.md> > Not sure if soc/intel is the appropriate section for that. @nic.c3.14@gmail. […] I can see how it's somewhat relevant to soc/intel, since it's currently specific to certain Intel chips, though I agree that it probably would be better somewhere else. However, I don't really think any existing section fits it well. Util would probably be the closest, but it is intended for utilities in `util` directory of coreboot's tree. Historically these sort of bypasses were board vendor specific and documented in mainboard/vendor (such as HP Sure Start), but deguard is a board vendor agnostic utility. I think it would fit best in some general section related to porting coreboot (and probably a subsection for porting Intel systems), as Bootguard has historically been a major consideration into whether a board could be ported. Things like porting guides could also be put in there. Then there could be some page about whether or not coreboot can be ported to some system (discussing things like whether coreboot has support for the chips on a platform and Bootguard), which could link to the deguard documentation in reference to platforms where Bootguard can be bypassed. -- To view, visit https://review.coreboot.org/c/coreboot/+/84825?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idba0f461d31db31cbc9c35ee3da70c116d5493ce Gerrit-Change-Number: 84825 Gerrit-PatchSet: 3 Gerrit-Owner: Máté Kukri <km(a)mkukri.xyz> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Máté Kukri <km(a)mkukri.xyz> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Mon, 02 Dec 2024 00:45:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>

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[M] Change in coreboot[main]: Documentation: Add information about the deguard utility
by Felix Singer (Code Review) 02 Dec '24

02 Dec '24

Attention is currently required from: Elyes Haouas, Máté Kukri, Nicholas Chin. Felix Singer has posted comments on this change by Máté Kukri. ( https://review.coreboot.org/c/coreboot/+/84825?usp=email ) Change subject: Documentation: Add information about the deguard utility ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/84825?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idba0f461d31db31cbc9c35ee3da70c116d5493ce Gerrit-Change-Number: 84825 Gerrit-PatchSet: 3 Gerrit-Owner: Máté Kukri <km(a)mkukri.xyz> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Máté Kukri <km(a)mkukri.xyz> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Mon, 02 Dec 2024 00:08:10 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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coreboot-gerrit December 2024