coreboot-gerrit December 2024

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[M] Change in coreboot[main]: mb/asrock/h77pro4-m/dt: Remove superfluous comments
by Riku Viitanen (Code Review) 24 Dec '24

24 Dec '24

Riku Viitanen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85761?usp=email ) Change subject: mb/asrock/h77pro4-m/dt: Remove superfluous comments ...................................................................... mb/asrock/h77pro4-m/dt: Remove superfluous comments Change-Id: Ie8d8d5287af8f3084f23c9d882202aa6ac8d4c5f Signed-off-by: Riku Viitanen <riku.viitanen(a)protonmail.com> --- M src/mainboard/asrock/h77pro4-m/devicetree.cb 1 file changed, 26 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/85761/1 diff --git a/src/mainboard/asrock/h77pro4-m/devicetree.cb b/src/mainboard/asrock/h77pro4-m/devicetree.cb index dc410ac..9d47057 100644 --- a/src/mainboard/asrock/h77pro4-m/devicetree.cb +++ b/src/mainboard/asrock/h77pro4-m/devicetree.cb @@ -3,13 +3,13 @@ chip northbridge/intel/sandybridge register "spd_addresses" = "{0x50, 0x51, 0x52, 0x53}" device domain 0 on - device ref host_bridge on # Host bridge + device ref host_bridge on subsystemid 0x1849 0x0100 end - device ref peg10 on # PEG - slot "PCIE1" + device ref peg10 on smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthLong" "PCIE1" "SlotDataBusWidth16X" end - device ref igd on # iGPU + device ref igd on subsystemid 0x1849 0x0102 end chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH @@ -39,49 +39,49 @@ { 1, 1, 5 }, { 1, 0, 6 } }" - device ref xhci on # USB 3.0 Controller + device ref xhci on subsystemid 0x1849 0x1e31 end - device ref mei1 on # Management Engine Interface 1 + device ref mei1 on subsystemid 0x1849 0x1e3a end - device ref mei2 off end # Management Engine Interface 2 - device ref me_ide_r off end # Management Engine IDE-R - device ref me_kt off end # Management Engine KT - device ref gbe off end # Intel Gigabit Ethernet - device ref ehci2 on # USB2 EHCI #2 + device ref mei2 off end + device ref me_ide_r off end + device ref me_kt off end + device ref gbe off end + device ref ehci2 on subsystemid 0x1849 0x1e2d end - device ref hda on # High Definition Audio + device ref hda on subsystemid 0x1849 0x8892 end - device ref pcie_rp1 on # PCIe Port #1 - slot "PCIE4", 4 lanes + device ref pcie_rp1 on subsystemid 0x1849 0x1e10 smbios_slot_desc "SlotTypePciExpressGen2X4" "SlotLengthLong" "PCIE4" "SlotDataBusWidth4X" end - device ref pcie_rp2 off end # PCIe Port #2 - device ref pcie_rp3 off end # PCIe Port #3 - device ref pcie_rp4 off end # PCIe Port #4 - device ref pcie_rp5 on # PCIe Port #5 - slot "PCIE2", 1 lane + device ref pcie_rp2 off end + device ref pcie_rp3 off end + device ref pcie_rp4 off end + device ref pcie_rp5 on subsystemid 0x1849 0x1e18 smbios_slot_desc "SlotTypePciExpressGen2X1" "SlotLengthShort" "PCIE2" "SlotDataBusWidth1X" end - device ref pcie_rp6 on # PCIe Port #6 - RTL8111E GbE + device ref pcie_rp6 on # RTL8111E GbE subsystemid 0x1849 0x1e1a device pci 00.0 on end # PCI 10ec:8168 end - device ref pcie_rp7 on # PCIe Port #7 - slot "PCIE3", 1 lane + device ref pcie_rp7 on subsystemid 0x1849 0x1e16 smbios_slot_desc "SlotTypePciExpressGen2X1" "SlotLengthLong" "PCIE3" "SlotDataBusWidth1X" end - device ref pcie_rp8 on # PCIe Port #8 - ASM1061 SATA Controller + device ref pcie_rp8 on # ASM1061 SATA Controller subsystemid 0x1849 0x1e1e end - device ref ehci1 on # USB2 EHCI #1 + device ref ehci1 on subsystemid 0x1849 0x1e26 end - device ref pci_bridge off end # PCI bridge - device ref lpc on # LPC bridge + device ref pci_bridge off end + device ref lpc on subsystemid 0x1849 0x1e4a chip superio/nuvoton/nct6776 device pnp 2e.0 off end # Floppy @@ -141,14 +141,14 @@ device pnp 2e.17 off end # GPIOA end end - device ref sata1 on # SATA (AHCI) + device ref sata1 on subsystemid 0x1849 0x1e02 end - device ref smbus on # SMBus + device ref smbus on subsystemid 0x1849 0x1e22 end - device ref sata2 off end # SATA (Legacy) - device ref thermal off end # Thermal + device ref sata2 off end + device ref thermal off end end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/85761?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie8d8d5287af8f3084f23c9d882202aa6ac8d4c5f Gerrit-Change-Number: 85761 Gerrit-PatchSet: 1 Gerrit-Owner: Riku Viitanen <riku.viitanen(a)protonmail.com>

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[XS] Change in coreboot[main]: mb/asrock/h77pro4-m: Add SMBIOS slot descriptions
by Riku Viitanen (Code Review) 24 Dec '24

24 Dec '24

Riku Viitanen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85760?usp=email ) Change subject: mb/asrock/h77pro4-m: Add SMBIOS slot descriptions ...................................................................... mb/asrock/h77pro4-m: Add SMBIOS slot descriptions Based mostly on the comments in the file. Physical slot lengths checked from manufacturer's specs online. Change-Id: I706910dd192ca3415082955a7611d17702d3cfba Signed-off-by: Riku Viitanen <riku.viitanen(a)protonmail.com> --- M src/mainboard/asrock/h77pro4-m/devicetree.cb 1 file changed, 6 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/85760/1 diff --git a/src/mainboard/asrock/h77pro4-m/devicetree.cb b/src/mainboard/asrock/h77pro4-m/devicetree.cb index 05cb870..dc410ac 100644 --- a/src/mainboard/asrock/h77pro4-m/devicetree.cb +++ b/src/mainboard/asrock/h77pro4-m/devicetree.cb @@ -6,7 +6,9 @@ device ref host_bridge on # Host bridge subsystemid 0x1849 0x0100 end - device ref peg10 on end # PEG - slot "PCIE1" + device ref peg10 on # PEG - slot "PCIE1" + smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthLong" "PCIE1" "SlotDataBusWidth16X" + end device ref igd on # iGPU subsystemid 0x1849 0x0102 end @@ -55,12 +57,14 @@ end device ref pcie_rp1 on # PCIe Port #1 - slot "PCIE4", 4 lanes subsystemid 0x1849 0x1e10 + smbios_slot_desc "SlotTypePciExpressGen2X4" "SlotLengthLong" "PCIE4" "SlotDataBusWidth4X" end device ref pcie_rp2 off end # PCIe Port #2 device ref pcie_rp3 off end # PCIe Port #3 device ref pcie_rp4 off end # PCIe Port #4 device ref pcie_rp5 on # PCIe Port #5 - slot "PCIE2", 1 lane subsystemid 0x1849 0x1e18 + smbios_slot_desc "SlotTypePciExpressGen2X1" "SlotLengthShort" "PCIE2" "SlotDataBusWidth1X" end device ref pcie_rp6 on # PCIe Port #6 - RTL8111E GbE subsystemid 0x1849 0x1e1a @@ -68,6 +72,7 @@ end device ref pcie_rp7 on # PCIe Port #7 - slot "PCIE3", 1 lane subsystemid 0x1849 0x1e16 + smbios_slot_desc "SlotTypePciExpressGen2X1" "SlotLengthLong" "PCIE3" "SlotDataBusWidth1X" end device ref pcie_rp8 on # PCIe Port #8 - ASM1061 SATA Controller subsystemid 0x1849 0x1e1e -- To view, visit https://review.coreboot.org/c/coreboot/+/85760?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I706910dd192ca3415082955a7611d17702d3cfba Gerrit-Change-Number: 85760 Gerrit-PatchSet: 1 Gerrit-Owner: Riku Viitanen <riku.viitanen(a)protonmail.com>

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[S] Change in coreboot[main]: ec/google/chromeec: Add API to check if battery is critically low
by Subrata Banik (Code Review) 24 Dec '24

24 Dec '24

Attention is currently required from: Boris Mittelberg, Caveh Jalali. Hello Boris Mittelberg, Caveh Jalali, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85759?usp=email to look at the new patch set (#2). Change subject: ec/google/chromeec: Add API to check if battery is critically low ...................................................................... ec/google/chromeec: Add API to check if battery is critically low This patch adds a new API `google_chromeec_is_below_critical_threshold() ` to check if the battery level is below the critical threshold. The API uses the existing `ec_cmd_battery_get_dynamic()` command to retrieve the battery flags and checks the `EC_BATT_FLAG_LEVEL_CRITICAL` flag to determine if the battery level is critical. This API can be used by other components to query the battery critical status and take necessary actions, for example, while the system is booting with low battery fuel with and/or without an AC charger attached. This addresses the need to implement a low battery charger icon and detect when the system is booting with low battery fuel. The existing `google_chromeec_is_battery_present_and_above_critical_threshold()` API is not suitable for this purpose because any negative decision (like battery not present and/or battery is critically low) implemented around this existing API will also render the lower battery indicator when the system is booting into battery cut-off mode. Ideally, we do not wish to render any icon and simply allow boot to the OS during system battery cut-off boot. BUG=b:377798581 TEST=Able to read the battery status correctly while booting google/fatcat. Change-Id: Id1fc1df374fb4c663becc371c69b285d8b9957ff Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/ec/google/chromeec/ec.c M src/ec/google/chromeec/ec.h 2 files changed, 24 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/85759/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85759?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id1fc1df374fb4c663becc371c69b285d8b9957ff Gerrit-Change-Number: 85759 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com>

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[S] Change in coreboot[main]: ec/google/chromeec: Add API to check if battery is critically low
by Subrata Banik (Code Review) 24 Dec '24

24 Dec '24

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85759?usp=email ) Change subject: ec/google/chromeec: Add API to check if battery is critically low ...................................................................... ec/google/chromeec: Add API to check if battery is critically low This patch adds a new API `google_chromeec_is_below_critical_threshold() ` to check if the battery level is below the critical threshold. The API uses the existing `ec_cmd_battery_get_dynamic()` command to retrieve the battery flags and checks the `EC_BATT_FLAG_LEVEL_CRITICAL` flag to determine if the battery level is critical. This API can be used by other components to query the battery critical status and take necessary actions, for example, while the system is booting with low battery fuel with and/or without an AC charger attached. This addresses the need to implement a low battery charger icon and detect when the system is booting with low battery fuel. The existing `google_chromeec_is_battery_present_and_above_critical_threshold()` API is not suitable for this purpose because any negative decision (like battery not present and/or battery is critically low) implemented around this existing API will also render the lower battery indicator when the system is booting into battery cut-off mode. Ideally, we do not wish to render any icon and simply allow boot to the OS during system battery cut-off boot. BUG=b:377798581 TEST=Able to read the battery status correctly while booting google/fatcat. Change-Id: Id1fc1df374fb4c663becc371c69b285d8b9957ff Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/ec/google/chromeec/ec.c M src/ec/google/chromeec/ec.h 2 files changed, 24 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/85759/1 diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index b6fd5b8..502684c 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -1617,6 +1617,22 @@ return false; } +bool google_chromeec_is_below_critical_threshold(void) +{ + struct ec_params_battery_dynamic_info params = { + .index = 0, + }; + struct ec_response_battery_dynamic_info resp; + + if (ec_cmd_battery_get_dynamic(PLAT_EC, &params, &resp) == 0) { + /* Check if battery LEVEL_CRITICAL is set */ + if (resp.flags & EC_BATT_FLAG_LEVEL_CRITICAL) + return true; + } + + return false; +} + bool google_chromeec_is_battery_present(void) { struct ec_params_battery_dynamic_info params = { diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h index afb1485..a50c311 100644 --- a/src/ec/google/chromeec/ec.h +++ b/src/ec/google/chromeec/ec.h @@ -448,6 +448,14 @@ bool google_chromeec_is_battery_present_and_above_critical_threshold(void); /** + * Check if battery level is below critical threshold. + * + * @return true: if the battery level is below critical threshold + * false: any the above conditions is not true + */ +bool google_chromeec_is_below_critical_threshold(void); + +/** * Check if battery is present. * * @return true: if the battery is present -- To view, visit https://review.coreboot.org/c/coreboot/+/85759?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id1fc1df374fb4c663becc371c69b285d8b9957ff Gerrit-Change-Number: 85759 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com>

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[L] Change in coreboot[main]: mb/asrock: Add Z87 Extreme4 (Haswell)
by Jan Philipp Groß (Code Review) 24 Dec '24

24 Dec '24

Attention is currently required from: Angel Pons, Nicholas Chin. Jan Philipp Groß has posted comments on this change by Jan Philipp Groß. ( https://review.coreboot.org/c/coreboot/+/84672?usp=email ) Change subject: mb/asrock: Add Z87 Extreme4 (Haswell) ...................................................................... Patch Set 5: (1 comment) File src/mainboard/asrock/z87_extreme4/devicetree.cb: https://review.coreboot.org/c/coreboot/+/84672/comment/d83bdfc9_6d4b881a?us… : PS1, Line 54: device pci 1c.0 on # PCIe Port #1 : subsystemid 0x1849 0x8c10 : end : device pci 1c.1 on # PCIe Port #2 : end : device pci 1c.2 on # PCIe Port #3 : subsystemid 0x1849 0x8c14 : end : device pci 1c.3 on # RP #4: PCIe x1 slot : end : device pci 1c.4 on # PCIe Port #5 : end : device pci 1c.5 on # PCIe Port #6 : end : device pci 1c.6 on # PCIe Port #7 : end : device pci 1c.7 on # PCIe Port #8 : end > Enable all in coreboot, populate slots, see which devices exist under there. […] Have a look at the PCIe RPs now. Looking good? -- To view, visit https://review.coreboot.org/c/coreboot/+/84672?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I78791aa9877a3ad79bf8b896c583fedf37e96d9a Gerrit-Change-Number: 84672 Gerrit-PatchSet: 5 Gerrit-Owner: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Tue, 24 Dec 2024 18:09:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jan Philipp Groß <jeangrande(a)mailbox.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

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[L] Change in coreboot[main]: mb/asrock: Add Z87 Extreme4 (Haswell)
by Jan Philipp Groß (Code Review) 24 Dec '24

24 Dec '24

Attention is currently required from: Angel Pons, Nicholas Chin. Hello Angel Pons, Nicholas Chin, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84672?usp=email to look at the new patch set (#5). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/asrock: Add Z87 Extreme4 (Haswell) ...................................................................... mb/asrock: Add Z87 Extreme4 (Haswell) This port was done via autoport and subsequent manual tweaking. The board features two socketed DIP-8 SPI flash chips, as well as a BIOS selection via jumper and onboard Power and Reset switches. Working: - Haswell MRC.bin - All four DDR3/DDR3L DIMM slots - HDMI-Out Port - DVI-D Port - RJ-45 Gigabit LAN Port - Both USB 2.0 Ports - All four USB 3.1 Gen1 Ports - Both USB 3.1 Gen1 headers - Vertical Type A USB 3.1 Gen1 (located next to RAM slots and PCH) - All six SATA3 6.0 Gb/s connectors by Intel - All three PCI Express 3.0 x16 slots (tested with NV 1080 Ti dGPU) - Both PCI Express 2.0 x1 slots (tested with TL-WDN4800 WiFi adapter) - HD Audio Jack (Audio output tested only) - Front Audio Jack (Audio output tested only) Working (board-specific) - Power Switch with LED (functional, yet no LED) - Reset Switch with LED (functional, yet no LED) - BIOS Selection via jumper not working: - both SATA3 6.0 Gb/s connectors by ASMedia ASM1061 not (yet) tested: - IR header - COM Port header - DisplayPort - eSATA connector - USB 2.0 headers - PS/2 Mouse/Keyboard Port - HDMI-In Port - PCI slots not (yet) working: - Software fan control: While the Nuvoton chip is correctly discovered, the numbering of the fan connectors is faulty, resulting in the wrong fan being controlled. - Dr. Debug: on vendor firmware, the LEDs turn off after successful boot. On coreboot, the LED shows two bright zeros after boot. Change-Id: I78791aa9877a3ad79bf8b896c583fedf37e96d9a Signed-off-by: Jan Philipp Groß <jeangrande(a)mailbox.org> --- A src/mainboard/asrock/z87_extreme4/Kconfig A src/mainboard/asrock/z87_extreme4/Kconfig.name A src/mainboard/asrock/z87_extreme4/Makefile.mk A src/mainboard/asrock/z87_extreme4/acpi/ec.asl A src/mainboard/asrock/z87_extreme4/acpi/platform.asl A src/mainboard/asrock/z87_extreme4/acpi/superio.asl A src/mainboard/asrock/z87_extreme4/board_info.txt A src/mainboard/asrock/z87_extreme4/bootblock.c A src/mainboard/asrock/z87_extreme4/data.vbt A src/mainboard/asrock/z87_extreme4/devicetree.cb A src/mainboard/asrock/z87_extreme4/dsdt.asl A src/mainboard/asrock/z87_extreme4/gma-mainboard.ads A src/mainboard/asrock/z87_extreme4/gpio.c A src/mainboard/asrock/z87_extreme4/hda_verb.c A src/mainboard/asrock/z87_extreme4/romstage.c 15 files changed, 536 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/84672/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/84672?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I78791aa9877a3ad79bf8b896c583fedf37e96d9a Gerrit-Change-Number: 84672 Gerrit-PatchSet: 5 Gerrit-Owner: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com>

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[S] Change in coreboot[main]: ec/google/chromeec: Add API to check if charger is present
by Subrata Banik (Code Review) 24 Dec '24

24 Dec '24

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85758?usp=email ) Change subject: ec/google/chromeec: Add API to check if charger is present ...................................................................... ec/google/chromeec: Add API to check if charger is present This patch introduces a new API, `google_chromeec_is_charger_present()`, to determine if a charger is connected. The API leverages the existing `ec_cmd_battery_get_dynamic()` command to retrieve battery flags and checks the `EC_BATT_FLAG_AC_PRESENT` flag to ascertain charger presence. Other components can leverage this API to query the charger status, which is particularly useful for distinguishing between barrel chargers and USB-C chargers after relying on the `google_chromeec_is_usb_pd_attached()` API. BUG=b:377798581 TEST=Able to read the charger status (w/ barrel and/or w/ USB-PD) correctly while booting google/fatcat. Change-Id: Iadf81400f71a51c093f71fe995cacc107c50c7af Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/ec/google/chromeec/ec.c M src/ec/google/chromeec/ec.h 2 files changed, 25 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/85758/1 diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index d0c5fc5..b6fd5b8 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -988,6 +988,23 @@ return false; } +/* This API checks if charger is present. */ +bool google_chromeec_is_charger_present(void) +{ + struct ec_params_battery_dynamic_info params = { + .index = 0, + }; + struct ec_response_battery_dynamic_info resp; + + if (ec_cmd_battery_get_dynamic(PLAT_EC, &params, &resp) == 0) { + /* Check if AC charger is present */ + if (resp.flags & EC_BATT_FLAG_AC_PRESENT) + return true; + } + + return false; +} + int google_chromeec_override_dedicated_charger_limit(uint16_t current_lim, uint16_t voltage_lim) { diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h index cdea70f..afb1485 100644 --- a/src/ec/google/chromeec/ec.h +++ b/src/ec/google/chromeec/ec.h @@ -140,6 +140,14 @@ /* Check if a USB Power Delivery (PD) charger is attached */ bool google_chromeec_is_usb_pd_attached(void); +/** + * Check if charger is present. + * + * @return true: if the charger is present + * false: if the charger is not present + */ +bool google_chromeec_is_charger_present(void); + /* * Set max current and voltage of a dedicated charger. * -- To view, visit https://review.coreboot.org/c/coreboot/+/85758?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iadf81400f71a51c093f71fe995cacc107c50c7af Gerrit-Change-Number: 85758 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com>

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[L] Change in coreboot[main]: mb/asrock: Add Z87 Pro4 (Haswell)
by Jan Philipp Groß (Code Review) 24 Dec '24

24 Dec '24

Attention is currently required from: Angel Pons, Máté Kukri, Nicholas Chin. Jan Philipp Groß has posted comments on this change by Jan Philipp Groß. ( https://review.coreboot.org/c/coreboot/+/85756?usp=email ) Change subject: mb/asrock: Add Z87 Pro4 (Haswell) ...................................................................... Patch Set 3: (8 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/85756/comment/1dcaa74d_99201ed2?us… : PS2, Line 22: - PCI Express 3.0 x16 slots (tested with AMD RX 550 dGPU) > I only see one slot on this mainboard Done https://review.coreboot.org/c/coreboot/+/85756/comment/9f7ca4ec_e4ebdb1d?us… : PS2, Line 30: possible hardware defect) > nit: add 2 spaces to align with previous line Done File src/mainboard/asrock/z87_pro4/Kconfig: https://review.coreboot.org/c/coreboot/+/85756/comment/5e2600f4_0b4e61b5?us… : PS2, Line 25: config USBDEBUG_HCD_INDEX # Neither any of the rear ports nor the vertical port on the board. Can't test the other ones. > How about: […] Done File src/mainboard/asrock/z87_pro4/devicetree.cb: https://review.coreboot.org/c/coreboot/+/85756/comment/417008bd_ca037450?us… : PS2, Line 41: device pci 16.1 on end # MEI 2 > Was this device enabled when using vendor firmware? It wasn't enabled on the initial autoport-created devicetree.cb. I must have accidentally enabled it at one point. I've disabled it again. File src/mainboard/asrock/z87_pro4/gma-mainboard.ads: https://review.coreboot.org/c/coreboot/+/85756/comment/ef77ca2d_9f7a1007?us… : PS2, Line 11: -- FIXME: check this > There are no DP outputs, and only 2 HDMI outputs are used (1 for HDMI, 1 for DVI) Done File src/mainboard/asrock/z87_pro4/hda_verb.c: https://review.coreboot.org/c/coreboot/+/85756/comment/9d0d0123_3ff9f65f?us… : PS2, Line 24: > nit: remove blank line […] Done File src/mainboard/asrock/z87_pro4/romstage.c: https://review.coreboot.org/c/coreboot/+/85756/comment/60d909aa_ab5590ca?us… : PS2, Line 3: #include <stdint.h> > This is probably not needed (and autoport should be updated to not add it) Done https://review.coreboot.org/c/coreboot/+/85756/comment/038d2730_ab82c3b5?us… : PS2, Line 11: /* FIXME: called after romstage_common, remove it if not used */ : void mb_late_romstage_setup(void) : { : } > 🧹 Done -- To view, visit https://review.coreboot.org/c/coreboot/+/85756?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2f01f2f25e0a4bcec10b075b574757250a5e5256 Gerrit-Change-Number: 85756 Gerrit-PatchSet: 3 Gerrit-Owner: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Máté Kukri <km(a)mkukri.xyz> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Máté Kukri <km(a)mkukri.xyz> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Tue, 24 Dec 2024 16:10:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

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[L] Change in coreboot[main]: mb/asrock: Add Z87 Pro4 (Haswell)
by Jan Philipp Groß (Code Review) 24 Dec '24

24 Dec '24

Attention is currently required from: Angel Pons, Jan Philipp Groß, Máté Kukri, Nicholas Chin. Hello Angel Pons, Máté Kukri, Nicholas Chin, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85756?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Code-Review+1 by Angel Pons, Verified+1 by build bot (Jenkins) Change subject: mb/asrock: Add Z87 Pro4 (Haswell) ...................................................................... mb/asrock: Add Z87 Pro4 (Haswell) This port was done via autoport and subsequent manual tweaking. Working: - Haswell MRC.bin - All four DDR3/DDR3L DIMM slots - HDMI-Out Port - DVI-D Port - D-Sub Port - RJ-45 Gigabit LAN Port - All four USB 2.0 Ports - All four USB 3.1 Gen1 Ports - Vertical Type A USB 3.1 Gen1 (located next to RAM slots) - All six SATA3 6.0 Gb/s connectors - PCI Express 3.0 x16 slot (tested with AMD RX 550 dGPU) - PCI Express 2.0 x16 slot (tested with AMD RX 550 dGPU) - Both PCI Express 2.0 x1 slots (tested with TL-WDN4800 WiFi adapter) - HD Audio Jack (Audio output tested only) - Front Audio Jack (Audio output tested only) not working: - Both USB 3.1 Gen1 headers (also not working on vendor firmware, possible hardware defect) not (yet) tested: - IR header - COM Port header - USB 2.0 headers - PS/2 Mouse/Keyboard Port - HDMI-In Port - PCI slots not (yet) working: - Software fan control: While the Nuvoton chip is correctly discovered, the numbering of the fan connectors is faulty, resulting in the wrong fan being controlled. Change-Id: I2f01f2f25e0a4bcec10b075b574757250a5e5256 Signed-off-by: Jan Philipp Groß <jeangrande(a)mailbox.org> --- A src/mainboard/asrock/z87_pro4/Kconfig A src/mainboard/asrock/z87_pro4/Kconfig.name A src/mainboard/asrock/z87_pro4/Makefile.mk A src/mainboard/asrock/z87_pro4/acpi/ec.asl A src/mainboard/asrock/z87_pro4/acpi/platform.asl A src/mainboard/asrock/z87_pro4/acpi/superio.asl A src/mainboard/asrock/z87_pro4/board_info.txt A src/mainboard/asrock/z87_pro4/bootblock.c A src/mainboard/asrock/z87_pro4/data.vbt A src/mainboard/asrock/z87_pro4/devicetree.cb A src/mainboard/asrock/z87_pro4/dsdt.asl A src/mainboard/asrock/z87_pro4/gma-mainboard.ads A src/mainboard/asrock/z87_pro4/gpio.c A src/mainboard/asrock/z87_pro4/hda_verb.c A src/mainboard/asrock/z87_pro4/romstage.c 15 files changed, 522 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/85756/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/85756?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2f01f2f25e0a4bcec10b075b574757250a5e5256 Gerrit-Change-Number: 85756 Gerrit-PatchSet: 3 Gerrit-Owner: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Máté Kukri <km(a)mkukri.xyz> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Máté Kukri <km(a)mkukri.xyz> Gerrit-Attention: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com>

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[L] Change in coreboot[main]: mb/asrock: Add Z87 Pro4 (Haswell)
by Angel Pons (Code Review) 24 Dec '24

24 Dec '24

Attention is currently required from: Jan Philipp Groß, Máté Kukri, Nicholas Chin. Angel Pons has posted comments on this change by Jan Philipp Groß. ( https://review.coreboot.org/c/coreboot/+/85756?usp=email ) Change subject: mb/asrock: Add Z87 Pro4 (Haswell) ...................................................................... Patch Set 2: Code-Review+1 (9 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/85756/comment/9d87c068_2370f455?us… : PS2, Line 22: - PCI Express 3.0 x16 slots (tested with AMD RX 550 dGPU) I only see one slot on this mainboard https://review.coreboot.org/c/coreboot/+/85756/comment/8c68b653_40d51fea?us… : PS2, Line 29: - Both USB 3.1 Gen1 headers (also not working on vendor firmware, I think they're wired to an ASMedia USB 3.0 hub on the mainboard itself. This chip might be dead on your board. I'm pretty sure the Z97 Extreme6 has the same ASMedia USB 3.0 hub (for the rear USB 3.0 ports), so it's likely it would just work anyway (on a board without hardware faults). https://review.coreboot.org/c/coreboot/+/85756/comment/9bfca044_b510db6e?us… : PS2, Line 30: possible hardware defect) nit: add 2 spaces to align with previous line File src/mainboard/asrock/z87_pro4/Kconfig: https://review.coreboot.org/c/coreboot/+/85756/comment/3047bf51_462a3752?us… : PS2, Line 25: config USBDEBUG_HCD_INDEX # Neither any of the rear ports nor the vertical port on the board. Can't test the other ones. How about: ```suggestion # FIXME: Figure out where the EHCI debug port is. It is not # one of the rear ports nor the vertical port on the # mainboard. Can't test the other ports. config USBDEBUG_HCD_INDEX``` File src/mainboard/asrock/z87_pro4/devicetree.cb: https://review.coreboot.org/c/coreboot/+/85756/comment/f3e61335_f233f3ec?us… : PS2, Line 41: device pci 16.1 on end # MEI 2 Was this device enabled when using vendor firmware? File src/mainboard/asrock/z87_pro4/gma-mainboard.ads: https://review.coreboot.org/c/coreboot/+/85756/comment/f730b851_eed28a47?us… : PS2, Line 11: -- FIXME: check this There are no DP outputs, and only 2 HDMI outputs are used (1 for HDMI, 1 for DVI) File src/mainboard/asrock/z87_pro4/hda_verb.c: https://review.coreboot.org/c/coreboot/+/85756/comment/5521006f_276a1ff7?us… : PS2, Line 24: nit: remove blank line (this should probably be fixed in autoport) File src/mainboard/asrock/z87_pro4/romstage.c: https://review.coreboot.org/c/coreboot/+/85756/comment/083adc5e_53e7c89b?us… : PS2, Line 3: #include <stdint.h> This is probably not needed (and autoport should be updated to not add it) https://review.coreboot.org/c/coreboot/+/85756/comment/425bd4f4_fa548228?us… : PS2, Line 11: /* FIXME: called after romstage_common, remove it if not used */ : void mb_late_romstage_setup(void) : { : } 🧹 -- To view, visit https://review.coreboot.org/c/coreboot/+/85756?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2f01f2f25e0a4bcec10b075b574757250a5e5256 Gerrit-Change-Number: 85756 Gerrit-PatchSet: 2 Gerrit-Owner: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Máté Kukri <km(a)mkukri.xyz> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Máté Kukri <km(a)mkukri.xyz> Gerrit-Attention: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Tue, 24 Dec 2024 15:38:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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