coreboot-gerrit December 2024

coreboot-gerrit@coreboot.org

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[M] Change in coreboot[main]: mb/google/corsola: Add new board variant Wyrdeer
by Yu-Ping Wu (Code Review) 24 Dec '24

24 Dec '24

Attention is currently required from: Hung-Te Lin, Yang Wu, Yidi Lin. Yu-Ping Wu has posted comments on this change by Yang Wu. ( https://review.coreboot.org/c/coreboot/+/85742?usp=email ) Change subject: mb/google/corsola: Add new board variant Wyrdeer ...................................................................... Patch Set 5: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/85742?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I07b73c97d8d51b32f557e31d834ffc6cfb8420ed Gerrit-Change-Number: 85742 Gerrit-PatchSet: 5 Gerrit-Owner: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Xinxiong Xu <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Tue, 24 Dec 2024 12:45:10 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: mb/google/corsola: Add new board variant Wyrdeer
by Xinxiong Xu (Code Review) 24 Dec '24

24 Dec '24

Attention is currently required from: Hung-Te Lin, Yang Wu, Yidi Lin, Yu-Ping Wu. Xinxiong Xu has posted comments on this change by Yang Wu. ( https://review.coreboot.org/c/coreboot/+/85742?usp=email ) Change subject: mb/google/corsola: Add new board variant Wyrdeer ...................................................................... Patch Set 5: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/85742?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I07b73c97d8d51b32f557e31d834ffc6cfb8420ed Gerrit-Change-Number: 85742 Gerrit-PatchSet: 5 Gerrit-Owner: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Xinxiong Xu <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Tue, 24 Dec 2024 11:59:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: soc/mediatek/mt8196: Add MT6685 adc init
by Hope Wang (Code Review) 24 Dec '24

24 Dec '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yidi Lin, Yu-Ping Wu. Hope Wang has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85734?usp=email ) Change subject: soc/mediatek/mt8196: Add MT6685 adc init ...................................................................... Patch Set 4: (5 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/85734/comment/7fed76f0_8ce626a7?us… : PS3, Line 7: adc > We don't use ADC function on MT6685 and this patch does not implement ADC function, too. Actually configs MT6685 ADC SW initial setting here, TIA will read thermal info in HW. File src/soc/mediatek/common/mt6685.c: https://review.coreboot.org/c/coreboot/+/85734/comment/493f4ad5_962edf08?us… : PS3, Line 10: define MT6685_SLAVE_ID 0x9 > remove Done https://review.coreboot.org/c/coreboot/+/85734/comment/0be4ddba_95f90afe?us… : PS3, Line 31: MT6685_SLAVE_ID > SPMI_SLAVE_9 Done https://review.coreboot.org/c/coreboot/+/85734/comment/c9b67f7d_3884d4bb?us… : PS3, Line 59: wdata = mt6685_read_field(MT6685_TOP_RST_MISC, 0xFFFF, 0); : printk(BIOS_INFO, "[%s]MT6685 TOP_RST_MISC = %#x\n", __func__, wdata); > Why do we need to print the register content before setting ? Done https://review.coreboot.org/c/coreboot/+/85734/comment/744b1708_ee00689e?us… : PS3, Line 81: "[mt6685]CHIP ID = %#x\n", mt6685_read_field(0xb, 0xFF, 0) > "[%s][MT6685]CHIP ID = %#x\n", __func__, mt6685_read_field(0xb, 0xFF, 0) Done -- To view, visit https://review.coreboot.org/c/coreboot/+/85734?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I26ae4f416202f04a8030259c49e009b19a60712e Gerrit-Change-Number: 85734 Gerrit-PatchSet: 4 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Tue, 24 Dec 2024 11:32:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com>

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[XS] Change in coreboot[main]: soc/mediatek/mt8189: Enable timer compensation v2.5
by Yidi Lin (Code Review) 24 Dec '24

24 Dec '24

Yidi Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85689?usp=email ) Change subject: soc/mediatek/mt8189: Enable timer compensation v2.5 ...................................................................... soc/mediatek/mt8189: Enable timer compensation v2.5 Enable timer compensation v2.5 for MT8189 systimer. BUG=b:379008996 BRANCH=none TEST=Check SYSTIMER_BASE register is configurated correctly. Change-Id: I28c051c2e51481464f5dacb4c93f41e4f7e62501 Signed-off-by: Ke Zheng <ot_ke.zheng(a)mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85689 Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Reviewed-by: Yidi Lin <yidilin(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/mediatek/mt8189/Makefile.mk M src/soc/mediatek/mt8189/timer.c 2 files changed, 5 insertions(+), 2 deletions(-) Approvals: Yidi Lin: Looks good to me, approved build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/soc/mediatek/mt8189/Makefile.mk b/src/soc/mediatek/mt8189/Makefile.mk index 3dc16be..a121413 100644 --- a/src/soc/mediatek/mt8189/Makefile.mk +++ b/src/soc/mediatek/mt8189/Makefile.mk @@ -4,7 +4,7 @@ all-y += ../common/gpio.c ../common/gpio_op.c gpio.c all-$(CONFIG_SPI_FLASH) += spi.c -all-y += timer.c +all-y += ../common/timer_prepare.c timer.c all-y += ../common/uart.c bootblock-y += bootblock.c diff --git a/src/soc/mediatek/mt8189/timer.c b/src/soc/mediatek/mt8189/timer.c index c010d58..0d9776b 100644 --- a/src/soc/mediatek/mt8189/timer.c +++ b/src/soc/mediatek/mt8189/timer.c @@ -8,8 +8,11 @@ #include <arch/lib_helpers.h> #include <commonlib/helpers.h> #include <delay.h> +#include <soc/timer.h> void init_timer(void) { - raw_write_cntfrq_el0(13 * MHz); + timer_prepare(); + + raw_write_cntfrq_el0(TIMER_MHZ * MHz); } -- To view, visit https://review.coreboot.org/c/coreboot/+/85689?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I28c051c2e51481464f5dacb4c93f41e4f7e62501 Gerrit-Change-Number: 85689 Gerrit-PatchSet: 5 Gerrit-Owner: Vince Liu <vince-wl.liu(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[XS] Change in coreboot[main]: soc/mediatek/mt8189: Enable timer compensation v2.5
by Yidi Lin (Code Review) 24 Dec '24

24 Dec '24

Attention is currently required from: Hung-Te Lin, Paul Menzel, Vince Liu. Yidi Lin has posted comments on this change by Vince Liu. ( https://review.coreboot.org/c/coreboot/+/85689?usp=email ) Change subject: soc/mediatek/mt8189: Enable timer compensation v2.5 ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85689?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I28c051c2e51481464f5dacb4c93f41e4f7e62501 Gerrit-Change-Number: 85689 Gerrit-PatchSet: 4 Gerrit-Owner: Vince Liu <vince-wl.liu(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Vince Liu <vince-wl.liu(a)mediatek.com> Gerrit-Comment-Date: Tue, 24 Dec 2024 11:22:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: soc/mediatek/mt8196: Define MFGPLL_*_BASE using MFGSYS_BASE
by Yidi Lin (Code Review) 24 Dec '24

24 Dec '24

Yidi Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85740?usp=email ) Change subject: soc/mediatek/mt8196: Define MFGPLL_*_BASE using MFGSYS_BASE ...................................................................... soc/mediatek/mt8196: Define MFGPLL_*_BASE using MFGSYS_BASE The MFGPLL_*_BASE addresses are based on MFGSYS_BASE (0x40000000) instead of IO_PHYS (0x10000000). Rewrite the address calculation for readability. Also rename these macros to MFG_PLL_* to make them consistent with other macros to be added in CB:85654. Change-Id: Ifd5d77b95c698cb6030c58ba259f2cdf2a29d87b Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85740 Reviewed-by: Yidi Lin <yidilin(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/mediatek/mt8196/include/soc/addressmap.h M src/soc/mediatek/mt8196/include/soc/pll.h 2 files changed, 6 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Yidi Lin: Looks good to me, approved diff --git a/src/soc/mediatek/mt8196/include/soc/addressmap.h b/src/soc/mediatek/mt8196/include/soc/addressmap.h index 96efa40..8d0a4bb 100644 --- a/src/soc/mediatek/mt8196/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8196/include/soc/addressmap.h @@ -191,9 +191,9 @@ OVLSYS1_CONFIG_BASE = IO_PHYS + 0x22C00000, DISP_VDISP_AO_CONFIG_BASE = IO_PHYS + 0x2E800000, EDP_BASE = IO_PHYS + 0x2EC40000, - MFGPLL_PLL_CTRL_BASE = IO_PHYS + 0x3B810000, - MFGPLL_SC0_PLL_CTRL_BASE = IO_PHYS + 0x3B810400, - MFGPLL_SC1_PLL_CTRL_BASE = IO_PHYS + 0x3B810800, + MFG_PLL_PLL_CTRL_BASE = MFGSYS_BASE + 0x0B810000, + MFG_PLL_SC0_PLL_CTRL_BASE = MFGSYS_BASE + 0x0B810400, + MFG_PLL_SC1_PLL_CTRL_BASE = MFGSYS_BASE + 0x0B810800, }; #endif diff --git a/src/soc/mediatek/mt8196/include/soc/pll.h b/src/soc/mediatek/mt8196/include/soc/pll.h index 6c4a976..e95434e 100644 --- a/src/soc/mediatek/mt8196/include/soc/pll.h +++ b/src/soc/mediatek/mt8196/include/soc/pll.h @@ -50,11 +50,11 @@ static struct mtk_dispsys_regs *const mtk_disp = (void *)DISP_VDISP_AO_CONFIG_BASE; static struct mtk_mfgpll_regs *const - mtk_mfgpll = (void *)MFGPLL_PLL_CTRL_BASE; + mtk_mfgpll = (void *)MFG_PLL_PLL_CTRL_BASE; static struct mtk_mfgpll_regs *const - mtk_mfgpll_sc0 = (void *)MFGPLL_SC0_PLL_CTRL_BASE; + mtk_mfgpll_sc0 = (void *)MFG_PLL_SC0_PLL_CTRL_BASE; static struct mtk_mfgpll_regs *const - mtk_mfgpll_sc1 = (void *)MFGPLL_SC1_PLL_CTRL_BASE; + mtk_mfgpll_sc1 = (void *)MFG_PLL_SC1_PLL_CTRL_BASE; static struct mtk_mcupll_regs *const mtk_ccipll = (void *)CCIPLL_PLL_CTRL_BASE; static struct mtk_mcupll_regs *const -- To view, visit https://review.coreboot.org/c/coreboot/+/85740?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifd5d77b95c698cb6030c58ba259f2cdf2a29d87b Gerrit-Change-Number: 85740 Gerrit-PatchSet: 4 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: mb/google/corsola: refactor mipi_panel_power_on function
by Yidi Lin (Code Review) 24 Dec '24

24 Dec '24

Attention is currently required from: Hung-Te Lin, Xinxiong Xu, Yang Wu. Yidi Lin has posted comments on this change by Yang Wu. ( https://review.coreboot.org/c/coreboot/+/85745?usp=email ) Change subject: mb/google/corsola: refactor mipi_panel_power_on function ...................................................................... Patch Set 6: (1 comment) File src/mainboard/google/corsola/panel_starmie.c: https://review.coreboot.org/c/coreboot/+/85745/comment/bf768efe_ff3cc37e?us… : PS6, Line 4: #include <delay.h> : #include <gpio.h> : #include <soc/regulator.h> unused includes ? -- To view, visit https://review.coreboot.org/c/coreboot/+/85745?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic0561e57d99ab55e6dcbb7744b2228c4cebb0d88 Gerrit-Change-Number: 85745 Gerrit-PatchSet: 6 Gerrit-Owner: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Xinxiong Xu <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Xinxiong Xu <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Tue, 24 Dec 2024 11:21:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[L] Change in coreboot[main]: mb/amd/crater: Add Crater mainboard support for Renoir/Cezanne SOC
by Anand Vaikar (Code Review) 24 Dec '24

24 Dec '24

Attention is currently required from: Anand Vaikar, Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier. Hello Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85749?usp=email to look at the new patch set (#5). Change subject: mb/amd/crater: Add Crater mainboard support for Renoir/Cezanne SOC ...................................................................... mb/amd/crater: Add Crater mainboard support for Renoir/Cezanne SOC 1) Initial commit for crater mainboard changes for RN/CZ SOC 2) Add the initial DXIO descriptors for crater 3) Add the DDI descriptors for crater 4) GPIO changes for crater mainboard TEST:Build crater mainboard changes with cezanne SOC Change-Id: Ibdb276fc160326c666d5990e34de5327813d9403 Signed-off-by: Anand Vaikar <a.vaikar2021(a)gmail.com> --- A src/mainboard/amd/crater/Kconfig A src/mainboard/amd/crater/Kconfig.name A src/mainboard/amd/crater/Makefile.mk A src/mainboard/amd/crater/board_info.txt A src/mainboard/amd/crater/board_renoir.fmd A src/mainboard/amd/crater/bootblock.c A src/mainboard/amd/crater/chromeos.c A src/mainboard/amd/crater/chromeos_renoir.fmd A src/mainboard/amd/crater/devicetree_renoir.cb A src/mainboard/amd/crater/dsdt.asl A src/mainboard/amd/crater/early_gpio.c A src/mainboard/amd/crater/ec.c A src/mainboard/amd/crater/ec.h A src/mainboard/amd/crater/gpio.c A src/mainboard/amd/crater/gpio.h A src/mainboard/amd/crater/mainboard.c A src/mainboard/amd/crater/port_descriptors_renoir.c M src/soc/amd/cezanne/chip.h M src/soc/amd/cezanne/include/soc/gpio.h 19 files changed, 940 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/85749/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/85749?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibdb276fc160326c666d5990e34de5327813d9403 Gerrit-Change-Number: 85749 Gerrit-PatchSet: 5 Gerrit-Owner: Anand Vaikar <a.vaikar2021(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Anand Vaikar <a.vaikar2021(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

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[M] Change in coreboot[main]: mb/google/corsola: refactor mipi_panel_power_on function
by Yidi Lin (Code Review) 24 Dec '24

24 Dec '24

Attention is currently required from: Hung-Te Lin, Xinxiong Xu, Yang Wu. Yidi Lin has posted comments on this change by Yang Wu. ( https://review.coreboot.org/c/coreboot/+/85745?usp=email ) Change subject: mb/google/corsola: refactor mipi_panel_power_on function ...................................................................... Patch Set 6: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/85745?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic0561e57d99ab55e6dcbb7744b2228c4cebb0d88 Gerrit-Change-Number: 85745 Gerrit-PatchSet: 6 Gerrit-Owner: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Xinxiong Xu <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Xinxiong Xu <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Tue, 24 Dec 2024 11:19:46 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: mb/google/rauru: Implement SKU ID
by Yidi Lin (Code Review) 24 Dec '24

24 Dec '24

Yidi Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85666?usp=email ) Change subject: mb/google/rauru: Implement SKU ID ...................................................................... mb/google/rauru: Implement SKU ID Retrieve the SKU ID for Rauru via CBI interface. If that failed (or no data found), fall back to ADC channels for SKU ID. TEST=Build pass, boot ok, log show: SKU Code: 0x2 BUG=b:317009620 Change-Id: I49ba6f428f55d3aae1b84a4d5ce06bec765caece Signed-off-by: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85666 Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yidi Lin <yidilin(a)google.com> --- M src/mainboard/google/rauru/Kconfig M src/mainboard/google/rauru/boardid.c 2 files changed, 25 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved Yidi Lin: Looks good to me, approved diff --git a/src/mainboard/google/rauru/Kconfig b/src/mainboard/google/rauru/Kconfig index 18a1699..57e8c1b 100644 --- a/src/mainboard/google/rauru/Kconfig +++ b/src/mainboard/google/rauru/Kconfig @@ -26,6 +26,7 @@ select CHROMEOS_USE_EC_WATCHDOG_FLAG if CHROMEOS select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_BOARDID + select EC_GOOGLE_CHROMEEC_SKUID select EC_GOOGLE_CHROMEEC_SPI select I2C_TPM if VBOOT select MAINBOARD_HAS_TPM2 if VBOOT diff --git a/src/mainboard/google/rauru/boardid.c b/src/mainboard/google/rauru/boardid.c index 1d49e03..e3e0979 100644 --- a/src/mainboard/google/rauru/boardid.c +++ b/src/mainboard/google/rauru/boardid.c @@ -3,6 +3,7 @@ #include <assert.h> #include <boardid.h> #include <console/console.h> +#include <device/mmio.h> #include <ec/google/chromeec/ec.h> #include <soc/mt6363_sdmadc.h> @@ -10,6 +11,10 @@ #define ADC_LEVELS 8 +DEFINE_BITFIELD(STORAGE_TYPE, 11, 9); +DEFINE_BITFIELD(CPU_TYPE, 8, 8); +DEFINE_BITFIELD(PANEL_TYPE, 7, 0); + enum { /* Storage IDs */ STORAGE_ID_LOW_CHANNEL = AUXADC_CHAN_VIN1, @@ -75,3 +80,22 @@ } return UFS_UNKNOWN; } + +uint32_t sku_id(void) +{ + static uint32_t cached_sku_code = BOARD_ID_INIT; + + if (cached_sku_code == BOARD_ID_INIT) { + cached_sku_code = google_chromeec_get_board_sku(); + + if (cached_sku_code == CROS_SKU_UNKNOWN || + cached_sku_code == CROS_SKU_UNPROVISIONED) { + printk(BIOS_WARNING, "Failed to get SKU code from EC\n"); + cached_sku_code = CROS_SKU_UNPROVISIONED; + SET32_BITFIELDS(&cached_sku_code, STORAGE_TYPE, storage_id()); + } + printk(BIOS_DEBUG, "SKU Code: %#02x\n", cached_sku_code); + } + + return cached_sku_code; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/85666?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I49ba6f428f55d3aae1b84a4d5ce06bec765caece Gerrit-Change-Number: 85666 Gerrit-PatchSet: 14 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Knox Chiou <knoxchiou(a)google.com>

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coreboot-gerrit December 2024