coreboot-gerrit December 2024

coreboot-gerrit@coreboot.org

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[M] Change in coreboot[main]: soc/mediatek/mt8196: Add MT6685 adc init
by Yidi Lin (Code Review) 24 Dec '24

24 Dec '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yu-Ping Wu. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85734?usp=email ) Change subject: soc/mediatek/mt8196: Add MT6685 adc init ...................................................................... Patch Set 3: Code-Review+1 (5 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/85734/comment/f239ca32_4c9628e8?us… : PS3, Line 7: adc We don't use ADC function on MT6685 and this patch does not implement ADC function, too. File src/soc/mediatek/common/mt6685.c: https://review.coreboot.org/c/coreboot/+/85734/comment/197b69f2_ca4c1475?us… : PS3, Line 10: define MT6685_SLAVE_ID 0x9 remove https://review.coreboot.org/c/coreboot/+/85734/comment/9024633f_b6146e5e?us… : PS3, Line 31: MT6685_SLAVE_ID SPMI_SLAVE_9 https://review.coreboot.org/c/coreboot/+/85734/comment/f6fdbfeb_7d2f48d2?us… : PS3, Line 59: wdata = mt6685_read_field(MT6685_TOP_RST_MISC, 0xFFFF, 0); : printk(BIOS_INFO, "[%s]MT6685 TOP_RST_MISC = %#x\n", __func__, wdata); Why do we need to print the register content before setting ? https://review.coreboot.org/c/coreboot/+/85734/comment/48f9e992_465b1755?us… : PS3, Line 81: "[mt6685]CHIP ID = %#x\n", mt6685_read_field(0xb, 0xFF, 0) "[%s][MT6685]CHIP ID = %#x\n", __func__, mt6685_read_field(0xb, 0xFF, 0) -- To view, visit https://review.coreboot.org/c/coreboot/+/85734?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I26ae4f416202f04a8030259c49e009b19a60712e Gerrit-Change-Number: 85734 Gerrit-PatchSet: 3 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Tue, 24 Dec 2024 08:57:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: soc/mediatek/mt8196: Set SPMI-P SCL/SDA SoC PD
by Yidi Lin (Code Review) 24 Dec '24

24 Dec '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yu-Ping Wu. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85751?usp=email ) Change subject: soc/mediatek/mt8196: Set SPMI-P SCL/SDA SoC PD ...................................................................... Patch Set 1: (2 comments) File src/soc/mediatek/mt8196/pmif_spmi.c: https://review.coreboot.org/c/coreboot/+/85751/comment/24aef166_cf8cd70a?us… : PS1, Line 178: setbits32p(SPMI_SCL_P_PD_ADDR, : BIT(SPMI_SCL_P_PD_OFFSET) | BIT(SPMI_SDA_P_PD_OFFSET)); This is identical to ``` gpio_set_pull(GPIO(SPMI_P_SCL), GPIO_PULL_ENABLE, GPIO_PULL_DOWN); gpio_set_pull(GPIO(SPMI_P_SCA), GPIO_PULL_ENABLE, GPIO_PULL_DOWN); ``` https://review.coreboot.org/c/coreboot/+/85751/comment/e9c3e825_69d4e489?us… : PS1, Line 177: if (dev->slvid == SPMI_SLAVE_6) { : setbits32p(SPMI_SCL_P_PD_ADDR, : BIT(SPMI_SCL_P_PD_OFFSET) | BIT(SPMI_SDA_P_PD_OFFSET)); : printk(BIOS_INFO, "%s, Set SoC PD for SPMI-P SCL/SDA, [0x%x] = 0x%x\n", : __func__, SPMI_SCL_P_PD_ADDR, read32p(SPMI_SCL_P_PD_ADDR)); : } This setting also effects other slaves, right ? Should we revert the setting for other slaves ? Please elaborate in a comment or the commit message. -- To view, visit https://review.coreboot.org/c/coreboot/+/85751?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idbf8ed8e31850ca81c823db1b25bde4a83a48c4f Gerrit-Change-Number: 85751 Gerrit-PatchSet: 1 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Tue, 24 Dec 2024 08:41:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: soc/mediatek/mt8196: Add MT6685 adc init
by Hope Wang (Code Review) 24 Dec '24

24 Dec '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yidi Lin, Yu-Ping Wu. Hope Wang has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85734?usp=email ) Change subject: soc/mediatek/mt8196: Add MT6685 adc init ...................................................................... Patch Set 3: (1 comment) Patchset: PS2: > Please follow MT6316 coding style and review comment. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/85734?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I26ae4f416202f04a8030259c49e009b19a60712e Gerrit-Change-Number: 85734 Gerrit-PatchSet: 3 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Tue, 24 Dec 2024 08:38:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com>

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[M] Change in coreboot[main]: soc/mediatek/mt8196: Add MT6685 adc init
by Jarried Lin (Code Review) 24 Dec '24

24 Dec '24

Attention is currently required from: Hope Wang, Hung-Te Lin, Jarried Lin, Yu-Ping Wu. Hello Hope Wang, Hung-Te Lin, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85734?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/mediatek/mt8196: Add MT6685 adc init ...................................................................... soc/mediatek/mt8196: Add MT6685 adc init Add MT6685 adc init. TEST=Build pass BUG=b:317009620 Change-Id: I26ae4f416202f04a8030259c49e009b19a60712e Signed-off-by: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> --- A src/soc/mediatek/common/include/soc/mt6685_adc_init.h A src/soc/mediatek/common/mt6685.c M src/soc/mediatek/mt8196/Makefile.mk A src/soc/mediatek/mt8196/mt6685.c M src/soc/mediatek/mt8196/pmif_init.c 5 files changed, 184 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/85734/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/85734?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I26ae4f416202f04a8030259c49e009b19a60712e Gerrit-Change-Number: 85734 Gerrit-PatchSet: 3 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com>

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[S] Change in coreboot[main]: soc/mediatek/mt8196: Set SPMI-P SCL/SDA SoC PD
by Jarried Lin (Code Review) 24 Dec '24

24 Dec '24

Attention is currently required from: Hung-Te Lin, Yidi Lin, Yu-Ping Wu. Hello Hope Wang, Hung-Te Lin, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85751?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/mediatek/mt8196: Set SPMI-P SCL/SDA SoC PD ...................................................................... soc/mediatek/mt8196: Set SPMI-P SCL/SDA SoC PD Configure the SCL and SDA of the SPMI-P to Pull-Down mode on MT8196 SoC, to fix spmi clk calibration failure. TEST=Build pass BUG=b:361174333 Change-Id: Idbf8ed8e31850ca81c823db1b25bde4a83a48c4f Signed-off-by: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> --- M src/soc/mediatek/mt8196/include/soc/pmif.h M src/soc/mediatek/mt8196/pmif_spmi.c 2 files changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/85751/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85751?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idbf8ed8e31850ca81c823db1b25bde4a83a48c4f Gerrit-Change-Number: 85751 Gerrit-PatchSet: 2 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com>

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[S] Change in coreboot[main]: mb/google/nissa/var/telith: Disable stylus function
by Kun Liu (Code Review) 24 Dec '24

24 Dec '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Nick Vaccaro. Kun Liu has posted comments on this change by Kun Liu. ( https://review.coreboot.org/c/coreboot/+/85738?usp=email ) Change subject: mb/google/nissa/var/telith: Disable stylus function ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/85738/comment/2eba2337_c34ba9df?us… : PS3, Line 7: Disable > disable or remove the stylus from this project? yes， remove the stylus from this project. -- To view, visit https://review.coreboot.org/c/coreboot/+/85738?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7b72284ab173633405d5de9541f0ea7520d09658 Gerrit-Change-Number: 85738 Gerrit-PatchSet: 3 Gerrit-Owner: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Tue, 24 Dec 2024 08:24:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Eric Lai <ericllai(a)google.com>

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[S] Change in coreboot[main]: tree: Switch to C23 dialect
by Elyes Haouas (Code Review) 24 Dec '24

24 Dec '24

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85748?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: tree: Switch to C23 dialect ...................................................................... tree: Switch to C23 dialect Change-Id: I42c0b3769f0c6e5c2261b9084e229c35576a832d Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M Makefile.mk M payloads/libpayload/Makefile M util/cbfstool/Makefile.mk M util/superiotool/Makefile 4 files changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/85748/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/85748?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I42c0b3769f0c6e5c2261b9084e229c35576a832d Gerrit-Change-Number: 85748 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: soc/mediatek/mt8196: Set SPMI-P SCL/SDA SoC PD
by Jarried Lin (Code Review) 24 Dec '24

24 Dec '24

Attention is currently required from: Hope Wang. Hello Hope Wang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/85751?usp=email to review the following change. Change subject: soc/mediatek/mt8196: Set SPMI-P SCL/SDA SoC PD ...................................................................... soc/mediatek/mt8196: Set SPMI-P SCL/SDA SoC PD Configure the SCL and SDA of the SPMI-P to Pull-Down mode on MT8196 SoC, to fix spmi clk calibration failure. TEST=Build pass BUG=b:361174333 Change-Id: Idbf8ed8e31850ca81c823db1b25bde4a83a48c4f Signed-off-by: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> --- M src/soc/mediatek/mt8196/include/soc/pmif.h M src/soc/mediatek/mt8196/pmif_spmi.c 2 files changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/85751/1 diff --git a/src/soc/mediatek/mt8196/include/soc/pmif.h b/src/soc/mediatek/mt8196/include/soc/pmif.h index a114dc6..189ee2a 100644 --- a/src/soc/mediatek/mt8196/include/soc/pmif.h +++ b/src/soc/mediatek/mt8196/include/soc/pmif.h @@ -4,6 +4,7 @@ #define __MT8196_SOC_PMIF_H__ #include <device/mmio.h> +#include <soc/addressmap.h> #include <soc/pmif_common.h> #include <types.h> @@ -138,6 +139,10 @@ #define FREQ_METER_VLP_AD_OSC_CK 59 #define PMIF_USE_FIX_26M_CLK 0 +#define SPMI_SCL_P_PD_ADDR (IOCFG_LM2_BASE+0x80) +#define SPMI_SCL_P_PD_OFFSET 4 +#define SPMI_SDA_P_PD_OFFSET 5 + /* calibation tolerance rate, unit: 0.1% */ enum { CAL_TOL_RATE = 40, diff --git a/src/soc/mediatek/mt8196/pmif_spmi.c b/src/soc/mediatek/mt8196/pmif_spmi.c index 91f9038..aea0730 100644 --- a/src/soc/mediatek/mt8196/pmif_spmi.c +++ b/src/soc/mediatek/mt8196/pmif_spmi.c @@ -174,6 +174,13 @@ { u32 rdata = 0; + if (dev->slvid == SPMI_SLAVE_6) { + setbits32p(SPMI_SCL_P_PD_ADDR, + BIT(SPMI_SCL_P_PD_OFFSET) | BIT(SPMI_SDA_P_PD_OFFSET)); + printk(BIOS_INFO, "%s, Set SoC PD for SPMI-P SCL/SDA, [0x%x] = 0x%x\n", + __func__, SPMI_SCL_P_PD_ADDR, read32p(SPMI_SCL_P_PD_ADDR)); + } + arb->read(arb, dev->slvid, dev->hwcid_addr, &rdata); if ((rdata & dev->hwcid_mask) != (dev->hwcid_val & dev->hwcid_mask)) { printk(BIOS_WARNING, "%s next, slvid:%d rdata = 0x%x\n", -- To view, visit https://review.coreboot.org/c/coreboot/+/85751?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idbf8ed8e31850ca81c823db1b25bde4a83a48c4f Gerrit-Change-Number: 85751 Gerrit-PatchSet: 1 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com>

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[L] Change in coreboot[main]: mb/amd/crater: Add Crater mainboard support for Renoir/Cezanne SOC
by Anand Vaikar (Code Review) 24 Dec '24

24 Dec '24

Attention is currently required from: Anand Vaikar, Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier. Hello Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85749?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: mb/amd/crater: Add Crater mainboard support for Renoir/Cezanne SOC ...................................................................... mb/amd/crater: Add Crater mainboard support for Renoir/Cezanne SOC 1) Initial commit for crater mainboard changes for RN/CZ SOC 2) Add the initial DXIO descriptors for crater 3) Add the DDI descriptors for crater 4) GPIO changes for crater mainboard TEST:Build crater mainboard changes with cezanne SOC Change-Id: Ibdb276fc160326c666d5990e34de5327813d9403 Signed-off-by: Anand Vaikar <a.vaikar2021(a)gmail.com> --- A src/mainboard/amd/crater/Kconfig A src/mainboard/amd/crater/Kconfig.name A src/mainboard/amd/crater/Makefile.mk A src/mainboard/amd/crater/board_info.txt A src/mainboard/amd/crater/board_renoir.fmd A src/mainboard/amd/crater/bootblock.c A src/mainboard/amd/crater/chromeos.c A src/mainboard/amd/crater/chromeos_renoir.fmd A src/mainboard/amd/crater/devicetree_renoir.cb A src/mainboard/amd/crater/dsdt.asl A src/mainboard/amd/crater/early_gpio.c A src/mainboard/amd/crater/ec.c A src/mainboard/amd/crater/ec.h A src/mainboard/amd/crater/gpio.c A src/mainboard/amd/crater/gpio.h A src/mainboard/amd/crater/mainboard.c A src/mainboard/amd/crater/port_descriptors_renoir.c M src/soc/amd/cezanne/chip.h M src/soc/amd/cezanne/include/soc/gpio.h 19 files changed, 939 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/85749/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85749?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibdb276fc160326c666d5990e34de5327813d9403 Gerrit-Change-Number: 85749 Gerrit-PatchSet: 2 Gerrit-Owner: Anand Vaikar <a.vaikar2021(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Anand Vaikar <a.vaikar2021(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

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[S] Change in coreboot[main]: mb/google/fatcat/var/francka: Fix early pad configuration for TPM
by Subrata Banik (Code Review) 24 Dec '24

24 Dec '24

Attention is currently required from: Dtrain Hsu, Ian Feng. Subrata Banik has posted comments on this change by Ian Feng. ( https://review.coreboot.org/c/coreboot/+/85736?usp=email ) Change subject: mb/google/fatcat/var/francka: Fix early pad configuration for TPM ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85736?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id08575d28f6f3bced74c0b301756fc8239cfd190 Gerrit-Change-Number: 85736 Gerrit-PatchSet: 4 Gerrit-Owner: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Attention: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Tue, 24 Dec 2024 07:11:51 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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coreboot-gerrit December 2024