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[L] Change in coreboot[main]: mb/amd/crater: Add Crater mainboard support for Renoir/Cezanne SOC
by Anand Vaikar (Code Review) 24 Dec '24

24 Dec '24

Anand Vaikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85749?usp=email ) Change subject: mb/amd/crater: Add Crater mainboard support for Renoir/Cezanne SOC ...................................................................... mb/amd/crater: Add Crater mainboard support for Renoir/Cezanne SOC 1) Initial commit for crater mainboard changes for RN/CZ SOC 2) Add the initial DXIO descriptors for crater 3) Add the DDI descriptors for crater 4) GPIO changes for crater mainboard TEST:Build crater mainboard changes with cezanne SOC Change-Id: Ibdb276fc160326c666d5990e34de5327813d9403 Signed-off-by: Anand Vaikar <a.vaikar2021(a)gmail.com> --- A src/mainboard/amd/crater/Kconfig A src/mainboard/amd/crater/Kconfig.name A src/mainboard/amd/crater/Makefile.mk A src/mainboard/amd/crater/board_info.txt A src/mainboard/amd/crater/board_renoir.fmd A src/mainboard/amd/crater/bootblock.c A src/mainboard/amd/crater/chromeos.c A src/mainboard/amd/crater/chromeos_renoir.fmd A src/mainboard/amd/crater/devicetree_renoir.cb A src/mainboard/amd/crater/dsdt.asl A src/mainboard/amd/crater/early_gpio.c A src/mainboard/amd/crater/ec.c A src/mainboard/amd/crater/ec.h A src/mainboard/amd/crater/gpio.c A src/mainboard/amd/crater/gpio.h A src/mainboard/amd/crater/mainboard.c A src/mainboard/amd/crater/port_descriptors_renoir.c M src/soc/amd/cezanne/chip.h M src/soc/amd/cezanne/include/soc/gpio.h 19 files changed, 940 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/85749/1 diff --git a/src/mainboard/amd/crater/Kconfig b/src/mainboard/amd/crater/Kconfig new file mode 100644 index 0000000..55048fd --- /dev/null +++ b/src/mainboard/amd/crater/Kconfig @@ -0,0 +1,140 @@ +# SPDX-License-Identifier: GPL-2.0-only + +config BOARD_AMD_CRATER_COMMON + def_bool n + select BOARD_ROMSIZE_KB_16384 # Birman actually has a 32MiB ROM + select EC_ACPI + select SOC_AMD_COMMON_BLOCK_USE_ESPI if !SOC_AMD_COMMON_BLOCK_SIMNOW_BUILD + select DRIVERS_PCIE_RTD3_DEVICE + select MAINBOARD_HAS_CHROMEOS + select HAVE_ACPI_RESUME + select PCIEXP_ASPM + select PCIEXP_CLK_PM + select PCIEXP_COMMON_CLOCK + select PCIEXP_L1_SUB_STATE + select SOC_AMD_COMMON_BLOCK_ESPI_RETAIN_PORT80_EN if !SOC_AMD_COMMON_BLOCK_SIMNOW_BUILD + select SOC_AMD_COMMON_BLOCK_SIMNOW_SUPPORTED + select SPI_FLASH_EXIT_4_BYTE_ADDR_MODE + select SOC_AMD_COMMON_BLOCK_PSP_RPMC + select SOC_AMD_COMMON_BLOCK_PSP_SMI + + +config BOARD_AMD_CRATER_RENOIR + select BOARD_AMD_CRATER_COMMON + select SOC_AMD_CEZANNE + +if BOARD_AMD_CRATER_RENOIR + +config FMDFILE + default "src/mainboard/amd/crater/chromeos_renoir.fmd" if CHROMEOS && BOARD_AMD_CRATER_RENOIR + +config MAINBOARD_DIR + default "amd/crater" if BOARD_AMD_CRATER_RENOIR + +config MAINBOARD_PART_NUMBER + default "Crater_RENOIR" if BOARD_AMD_CRATER_RENOIR + + +config DEVICETREE + default "devicetree_renoir.cb" if BOARD_AMD_CRATER_RENOIR + +config CRATER_HAVE_MCHP_FW + bool "Have Microchip EC firmware?" + default n + +config CRATER_MCHP_SIG_FILE + string "Microchip EC signature file" + depends on CRATER_HAVE_MCHP_FW + default "3rdparty/blobs/mainboard/amd/crater/EC_birmanplus_sig.bin" + help + The EC sig blob is the first 4kBytes of the firmware image. + The first 4 bytes form a pointer (with CRC) to where the EC firmware + is located + +config AMD_SOC_CONSOLE_UART + default y if !SOC_AMD_COMMON_BLOCK_SIMNOW_BUILD + +config CRATER_MCHP_FW_FILE + string "Microchip EC firmware file" + depends on CRATER_HAVE_MCHP_FW + default "3rdparty/blobs/mainboard/amd/crater/EC_birmanplus.bin" + help + The EC firmware blob is at the EC_BODY FMAP region of the firmware image. + +config VBOOT + select VBOOT_NO_BOARD_SUPPORT + select VBOOT_SEPARATE_VERSTAGE + select VBOOT_STARTS_IN_BOOTBLOCK + +config VBOOT_VBNV_OFFSET + hex + default 0x2A + +config RO_REGION_ONLY + string + depends on VBOOT_SLOTS_RW_AB || VBOOT_SLOTS_RW_A + # Add the EFS and EC to the RO region only + # This is a birmanplus specific override of soc/amd/(phoenix | glinda)/Kconfig + default "apu/amdfw apu/ecfw" + +config CHROMEOS + # Use default libpayload config + select LP_DEFCONFIG_OVERRIDE if PAYLOAD_DEPTHCHARGE + # We don't have recovery buttons, so we can't manually enable devmode. + select GBB_FLAG_FORCE_DEV_SWITCH_ON + + +config ENABLE_EDP + bool "Enable EDP display" + default n + help + Select this option to enable EDP display on DDI1 interface + +config ENABLE_EVAL_CARD + bool "Enable Eval Card" + help + Enable the Eval Card PCIe slot + +config ENABLE_EVAL_19V + bool "Enable 19V rail for Eval Card" + depends on ENABLE_EVAL_CARD + help + Enable the 19V rail for Eval Card PCIe slot + +choice + prompt "I2C Speed Selection" + default SELECT_400KHz + help + Select Different speeds of I2C 400KHz / 1 MHz + +config SELECT_400KHz + bool "400KHz" + +config SELECT_1MHz + bool "1MHz" + +endchoice + + +if !EM100 # EM100 defaults in soc/amd/common/blocks/spi/Kconfig +config EFS_SPI_READ_MODE + default 3 # Quad IO (1-1-4) + +config EFS_SPI_SPEED + default 0 # 66MHz + +config EFS_SPI_MICRON_FLAG + default 0 + +config NORMAL_READ_SPI_SPEED + default 1 # 33MHz + +config ALT_SPI_SPEED + default 1 # 33MHz + +config TPM_SPI_SPEED + default 1 # 33MHz + +endif # !EM100 + +endif # BOARD_AMD_BIRMANPLUS_COMMON diff --git a/src/mainboard/amd/crater/Kconfig.name b/src/mainboard/amd/crater/Kconfig.name new file mode 100644 index 0000000..8190008 --- /dev/null +++ b/src/mainboard/amd/crater/Kconfig.name @@ -0,0 +1,5 @@ +comment "Crater" + +config BOARD_AMD_CRATER_RENOIR + bool "-> Crater for RENOIR SoC" + diff --git a/src/mainboard/amd/crater/Makefile.mk b/src/mainboard/amd/crater/Makefile.mk new file mode 100644 index 0000000..dc169f1 --- /dev/null +++ b/src/mainboard/amd/crater/Makefile.mk @@ -0,0 +1,34 @@ +# SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += bootblock.c +bootblock-y += early_gpio.c +bootblock-y += ec.c + +romstage-$(CONFIG_BOARD_AMD_CRATER_RENOIR) += port_descriptors_renoir.c + +ramstage-y += chromeos.c +ramstage-y += gpio.c +ramstage-$(CONFIG_BOARD_AMD_CRATER_RENOIR) += port_descriptors_renoir.c + +ifneq ($(wildcard $(MAINBOARD_BLOBS_DIR)/APCB_RN_D4_Updatable.bin),) +APCB_SOURCES = $(MAINBOARD_BLOBS_DIR)/APCB_RN_D4_Updatable.bin +APCB_SOURCES_RECOVERY = $(MAINBOARD_BLOBS_DIR)/APCB_RN_D4_DefaultRecovery.bin +else +show_notices:: warn_no_apcb +endif + +ifeq ($(CONFIG_CRATER_HAVE_MCHP_FW),y) +$(call add_intermediate, add_mchp_fw) + $(CBFSTOOL) $(obj)/coreboot.pre write -r EC_SIG -f $(CONFIG_CRATER_MCHP_SIG_FILE) --fill-upward + $(CBFSTOOL) $(obj)/coreboot.pre write -r EC_BODY -f $(CONFIG_CRATER_MCHP_FW_FILE) --fill-upward + +else +show_notices:: warn_no_mchp +endif + +PHONY+=warn_no_mchp +warn_no_mchp: + printf "\n\t** WARNING **\n" + printf "coreboot has been built without the EC FW.\n" + printf "Do not flash this image. Your Crater's power button\n" + printf "will not respond when you press it.\n\n" diff --git a/src/mainboard/amd/crater/board_info.txt b/src/mainboard/amd/crater/board_info.txt new file mode 100644 index 0000000..b351b8e --- /dev/null +++ b/src/mainboard/amd/crater/board_info.txt @@ -0,0 +1 @@ +Category: eval diff --git a/src/mainboard/amd/crater/board_renoir.fmd b/src/mainboard/amd/crater/board_renoir.fmd new file mode 100644 index 0000000..a66e97b --- /dev/null +++ b/src/mainboard/amd/crater/board_renoir.fmd @@ -0,0 +1,11 @@ +FLASH@0xFF000000 16M { + BIOS { + EC_SIG 4K + FMAP 4K + COREBOOT(CBFS) + PSP_NVRAM(PRESERVE) 128K + PSP_RPMC_NVRAM(PRESERVE) 256K + EC_BODY@15872K 256K + RW_MRC_CACHE 120K + } +} diff --git a/src/mainboard/amd/crater/bootblock.c b/src/mainboard/amd/crater/bootblock.c new file mode 100644 index 0000000..58ef0ba --- /dev/null +++ b/src/mainboard/amd/crater/bootblock.c @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include <soc/espi.h> +#include "ec.h" +#include "gpio.h" + +void bootblock_mainboard_early_init(void) +{ + mainboard_program_early_gpios(); + + espi_switch_to_spi2_pads(); +} + +void bootblock_mainboard_init(void) +{ + if (!CONFIG(SOC_AMD_COMMON_BLOCK_SIMNOW_BUILD)) + crater_ec_init(); +} diff --git a/src/mainboard/amd/crater/chromeos.c b/src/mainboard/amd/crater/chromeos.c new file mode 100644 index 0000000..515da94 --- /dev/null +++ b/src/mainboard/amd/crater/chromeos.c @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <bootmode.h> +#include <boot/coreboot_tables.h> +#include <gpio.h> +#include <types.h> +#include <vendorcode/google/chromeos/chromeos.h> + +void fill_lb_gpios(struct lb_gpios *gpios) +{ + struct lb_gpio chromeos_gpios[] = {}; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); +} + +int get_write_protect_state(void) +{ + /* Birman doesn't have a write protect pin */ + return 0; +} + +DECLARE_NO_CROS_GPIOS(); diff --git a/src/mainboard/amd/crater/chromeos_renoir.fmd b/src/mainboard/amd/crater/chromeos_renoir.fmd new file mode 100644 index 0000000..66227c2 --- /dev/null +++ b/src/mainboard/amd/crater/chromeos_renoir.fmd @@ -0,0 +1,35 @@ +FLASH@0xFF000000 16M { + SI_BIOS { + WP_RO 8M { + EC_SIG 4K + RO_VPD(PRESERVE) 16K + RO_SECTION { + FMAP 2K + RO_FRID 64 + COREBOOT(CBFS) + GBB 448K + } + } + RW_SECTION_A 3M { + VBLOCK_A 8K + FW_MAIN_A(CBFS) + RW_FWID_A 256 + } + RW_SECTION_B 3M { + VBLOCK_B 8K + FW_MAIN_B(CBFS) + RW_FWID_B 256 + } + RW_ELOG(PRESERVE) 4K + RW_SHARED 16K { + SHARED_DATA 8K + VBLOCK_DEV 8K + } + RW_VPD(PRESERVE) 8K + RW_NVRAM(PRESERVE) 20K + SMMSTORE(PRESERVE) 256K + RW_LEGACY(CBFS) + EC_BODY@15872K 256K + RW_MRC_CACHE(PRESERVE) 120K + } +} diff --git a/src/mainboard/amd/crater/devicetree_renoir.cb b/src/mainboard/amd/crater/devicetree_renoir.cb new file mode 100644 index 0000000..2a295e0 --- /dev/null +++ b/src/mainboard/amd/crater/devicetree_renoir.cb @@ -0,0 +1,134 @@ +# SPDX-License-Identifier: GPL-2.0-only + + +chip soc/amd/cezanne + register "common_config.espi_config" = "{ + .std_io_decode_bitmap = ESPI_DECODE_IO_0x80_EN | ESPI_DECODE_IO_0X2E_0X2F_EN, + .generic_io_range[0] = { + .base = 0x662, + .size = 8, + }, + .io_mode = ESPI_IO_MODE_QUAD, + .op_freq_mhz = ESPI_OP_FREQ_16_MHZ, + .crc_check_enable = 1, + .alert_pin = ESPI_ALERT_PIN_PUSH_PULL, + .periph_ch_en = 1, + .vw_ch_en = 1, + .oob_ch_en = 1, + .flash_ch_en = 0, + }" + + # Set FADT Configuration + register "common_config.fadt_boot_arch" = "ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042" + register "common_config.fadt_flags" = "ACPI_FADT_SLEEP_BUTTON" # See table 5-34 ACPI 6.3 spec + + # ACP Configuration + register "acp_i2s_use_external_48mhz_osc" = "true" + register "common_config.acp_config.acp_pin_cfg" = "I2S_PINS_I2S_TDM" + register "common_config.acp_config" = "{ + .acp_pin_cfg = I2S_PINS_I2S_TDM, + .acp_i2s_wake_enable = 0, + .acp_pme_enable = 0, + }" + + # I2C Pad Control RX Select Configuration + register "i2c_pad[0].rx_level" = "I2C_PAD_RX_3_3V" + register "i2c_pad[1].rx_level" = "I2C_PAD_RX_3_3V" + register "i2c_pad[2].rx_level" = "I2C_PAD_RX_3_3V" + register "i2c_pad[3].rx_level" = "I2C_PAD_RX_3_3V" + + register "s0ix_enable" = "false" + + # general purpose PCIe clock output configuration + register "gpp_clk_config[0]" = "GPP_CLK_ON" + register "gpp_clk_config[1]" = "GPP_CLK_ON" + register "gpp_clk_config[2]" = "GPP_CLK_ON" + register "gpp_clk_config[3]" = "GPP_CLK_ON" + register "gpp_clk_config[4]" = "GPP_CLK_ON" + register "gpp_clk_config[5]" = "GPP_CLK_ON" + register "gpp_clk_config[6]" = "GPP_CLK_ON" + + register "pspp_policy" = "DXIO_PSPP_BALANCED" + + device domain 0 on + device ref iommu on end + device ref gpp_gfx_bridge_0 on end #GFX + device ref gpp_gfx_bridge_1 on end + device ref gpp_bridge_0 off end + device ref gpp_bridge_1 off end + device ref gpp_bridge_2 on end + device ref gpp_bridge_3 on end # NVME + device ref gpp_bridge_4 off end + device ref gpp_bridge_5 off end + device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A + device ref gfx on end # Internal GPU (GFX) + device ref gfx_hda on end # gfx_hda + device ref crypto on end # Crypto Coprocessor + device ref xhci_0 on # USB 3.1 (USB0) + chip drivers/usb/acpi + device ref xhci_0_root_hub on + chip drivers/usb/acpi + device ref usb3_port0 on end + end + chip drivers/usb/acpi + device ref usb3_port1 on end + end + chip drivers/usb/acpi + device ref usb2_port0 on end + end + chip drivers/usb/acpi + device ref usb2_port1 on end + end + chip drivers/usb/acpi + device ref usb2_port2 on end + end + chip drivers/usb/acpi + device ref usb2_port3 on end + end + end + end + end + device ref xhci_1 on # USB 3.1 (USB1) + chip drivers/usb/acpi + device ref xhci_1_root_hub on + chip drivers/usb/acpi + device ref usb3_port4 on end + end + chip drivers/usb/acpi + device ref usb3_port5 on end + end + chip drivers/usb/acpi + device ref usb2_port4 on end + end + chip drivers/usb/acpi + device ref usb2_port5 on end + end + chip drivers/usb/acpi + device ref usb2_port6 on end + end + chip drivers/usb/acpi + device ref usb2_port7 on end + end + end + end + end + device ref acp on end # Audio Processor (ACP) + device ref hda on end # Audio Processor HD Audio Controller + end + + device ref gpp_bridge_b on # Internal GPP Bridge 1 to Bus B + device ref sata_0 on end # SATA 0 + device ref sata_1 on end # SATA 1 + device ref xgbe_0 on end # XGBE0 + device ref xgbe_1 on end # XGBE1 + end + end + + device ref i2c_0 on end + device ref i2c_1 on end + device ref i2c_2 on end + device ref i2c_3 on end + device ref uart_0 on end # UART0 + device ref uart_1 on end # UART1 + +end diff --git a/src/mainboard/amd/crater/dsdt.asl b/src/mainboard/amd/crater/dsdt.asl new file mode 100644 index 0000000..7b8982a --- /dev/null +++ b/src/mainboard/amd/crater/dsdt.asl @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +DefinitionBlock ( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x00010001 /* OEM Revision */ + ) +{ + #include <acpi/dsdt_top.asl> + + #include <soc.asl> +} diff --git a/src/mainboard/amd/crater/early_gpio.c b/src/mainboard/amd/crater/early_gpio.c new file mode 100644 index 0000000..038910b --- /dev/null +++ b/src/mainboard/amd/crater/early_gpio.c @@ -0,0 +1,74 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <gpio.h> +#include "gpio.h" + +/* GPIO pins used by coreboot should be initialized in bootblock */ + +static const struct soc_amd_gpio gpio_set_stage_reset[] = { + PAD_NF(GPIO_0, PWR_BTN_L, PULL_UP), + PAD_NF(GPIO_1, SYS_RESET_L, PULL_UP), + PAD_NF(GPIO_2, WAKE_L, PULL_UP), + PAD_GPI(GPIO_3, PULL_UP), + /* TPM CS */ + PAD_NF(GPIO_129, KBRST_L, PULL_NONE), + /* SPI_ROM_REQ */ + PAD_NF(GPIO_67, SPI_ROM_REQ, PULL_NONE), + /* SPI_ROM_GNT */ + PAD_NF(GPIO_76, SPI_ROM_GNT, PULL_NONE), + /* LPC_PME */ + PAD_NF(GPIO_22, LPC_PME_L, PULL_NONE), + + /* Deassert PCIe Reset lines */ + /* PCIE_RST0_L */ + PAD_NFO(GPIO_26, PCIE_RST_L, HIGH), + /* PCIE_RST1_L */ + PAD_NFO(GPIO_27, PCIE_RST1_L, HIGH), + /* M2_SSD0_RST */ + PAD_GPO(GPIO_24, HIGH), + /* DEVSLP1 */ + PAD_NFO(GPIO_6, DEVSLP1, LOW), + + /*I2S SP/BT Audio & Record*/ + PAD_NF(GPIO_8, FCH_ACP_I2S_LRCLK, PULL_DOWN), + PAD_NF(GPIO_7, FCH_ACP_I2S_SDIN, PULL_DOWN), + + /*MDIO0_SCL*/ + PAD_NF(GPIO_10, MDIO0_SCL, PULL_DOWN), + /*MDIO0_SDA*/ + PAD_NF(GPIO_40, MDIO0_SDA, PULL_DOWN), + /*MDIO1_SCL*/ + PAD_NF(GPIO_9, MDIO1_SCL, PULL_DOWN), + /*MDIO1_SDA*/ + PAD_NF(GPIO_23, MDIO1_SDA, PULL_DOWN), + + + /* Enable UART 0 */ + /* UART0_RXD */ + PAD_NF(GPIO_141, UART0_RXD, PULL_NONE), + /* UART0_TXD */ + PAD_NF(GPIO_143, UART0_TXD, PULL_NONE), + /* FANOUT0 */ + PAD_NF(GPIO_85, FANOUT0, PULL_NONE), + + /* I2C0 SCL */ + PAD_NF(GPIO_145, I2C0_SCL, PULL_NONE), + /* I2C0 SDA */ + PAD_NF(GPIO_146, I2C0_SDA, PULL_NONE), + /* I2C1 SCL */ + PAD_NF(GPIO_147, I2C1_SCL, PULL_NONE), + /* I2C1 SDA */ + PAD_NF(GPIO_148, I2C1_SDA, PULL_NONE), + /* I2C2_SCL */ + PAD_NF(GPIO_113, I2C2_SCL, PULL_NONE), + /* I2C2_SDA */ + PAD_NF(GPIO_114, I2C2_SDA, PULL_NONE), + /* I2C3_SCL*/ + PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE), + /* I2C3_SDA*/ + PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE), +}; +void mainboard_program_early_gpios(void) +{ + gpio_configure_pads(gpio_set_stage_reset, ARRAY_SIZE(gpio_set_stage_reset)); +} diff --git a/src/mainboard/amd/crater/ec.c b/src/mainboard/amd/crater/ec.c new file mode 100644 index 0000000..20fad1d --- /dev/null +++ b/src/mainboard/amd/crater/ec.c @@ -0,0 +1,171 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <ec/acpi/ec.h> +#include <stdint.h> +#include <gpio.h> +#include "ec.h" + +#define CRATER_EC_CMD 0x666 +#define CRATER_EC_DATA 0x662 + +#define ENABLE_M2_SSD1 1 +#define EC_GPIO_0_ADDR 0xA0 +#define EC_EVAL_PWREN BIT(0) + +#define EC_GPIO_2_ADDR 0xA2 +#define EC2_EVAL_SLOT_PWREN BIT(5) +#define EC2_EVAL_19V_EN BIT(2) +#define EC2_DT_PWREN BIT(6) + +#define EC_GPIO_3_ADDR 0xA3 +#define EC3_WLAN_RST_AUX BIT(5) +#define EC3_WWAN_RST_AUX BIT(4) +#define EC3_SD_RST_AUX BIT(3) +#define EC3_DT_RST BIT(2) +#define EC3_LOM_RST_AUX BIT(1) +#define EC3_EVAL_RST_AUX BIT(0) +#define EC3_TBT_RST BIT(7) + +#define EC_GPIO_4_ADDR 0xA4 +#define EC4_TBT_PWREN BIT(0) + +#define EC_GPIO_7_ADDR 0xA7 +#define EC7_SSD_HDD_SW BIT(5) +#define EC7_ODD_SSD_SW BIT(4) +#define EC7_CAM1_EN BIT(0) + +#define EC_GPIO_8_ADDR 0xA8 +#define EC8_ODD_PWR_EN BIT(0) +#define EC8_HDD_PWR_EN BIT(1) +#define EC8_M2SSD_PWREN BIT(5) +#define EC8_WL_RADIO BIT(6) +#define EC8_BT_RADIO BIT(7) + +#define EC_GPIO_9_ADDR 0xA9 +#define SMBUS1_DEV_MUX_SW BIT(0) // ECRAMxA9[0] +#define SMBUS0_DEV_MUX_SW BIT(1) // ECRAMxA9[1] +#define MUX0_S0 BIT(2) // ECRAMxA9[2] +#define MUX0_S1 BIT(3) // ECRAMxA9[3] +#define MUX1_S0 BIT(4) // ECRAMxA9[4] +#define MUX1_S1 BIT(5) // ECRAMxA9[5] +#define MUX2_S0 BIT(6) // ECRAMxA9[6] +#define MUX2_S1 BIT(7) // ECRAMxA9[7] + + +#define EC_GPIO_A_ADDR 0xAA +#define ECA_MUX2_S0 BIT(7) +#define ECA_MUX2_S1 BIT(6) +#define ECA_MUX1_S0 BIT(5) +#define ECA_MUX1_S1 BIT(4) +#define ECA_MUX0_S0 BIT(3) +#define ECA_MUX0_S1 BIT(2) +#define ECA_SMBUS1_EN BIT(1) +#define ECA_SMBUS0_EN BIT(0) + +#define EC_GPIO_C_ADDR 0xAC +#define ECC_TPNL_BUF_EN BIT(6) +#define ECC_TPAD_BUF_EN BIT(5) +#define ECC_NFC_BUF_EN BIT(4) + +#define EC_GPIO_D_ADDR 0xAD +#define ECD_TPNL_PWR_EN BIT(7) +#define ECD_TPNL_EN BIT(6) +#define ECD_SSD1_PWR_EN BIT(5) +#define ECD_FPR_PWR_EN BIT(3) +#define ECD_FPR_OFF_N BIT(2) +#define ECD_FPR_LOCK_N BIT(1) +#define ECD_TPAD_DISABLE_N BIT(0) + +#define EC_GPIO_E_ADDR 0xAE +#define ECE_LOM_PWR_EN BIT(7) +#define ECE_SSD0_PWR_EN BIT(6) +#define ECE_SD_PWR_EN BIT(5) +#define ECE_WLAN_PWR_EN BIT(4) +#define ECE_WWAN_PWR_EN BIT(3) +#define ECE_CAM_PWR_EN BIT(2) +#define ECE_FPR_N_GBE_SEL BIT(1) +#define ECE_BT_N_TPNL_SEL BIT(0) + +#define EC_GPIO_F_ADDR 0xAF +#define ECF_CAM_FW_WP_N BIT(7) +#define ECF_I2C_MUX_OE_N BIT(4) +#define ECF_WLAN0_N_WWAN1_SW BIT(1) +#define ECF_WWAN0_N_WLAN1_SW BIT(0) + +#define EC_GPIO_G_ADDR 0xB0 +#define ECG_IR_LED_PWR_EN BIT(7) +#define ECG_U0_WLAN_HDR_SEL BIT(6) +#define ECG_DT_SSD1_MUX_OFF BIT(5) +#define ECG_WLAN_WWAN_MUX_OFF BIT(4) + +#define ECRAM_BOARDID_OFFSET 0x93 +#define CRATER_REVB 0x42 + +static void configure_ec_gpio(void) +{ + uint8_t tmp; + + tmp = ec_read(EC_GPIO_2_ADDR); + printk(BIOS_SPEW, "A2: Write reg [0x%02x] = 0x%02x\n", EC_GPIO_2_ADDR, tmp); + if (CONFIG(ENABLE_EVAL_CARD)) { + tmp |= EC2_EVAL_SLOT_PWREN; + if (CONFIG(ENABLE_EVAL_19V)) { + tmp |= EC2_EVAL_19V_EN; + } else { + tmp &= ~EC2_EVAL_19V_EN; + } + } else { + tmp &= ~EC2_EVAL_SLOT_PWREN; + tmp &= ~EC2_EVAL_19V_EN; + } + printk(BIOS_SPEW, "Write reg [0x%02x] = 0x%02x\n", EC_GPIO_2_ADDR, tmp); + ec_write(EC_GPIO_2_ADDR, tmp); + + tmp = ec_read(EC_GPIO_7_ADDR); + printk(BIOS_SPEW, "A7: Write reg [0x%02x] = 0x%02x\n", EC_GPIO_7_ADDR, tmp); + if (ENABLE_M2_SSD1) { + tmp |= (EC7_ODD_SSD_SW|EC7_SSD_HDD_SW); + } else { + tmp &= ~(EC7_ODD_SSD_SW|EC7_SSD_HDD_SW); + } + printk(BIOS_SPEW, "Write reg [0x%02x] = 0x%02x\n", EC_GPIO_7_ADDR, tmp); + ec_write(EC_GPIO_7_ADDR, tmp); + + tmp = ec_read(EC_GPIO_8_ADDR); + printk(BIOS_SPEW, "A8: Write reg [0x%02x] = 0x%02x\n", EC_GPIO_8_ADDR, tmp); + if (ENABLE_M2_SSD1) { + tmp |= EC8_M2SSD_PWREN; + } else { + tmp &= ~EC8_M2SSD_PWREN; + } + printk(BIOS_SPEW, "Write reg [0x%02x] = 0x%02x\n", EC_GPIO_8_ADDR, tmp); + ec_write(EC_GPIO_8_ADDR, tmp); +} + +static const struct soc_amd_gpio RevA_gpio_set_stage_ram[] = { + /* PCIE x8 SLOT*/ + PAD_GPO(GPIO_4, HIGH), +}; + +static const struct soc_amd_gpio RevB_gpio_set_stage_ram[] = { + PAD_GPI(GPIO_4, PULL_UP), + PAD_GPO(GPIO_12, LOW), +}; + +void crater_boardrevision(void) +{ + uint8_t BoardRev; + BoardRev = ec_read(ECRAM_BOARDID_OFFSET + 0x3); + if(BoardRev == CRATER_REVB) + gpio_configure_pads(RevB_gpio_set_stage_ram, ARRAY_SIZE(RevB_gpio_set_stage_ram)); + else + gpio_configure_pads(RevA_gpio_set_stage_ram, ARRAY_SIZE(RevA_gpio_set_stage_ram)); +} + +void crater_ec_init(void) +{ + ec_set_ports(CRATER_EC_CMD, CRATER_EC_DATA); + crater_boardrevision(); + configure_ec_gpio(); +} diff --git a/src/mainboard/amd/crater/ec.h b/src/mainboard/amd/crater/ec.h new file mode 100644 index 0000000..78fb36c --- /dev/null +++ b/src/mainboard/amd/crater/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef CRATER_EC_H +#define CRATER_EC_H + +void crater_ec_init(void); +void crater_boardrevision(void); +#endif /* CRATER_EC_H */ diff --git a/src/mainboard/amd/crater/gpio.c b/src/mainboard/amd/crater/gpio.c new file mode 100644 index 0000000..ee4c7c6 --- /dev/null +++ b/src/mainboard/amd/crater/gpio.c @@ -0,0 +1,77 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <gpio.h> +#include "gpio.h" + +/* + * As a rule of thumb, GPIO pins used by coreboot should be initialized at + * bootblock while GPIO pins used only by the OS should be initialized at + * ramstage. + */ +static const struct soc_amd_gpio gpio_set_stage_ram[] = { + PAD_NF(GPIO_0, PWR_BTN_L, PULL_UP), + PAD_NF(GPIO_1, SYS_RESET_L, PULL_UP), + PAD_NF(GPIO_2, WAKE_L, PULL_UP), + PAD_GPI(GPIO_3, PULL_UP), + /* TPM CS */ + PAD_NF(GPIO_129, KBRST_L, PULL_NONE), + /* SPI_ROM_REQ */ + PAD_NF(GPIO_67, SPI_ROM_REQ, PULL_NONE), + /* SPI_ROM_GNT */ + PAD_NF(GPIO_76, SPI_ROM_GNT, PULL_NONE), + /* LPC_PME */ + PAD_NF(GPIO_22, LPC_PME_L, PULL_NONE), + + /* Deassert PCIe Reset lines */ + /* PCIE_RST0_L */ + PAD_NFO(GPIO_26, PCIE_RST_L, HIGH), + /* PCIE_RST1_L */ + PAD_NFO(GPIO_27, PCIE_RST1_L, HIGH), + /* M2_SSD0_RST */ + PAD_GPO(GPIO_24, HIGH), + /* DEVSLP1 */ + PAD_NFO(GPIO_6, DEVSLP1, LOW), + + /*I2S SP/BT Audio & Record*/ + PAD_NF(GPIO_8, FCH_ACP_I2S_LRCLK, PULL_DOWN), + PAD_NF(GPIO_7, FCH_ACP_I2S_SDIN, PULL_DOWN), + + /*MDIO0_SCL*/ + PAD_NF(GPIO_10, MDIO0_SCL, PULL_DOWN), + /*MDIO0_SDA*/ + PAD_NF(GPIO_40, MDIO0_SDA, PULL_DOWN), + /*MDIO1_SCL*/ + PAD_NF(GPIO_9, MDIO1_SCL, PULL_DOWN), + /*MDIO1_SDA*/ + PAD_NF(GPIO_23, MDIO1_SDA, PULL_DOWN), + + /* Enable UART 0 */ + /* UART0_RXD */ + PAD_NF(GPIO_141, UART0_RXD, PULL_NONE), + /* UART0_TXD */ + PAD_NF(GPIO_143, UART0_TXD, PULL_NONE), + /* FANOUT0 */ + PAD_NF(GPIO_85, FANOUT0, PULL_NONE), + + /* I2C0 SCL */ + PAD_NF(GPIO_145, I2C0_SCL, PULL_NONE), + /* I2C0 SDA */ + PAD_NF(GPIO_146, I2C0_SDA, PULL_NONE), + /* I2C1 SCL */ + PAD_NF(GPIO_147, I2C1_SCL, PULL_NONE), + /* I2C1 SDA */ + PAD_NF(GPIO_148, I2C1_SDA, PULL_NONE), + /* I2C2_SCL*/ + PAD_NF(GPIO_113, I2C2_SCL, PULL_NONE), + /* I2C2_SDA */ + PAD_NF(GPIO_114, I2C2_SDA, PULL_NONE), + /* I2C3_SCL*/ + PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE), + /* I2C3_SDA*/ + PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE), +}; + +void mainboard_program_gpios(void) +{ + gpio_configure_pads(gpio_set_stage_ram, ARRAY_SIZE(gpio_set_stage_ram)); +} diff --git a/src/mainboard/amd/crater/gpio.h b/src/mainboard/amd/crater/gpio.h new file mode 100644 index 0000000..04c98c5 --- /dev/null +++ b/src/mainboard/amd/crater/gpio.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +void mainboard_program_early_gpios(void); /* bootblock GPIO configuration */ +void mainboard_program_gpios(void); /* ramstage GPIO configuration */ + +#endif /* MAINBOARD_GPIO_H */ diff --git a/src/mainboard/amd/crater/mainboard.c b/src/mainboard/amd/crater/mainboard.c new file mode 100644 index 0000000..eb13e07 --- /dev/null +++ b/src/mainboard/amd/crater/mainboard.c @@ -0,0 +1,63 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <amdblocks/acpi.h> +#include <amdblocks/amd_pci_util.h> +#include <commonlib/helpers.h> +#include <device/device.h> +#include <types.h> +#include "gpio.h" + +/* The IRQ mapping in fch_irq_map ends up getting written to the indirect address space that is + accessed via I/O ports 0xc00/0xc01. */ + +/* + * This controls the device -> IRQ routing. + * + * Hardcoded IRQs: + * 0: timer < soc/amd/common/acpi/lpc.asl + * 1: i8042 - Keyboard + * 2: cascade + * 8: rtc0 <- soc/amd/common/acpi/lpc.asl + * 9: acpi <- soc/amd/common/acpi/lpc.asl + */ +static const struct fch_irq_routing fch_irq_map[] = { + { PIRQ_A, 12, PIRQ_NC }, + { PIRQ_B, 14, PIRQ_NC }, + { PIRQ_C, 15, PIRQ_NC }, + { PIRQ_D, 12, PIRQ_NC }, + { PIRQ_E, 14, PIRQ_NC }, + { PIRQ_F, 15, PIRQ_NC }, + { PIRQ_G, 12, PIRQ_NC }, + { PIRQ_H, 14, PIRQ_NC }, + + { PIRQ_SCI, ACPI_SCI_IRQ, ACPI_SCI_IRQ }, + { PIRQ_SDIO, PIRQ_NC, PIRQ_NC }, + { PIRQ_GPIO, 11, 11 }, + { PIRQ_I2C0, 10, 10 }, + { PIRQ_I2C1, 7, 7 }, + { PIRQ_I2C2, 6, 6 }, + { PIRQ_I2C3, 5, 5 }, + { PIRQ_UART0, 4, 4 }, + { PIRQ_UART1, 3, 3 }, + + /* The MISC registers are not interrupt numbers */ + { PIRQ_MISC, 0xfa, 0x00 }, + { PIRQ_MISC0, 0x91, 0x00 }, + { PIRQ_HPET_L, 0x00, 0x00 }, + { PIRQ_HPET_H, 0x00, 0x00 }, +}; + +const struct fch_irq_routing *mb_get_fch_irq_mapping(size_t *length) +{ + *length = ARRAY_SIZE(fch_irq_map); + return fch_irq_map; +} + +static void mainboard_init(void *chip_info) +{ + mainboard_program_gpios(); +} + +struct chip_operations mainboard_ops = { + .init = mainboard_init, +}; diff --git a/src/mainboard/amd/crater/port_descriptors_renoir.c b/src/mainboard/amd/crater/port_descriptors_renoir.c new file mode 100644 index 0000000..365a037 --- /dev/null +++ b/src/mainboard/amd/crater/port_descriptors_renoir.c @@ -0,0 +1,118 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <gpio.h> +#include <soc/platform_descriptors.h> +#include <soc/cpu.h> +#include <types.h> +#include <amdblocks/cpu.h> +#include <soc/pci_devs.h> +#include <console/console.h> +#include <ec/acpi/ec.h> +#include <stdint.h> +void mainboard_fsp_mainboard_params_init(FSP_M_CONFIG *m_config); + +#define ECRAM_MACID_OFFSET 0x54 +#define MACID_LEN 12 + +#define ECRAM_BOARDID_OFFSET 0x93 + +#define CRATER_EC_CMD 0x666 +#define CRATER_EC_DATA 0x662 + +#define XGBE_PORT_0 0 +#define XGBE_PORT_1 1 +#define CRATER_REVB 0x42 + +static const fsp_dxio_descriptor crater_dxio_descriptors[] = { + { /* MXM */ + .engine_type = PCIE_ENGINE, + .port_present = true, + .start_logical_lane = 16, + .end_logical_lane = 23, + .device_number = 1, + .function_number = 1, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .turn_off_unused_lanes = false, + .clk_req = CLK_REQ0, + .gpio_group_id = GPIO_4, + .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} + }, + { /* SSD */ + .engine_type = PCIE_ENGINE, + .port_present = true, + .start_logical_lane = 8, + .end_logical_lane = 11, + .device_number = 2, + .function_number = 4, + .link_aspm = ASPM_DISABLED, + .link_aspm_L1_1 = false, + .link_aspm_L1_2 = false, + .turn_off_unused_lanes = false, + .clk_req = CLK_REQ3, + .gpio_group_id = GPIO_27, + .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} + }, +}; + +static fsp_ddi_descriptor crater_ddi_descriptors[] = { + { /* DDI0 - DP */ + .connector_type = DDI_DP, + .aux_index = DDI_AUX1, + .hdp_index = DDI_HDP1 + }, + { /* DDI1 - HDMI */ + .connector_type = DDI_HDMI, + .aux_index = DDI_AUX2, + .hdp_index = DDI_HDP2 + }, + { /* DDI2 */ + .connector_type = DDI_UNUSED_TYPE, + .aux_index = DDI_AUX3, + .hdp_index = DDI_HDP3, + }, + { /* DDI3 - DP (type C) */ + .connector_type = DDI_DP, + .aux_index = DDI_AUX3, + .hdp_index = DDI_HDP3, + }, + { /* DDI4 - DP (type C) */ + .connector_type = DDI_DP, + .aux_index = DDI_AUX4, + .hdp_index = DDI_HDP4, + } +}; + +void mainboard_get_dxio_ddi_descriptors( + const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num, + const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num) +{ + uint8_t BoardRev; + + if ((get_cpu_count() == 4 && get_threads_per_core() == 2) || get_cpu_count() == 2) + crater_ddi_descriptors[1].connector_type = DDI_UNUSED_TYPE; + + ec_set_ports(CRATER_EC_CMD, CRATER_EC_DATA); + BoardRev = ec_read(ECRAM_BOARDID_OFFSET + 0x3); + + if (CONFIG(ENABLE_EDP)) { + crater_ddi_descriptors[1].connector_type = DDI_EDP; + } else { + if (BoardRev == CRATER_REVB) + crater_ddi_descriptors[1].connector_type = DDI_DP; + else + crater_ddi_descriptors[1].connector_type = DDI_HDMI; + } + + + *dxio_descs = crater_dxio_descriptors; + *dxio_num = ARRAY_SIZE(crater_dxio_descriptors); + *ddi_descs = crater_ddi_descriptors; + *ddi_num = ARRAY_SIZE(crater_ddi_descriptors); +} + +void __weak mainboard_fsp_mainboard_params_init(FSP_M_CONFIG *m_config) +{ + +} diff --git a/src/soc/amd/cezanne/chip.h b/src/soc/amd/cezanne/chip.h index a8b7f22..2204b66 100644 --- a/src/soc/amd/cezanne/chip.h +++ b/src/soc/amd/cezanne/chip.h @@ -108,6 +108,8 @@ uint8_t tx_eq_post; uint8_t tx_vboost_lvl; } edp_tuningset; + /* If using an external 48MHz OSC for codec, will disable internal X48M_OSC */ + bool acp_i2s_use_external_48mhz_osc; }; #endif /* CEZANNE_CHIP_H */ diff --git a/src/soc/amd/cezanne/include/soc/gpio.h b/src/soc/amd/cezanne/include/soc/gpio.h index d12d667..9515abb 100644 --- a/src/soc/amd/cezanne/include/soc/gpio.h +++ b/src/soc/amd/cezanne/include/soc/gpio.h @@ -128,9 +128,9 @@ #define GPIO_6_IOMUX_DEVSLP1 1 #define GPIO_6_IOMUX_DEVSLP3 2 #define GPIO_7_IOMUX_GPIOxx 0 -#define GPIO_7_IOMUX_ACP_I2S_SDIN 1 +#define GPIO_7_IOMUX_FCH_ACP_I2S_SDIN 1 #define GPIO_8_IOMUX_GPIOxx 0 -#define GPIO_8_IOMUX_ACP_I2S_LRCLK 1 +#define GPIO_8_IOMUX_FCH_ACP_I2S_LRCLK 1 #define GPIO_9_IOMUX_GPIOxx 0 /* GPIO 9 IOMUX == 1 is reserved */ #define GPIO_9_IOMUX_MDIO1_SCL 2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85749?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibdb276fc160326c666d5990e34de5327813d9403 Gerrit-Change-Number: 85749 Gerrit-PatchSet: 1 Gerrit-Owner: Anand Vaikar <a.vaikar2021(a)gmail.com>

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[M] Change in coreboot[main]: amdfwtool: Check fletcher of each header
by Bao Zheng (Code Review) 24 Dec '24

24 Dec '24

Attention is currently required from: Felix Held, Julius Werner, Maximilian Brune, Paul Menzel, Zheng Bao. Bao Zheng has posted comments on this change by Bao Zheng. ( https://review.coreboot.org/c/coreboot/+/84338?usp=email ) Change subject: amdfwtool: Check fletcher of each header ...................................................................... Patch Set 6: (3 comments) File util/amdfwtool/amdfwtool.c: https://review.coreboot.org/c/coreboot/+/84338/comment/24a3196f_0a9b7cb8?us… : PS5, Line 540: psp_directory_table *dir = directory; > nit: […] Done https://review.coreboot.org/c/coreboot/+/84338/comment/cdee6d92_1cd0789a?us… : PS5, Line 544: uint32_t cookie = ((psp_directory_table *)directory)->header.cookie; > Do you need the extra type conversion? Can't you just use the `dir` from above? Done https://review.coreboot.org/c/coreboot/+/84338/comment/8e6d6256_e8c58598?us… : PS5, Line 549: if (directory == NULL) > You should probably do this check before dereferencing `directory` above Done -- To view, visit https://review.coreboot.org/c/coreboot/+/84338?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie7540386027c6449317e9b7c0b4fd22d09d4a3a3 Gerrit-Change-Number: 84338 Gerrit-PatchSet: 6 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Zheng Bao Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 24 Dec 2024 02:55:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Maximilian Brune <maximilian.brune(a)9elements.com>

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[S] Change in coreboot[main]: amdfwtool: Merge all the steps for A/B recovery into one branch
by Bao Zheng (Code Review) 24 Dec '24

24 Dec '24

Attention is currently required from: Felix Held, Julius Werner, Marshall Dawson, Zheng Bao, ritul guru. Bao Zheng has posted comments on this change by Bao Zheng. ( https://review.coreboot.org/c/coreboot/+/84531?usp=email ) Change subject: amdfwtool: Merge all the steps for A/B recovery into one branch ...................................................................... Patch Set 8: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/84531/comment/96e51915_bcb660a3?us… : PS7, Line 7: branches > branch Done -- To view, visit https://review.coreboot.org/c/coreboot/+/84531?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5f7213fd42c7f0ff5ecd9e504a6654cdfb1e3513 Gerrit-Change-Number: 84531 Gerrit-PatchSet: 8 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Zheng Bao Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 24 Dec 2024 02:55:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Bao Zheng <fishbaozi(a)gmail.com>

1 0

[M] Change in coreboot[main]: amdfwtool: Check fletcher of each header
by Bao Zheng (Code Review) 24 Dec '24

24 Dec '24

Attention is currently required from: Bao Zheng, Felix Held, Julius Werner, Paul Menzel, Zheng Bao. Hello Julius Werner, Zheng Bao, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84338?usp=email to look at the new patch set (#6). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: amdfwtool: Check fletcher of each header ...................................................................... amdfwtool: Check fletcher of each header If there is something wrong, now or in later change, like some bytes are accidentally and incorrectly written, we can detect it. Change-Id: Ie7540386027c6449317e9b7c0b4fd22d09d4a3a3 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M util/amdfwtool/amdfwtool.c 1 file changed, 92 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/84338/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/84338?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie7540386027c6449317e9b7c0b4fd22d09d4a3a3 Gerrit-Change-Number: 84338 Gerrit-PatchSet: 6 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Zheng Bao Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

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[S] Change in coreboot[main]: amdfwtool: Merge all the steps for A/B recovery into one branch
by Bao Zheng (Code Review) 24 Dec '24

24 Dec '24

Attention is currently required from: Felix Held, Julius Werner, Marshall Dawson, Zheng Bao, ritul guru. Hello Felix Held, Julius Werner, Marshall Dawson, Zheng Bao, build bot (Jenkins), ritul guru, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84531?usp=email to look at the new patch set (#8). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: amdfwtool: Merge all the steps for A/B recovery into one branch ...................................................................... amdfwtool: Merge all the steps for A/B recovery into one branch Clean up the code to make it more logical. This is for later changes to reorder the PSP Level 1, Level 2, ISH and BIOS tables. TEST=Identical test on all AMD platform Change-Id: I5f7213fd42c7f0ff5ecd9e504a6654cdfb1e3513 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M util/amdfwtool/amdfwtool.c 1 file changed, 6 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/84531/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/84531?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5f7213fd42c7f0ff5ecd9e504a6654cdfb1e3513 Gerrit-Change-Number: 84531 Gerrit-PatchSet: 8 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Zheng Bao Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

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[M] Change in coreboot[main]: mb/google/corsola: refactor mipi_panel_power_on function
by Yidi Lin (Code Review) 24 Dec '24

24 Dec '24

Attention is currently required from: Hung-Te Lin, Xinxiong Xu, Yang Wu, Yu-Ping Wu. Yidi Lin has posted comments on this change by Yang Wu. ( https://review.coreboot.org/c/coreboot/+/85745?usp=email ) Change subject: mb/google/corsola: refactor mipi_panel_power_on function ...................................................................... Patch Set 4: (2 comments) File src/mainboard/google/corsola/panel_starmie.c: https://review.coreboot.org/c/coreboot/+/85745/comment/49b2e8f8_eeef57cd?us… : PS4, Line 14: struct mipi_panel_config config = { : .en_gpio = GPIO_EN_PP3300_DISP_X, : .sync_gpio = GPIO_EN_PP3300_SDBRDG_X, : }; : tps65132s_power_on(&config); Instead of creating a new struct, we can declare `struct tps65132s_cfg` here and fill `struct tps65132s_reg_setting` in `tps65132s_power_on()`. File src/mainboard/google/corsola/panel_tps65132s.c: https://review.coreboot.org/c/coreboot/+/85745/comment/e8c2b126_d93f8320?us… : PS4, Line 29: PMIC_I2C_BUS cfg->i2c_bus -- To view, visit https://review.coreboot.org/c/coreboot/+/85745?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic0561e57d99ab55e6dcbb7744b2228c4cebb0d88 Gerrit-Change-Number: 85745 Gerrit-PatchSet: 4 Gerrit-Owner: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Xinxiong Xu <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Xinxiong Xu <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Tue, 24 Dec 2024 02:25:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: amdfwtool: Put all the steps for A/B recovery into one branches
by Bao Zheng (Code Review) 24 Dec '24

24 Dec '24

Attention is currently required from: Felix Held, Julius Werner, Marshall Dawson, Zheng Bao, ritul guru. Bao Zheng has posted comments on this change by Bao Zheng. ( https://review.coreboot.org/c/coreboot/+/84531?usp=email ) Change subject: amdfwtool: Put all the steps for A/B recovery into one branches ...................................................................... Patch Set 7: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/84531/comment/76be499b_1ae76887?us… : PS7, Line 7: branches branch -- To view, visit https://review.coreboot.org/c/coreboot/+/84531?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5f7213fd42c7f0ff5ecd9e504a6654cdfb1e3513 Gerrit-Change-Number: 84531 Gerrit-PatchSet: 7 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Zheng Bao Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 24 Dec 2024 01:40:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: drivers/mipi: Add support for KD_KD110N11_51IE panel
by Yidi Lin (Code Review) 24 Dec '24

24 Dec '24

Attention is currently required from: Yang Wu. Yidi Lin has posted comments on this change by Yang Wu. ( https://review.coreboot.org/c/coreboot/+/85741?usp=email ) Change subject: drivers/mipi: Add support for KD_KD110N11_51IE panel ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85741?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iecf7957185afd1c62f768d163bba69ed373b7f92 Gerrit-Change-Number: 85741 Gerrit-PatchSet: 2 Gerrit-Owner: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Xinxiong Xu <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Tue, 24 Dec 2024 01:28:19 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: mb/google/corsola: refactor mipi_panel_power_on function
by Yang Wu (Code Review) 24 Dec '24

24 Dec '24

Attention is currently required from: Hung-Te Lin, Xinxiong Xu, Yidi Lin, Yu-Ping Wu. Hello Hung-Te Lin, Xinxiong Xu, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85745?usp=email to look at the new patch set (#4). Change subject: mb/google/corsola: refactor mipi_panel_power_on function ...................................................................... mb/google/corsola: refactor mipi_panel_power_on function Refactor mipi_panel_power_on function in panel-starmie.c and panel-wyrdeer.c to reduce code duplication. BUG=b:379810871 TEST=emerge-staryu coreboot chromeos-bootimage and check both starmie and wyrdeer FW screen BRANCH=corsola Change-Id: Ic0561e57d99ab55e6dcbb7744b2228c4cebb0d88 Signed-off-by: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/corsola/Makefile.mk M src/mainboard/google/corsola/panel.h M src/mainboard/google/corsola/panel_starmie.c A src/mainboard/google/corsola/panel_tps65132s.c M src/mainboard/google/corsola/panel_wyrdeer.c 5 files changed, 64 insertions(+), 66 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/85745/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/85745?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic0561e57d99ab55e6dcbb7744b2228c4cebb0d88 Gerrit-Change-Number: 85745 Gerrit-PatchSet: 4 Gerrit-Owner: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Xinxiong Xu <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Xinxiong Xu <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com>

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[S] Change in coreboot[main]: mb/google/nissa/var/telith: Disable stylus function
by Kun Liu (Code Review) 24 Dec '24

24 Dec '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kun Liu, Nick Vaccaro, Subrata Banik. Hello Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Rui Zhou, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85738?usp=email to look at the new patch set (#3). Change subject: mb/google/nissa/var/telith: Disable stylus function ...................................................................... mb/google/nissa/var/telith: Disable stylus function Disable stylus function based on hardware schematic diagram.Because the external environment is floating, EE requires setting GPIO output to be pulled high or low. BUG=b:372506691 TEST=Local build successfully. Change-Id: I7b72284ab173633405d5de9541f0ea7520d09658 Signed-off-by: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/brya/variants/telith/gpio.c M src/mainboard/google/brya/variants/telith/overridetree.cb 2 files changed, 4 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/85738/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/85738?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7b72284ab173633405d5de9541f0ea7520d09658 Gerrit-Change-Number: 85738 Gerrit-PatchSet: 3 Gerrit-Owner: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Kun Liu <liukun11(a)huaqin.corp-partner.google.com>

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