coreboot-gerrit December 2024

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[L] Change in coreboot[main]: drivers/amd/opensil/mpio: Extract chip ops and per-device MPIO config
by Nick Kochlowski (Code Review) 23 Dec '24

23 Dec '24

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Martin L Roth, Matt DeVillier, Varshit Pandya. Nick Kochlowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85746?usp=email ) Change subject: drivers/amd/opensil/mpio: Extract chip ops and per-device MPIO config ...................................................................... drivers/amd/opensil/mpio: Extract chip ops and per-device MPIO config Factor out the MPIO per-device configuration function and chip operations struct from vendorcode into the openSIL driver as they are common for all SoCs. Change-Id: I9e496ab9df07f2f2ba32314cf5c5fd2861333e67 Signed-off-by: Nicolas Kochlowski <nickkochlowski(a)gmail.com> --- M src/drivers/amd/opensil/mpio/chip.c M src/mainboard/amd/birman/devicetree_phoenix_opensil.cb M src/mainboard/amd/birman/update_devicetree_phoenix_opensil.c M src/mainboard/amd/onyx_poc/devicetree.cb M src/soc/amd/genoa_poc/chipset.cb M src/soc/amd/phoenix/chipset_opensil.cb M src/vendorcode/amd/opensil/genoa_poc/mpio/chip.c M src/vendorcode/amd/opensil/genoa_poc/mpio/chip.h M src/vendorcode/amd/opensil/opensil.h M src/vendorcode/amd/opensil/stub/mpio/chip.c M src/vendorcode/amd/opensil/stub/mpio/chip.h 11 files changed, 137 insertions(+), 135 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/85746/1 diff --git a/src/drivers/amd/opensil/mpio/chip.c b/src/drivers/amd/opensil/mpio/chip.c index df488cf..a34ae71 100644 --- a/src/drivers/amd/opensil/mpio/chip.c +++ b/src/drivers/amd/opensil/mpio/chip.c @@ -6,7 +6,17 @@ #include "chip.h" #include "../opensil.h" +struct chip_operations drivers_amd_opensil_mpio_ops = { + .name = "AMD MPIO", +}; + void configure_mpio(void) { - opensil_mpio_config(); + opensil_mpio_common_config(); + + /* Find all devices with this chip that are directly below the chip */ + for (struct device *dev = &dev_root; dev; dev = dev->next) + if (dev->chip_ops == &drivers_amd_opensil_mpio_ops && + dev->chip_info != dev->upstream->dev->chip_info) + opensil_mpio_per_device_config(dev); } diff --git a/src/mainboard/amd/birman/devicetree_phoenix_opensil.cb b/src/mainboard/amd/birman/devicetree_phoenix_opensil.cb index 58c022e..d84a010 100644 --- a/src/mainboard/amd/birman/devicetree_phoenix_opensil.cb +++ b/src/mainboard/amd/birman/devicetree_phoenix_opensil.cb @@ -208,7 +208,7 @@ device domain 0 on device ref iommu on end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio register "type" = "IFTYPE_PCIE" register "start_lane" = "0" register "end_lane" = "7" @@ -217,7 +217,7 @@ # register "gpio_group" is currently not used device ref gpp_bridge_1_1 on end # MXM end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio register "type" = "IFTYPE_PCIE" register "start_lane" = "8" register "end_lane" = "11" @@ -231,7 +231,7 @@ end end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio register "type" = "IFTYPE_PCIE" register "start_lane" = "12" register "end_lane" = "12" @@ -239,7 +239,7 @@ register "clk_req" = "CLK_REQ6" device ref gpp_bridge_1_3 on end # GBE end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio register "type" = "IFTYPE_PCIE" register "start_lane" = "13" register "end_lane" = "13" @@ -247,7 +247,7 @@ register "clk_req" = "CLK_REQ5" device ref gpp_bridge_2_1 on end # SD end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio register "type" = "IFTYPE_PCIE" register "start_lane" = "14" register "end_lane" = "14" @@ -255,7 +255,7 @@ register "clk_req" = "CLK_REQ4" device ref gpp_bridge_2_2 on end # WWAN end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio register "type" = "IFTYPE_PCIE" register "start_lane" = "15" register "end_lane" = "15" @@ -263,7 +263,7 @@ register "clk_req" = "CLK_REQ3" device ref gpp_bridge_2_3 on end # WIFI end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio register "type" = "IFTYPE_PCIE" register "start_lane" = "16" register "end_lane" = "19" diff --git a/src/mainboard/amd/birman/update_devicetree_phoenix_opensil.c b/src/mainboard/amd/birman/update_devicetree_phoenix_opensil.c index 2640e74..75bedd4 100644 --- a/src/mainboard/amd/birman/update_devicetree_phoenix_opensil.c +++ b/src/mainboard/amd/birman/update_devicetree_phoenix_opensil.c @@ -4,7 +4,7 @@ #include <soc/amd/phoenix/chip.h> #include <soc/soc_util.h> #include <static.h> -#include <vendorcode/amd/opensil/chip/mpio/chip.h> +#include <drivers/amd/opensil/mpio/chip.h> #include "display_card_type.h" #include "update_devicetree.h" @@ -14,10 +14,10 @@ struct device *ssd1_bridge = DEV_PTR(gpp_bridge_1_2); struct device *wwan_bridge = DEV_PTR(gpp_bridge_2_2); struct device *wlan_bridge = DEV_PTR(gpp_bridge_2_3); - struct vendorcode_amd_opensil_chip_mpio_config *mxm_bridge_cfg = config_of(mxm_bridge); - struct vendorcode_amd_opensil_chip_mpio_config *ssd1_bridge_cfg = config_of(ssd1_bridge); - struct vendorcode_amd_opensil_chip_mpio_config *wwan_bridge_cfg = config_of(wwan_bridge); - struct vendorcode_amd_opensil_chip_mpio_config *wlan_bridge_cfg = config_of(wlan_bridge); + struct drivers_amd_opensil_mpio_config *mxm_bridge_cfg = config_of(mxm_bridge); + struct drivers_amd_opensil_mpio_config *ssd1_bridge_cfg = config_of(ssd1_bridge); + struct drivers_amd_opensil_mpio_config *wwan_bridge_cfg = config_of(wwan_bridge); + struct drivers_amd_opensil_mpio_config *wlan_bridge_cfg = config_of(wlan_bridge); /* Phoenix 2 has less PCIe lanes than Phoenix */ if (get_soc_type() == SOC_PHOENIX2) { diff --git a/src/mainboard/amd/onyx_poc/devicetree.cb b/src/mainboard/amd/onyx_poc/devicetree.cb index f3c0be4..1138e08 100644 --- a/src/mainboard/amd/onyx_poc/devicetree.cb +++ b/src/mainboard/amd/onyx_poc/devicetree.cb @@ -55,7 +55,7 @@ device domain 0 on device ref iommu_0 on end device ref rcec_0 on end - chip vendorcode/amd/opensil/chip/mpio # P2 + chip drivers/amd/opensil/mpio # P2 register "type" = "IFTYPE_PCIE" register "start_lane" = "48" register "end_lane" = "63" @@ -63,7 +63,7 @@ register "aspm" = "L1" device ref gpp_bridge_0_0_a on end end - chip vendorcode/amd/opensil/chip/mpio # G2 + chip drivers/amd/opensil/mpio # G2 register "type" = "IFTYPE_PCIE" register "start_lane" = "112" register "end_lane" = "127" @@ -72,7 +72,7 @@ register "hotplug" = "ServerExpress" device ref gpp_bridge_0_0_b on end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio register "type" = "IFTYPE_PCIE" register "start_lane" = "128" register "end_lane" = "131" @@ -93,7 +93,7 @@ device domain 1 on device ref iommu_1 on end device ref rcec_1 on end - chip vendorcode/amd/opensil/chip/mpio # P3 + chip drivers/amd/opensil/mpio # P3 register "type" = "IFTYPE_PCIE" register "start_lane" = "16" register "end_lane" = "31" @@ -101,7 +101,7 @@ register "aspm" = "L1" device ref gpp_bridge_1_0_a on end end - chip vendorcode/amd/opensil/chip/mpio # G3 + chip drivers/amd/opensil/mpio # G3 register "type" = "IFTYPE_PCIE" register "start_lane" = "80" register "end_lane" = "95" @@ -114,7 +114,7 @@ device domain 2 on device ref iommu_2 on end device ref rcec_2 on end - chip vendorcode/amd/opensil/chip/mpio # P1 + chip drivers/amd/opensil/mpio # P1 register "type" = "IFTYPE_PCIE" register "start_lane" = "32" register "end_lane" = "47" @@ -123,7 +123,7 @@ register "hotplug" = "ServerExpress" device ref gpp_bridge_2_0_a on end end - chip vendorcode/amd/opensil/chip/mpio # G1 + chip drivers/amd/opensil/mpio # G1 register "type" = "IFTYPE_PCIE" register "start_lane" = "64" register "end_lane" = "79" @@ -137,7 +137,7 @@ device domain 3 on device ref iommu_3 on end device ref rcec_3 on end - chip vendorcode/amd/opensil/chip/mpio # P0 + chip drivers/amd/opensil/mpio # P0 register "type" = "IFTYPE_PCIE" register "start_lane" = "0" register "end_lane" = "15" @@ -145,7 +145,7 @@ register "aspm" = "L1" device ref gpp_bridge_3_0_a on end end - chip vendorcode/amd/opensil/chip/mpio # G0 + chip drivers/amd/opensil/mpio # G0 register "type" = "IFTYPE_PCIE" register "start_lane" = "96" register "end_lane" = "111" @@ -153,7 +153,7 @@ register "aspm" = "L1" device ref gpp_bridge_3_0_b on end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio register "type" = "IFTYPE_PCIE" register "start_lane" = "132" register "end_lane" = "133" @@ -161,7 +161,7 @@ register "aspm" = "L1" device ref gpp_bridge_3_0_c on end # WAFL end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio register "type" = "IFTYPE_PCIE" register "start_lane" = "134" register "end_lane" = "134" @@ -170,7 +170,7 @@ register "bmc" = "1" device ref gpp_bridge_3_1_c on end # BMC end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio register "type" = "IFTYPE_PCIE" register "start_lane" = "135" register "end_lane" = "135" diff --git a/src/soc/amd/genoa_poc/chipset.cb b/src/soc/amd/genoa_poc/chipset.cb index 832b9b6..60eea56 100644 --- a/src/soc/amd/genoa_poc/chipset.cb +++ b/src/soc/amd/genoa_poc/chipset.cb @@ -16,78 +16,78 @@ device pci 00.3 alias rcec_0 off end device pci 01.0 on end # Dummy device function, do not disable - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 01.1 alias gpp_bridge_0_0_a off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 01.2 alias gpp_bridge_0_1_a off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 01.3 alias gpp_bridge_0_2_a off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 01.4 alias gpp_bridge_0_3_a off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 01.5 alias gpp_bridge_0_4_a off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 01.6 alias gpp_bridge_0_5_a off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 01.7 alias gpp_bridge_0_6_a off end end device pci 02.0 on end # Dummy device function, do not disable - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 02.1 alias gpp_bridge_0_7_a off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 02.2 alias gpp_bridge_0_8_a off end end device pci 03.0 on end # Dummy device function, do not disable - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 03.1 alias gpp_bridge_0_0_b off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 03.2 alias gpp_bridge_0_1_b off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 03.3 alias gpp_bridge_0_2_b off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 03.4 alias gpp_bridge_0_3_b off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 03.5 alias gpp_bridge_0_4_b off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 03.6 alias gpp_bridge_0_5_b off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 03.7 alias gpp_bridge_0_6_b off end end device pci 04.0 on end # Dummy device function, do not disable - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 04.1 alias gpp_bridge_0_7_b off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 04.2 alias gpp_bridge_0_8_b off end end device pci 05.0 on end # Dummy device function, do not disable - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 05.1 alias gpp_bridge_0_0_c off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 05.2 alias gpp_bridge_0_1_c off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 05.3 alias gpp_bridge_0_2_c off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 05.4 alias gpp_bridge_0_3_c off end end @@ -128,64 +128,64 @@ device pci 00.3 alias rcec_1 off end device pci 01.0 on end # Dummy device function, do not disable - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 01.1 alias gpp_bridge_1_0_a off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 01.2 alias gpp_bridge_1_1_a off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 01.3 alias gpp_bridge_1_2_a off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 01.4 alias gpp_bridge_1_3_a off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 01.5 alias gpp_bridge_1_4_a off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 01.6 alias gpp_bridge_1_5_a off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 01.7 alias gpp_bridge_1_6_a off end end device pci 02.0 on end # Dummy device function, do not disable - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 02.1 alias gpp_bridge_1_7_a off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 02.2 alias gpp_bridge_1_8_a off end end device pci 03.0 on end # Dummy device function, do not disable - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 03.1 alias gpp_bridge_1_0_b off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 03.2 alias gpp_bridge_1_1_b off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 03.3 alias gpp_bridge_1_2_b off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 03.4 alias gpp_bridge_1_3_b off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 03.5 alias gpp_bridge_1_4_b off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 03.6 alias gpp_bridge_1_5_b off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 03.7 alias gpp_bridge_1_6_b off end end device pci 04.0 on end # Dummy device function, do not disable - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 04.1 alias gpp_bridge_1_7_b off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 04.2 alias gpp_bridge_1_8_b off end end @@ -207,64 +207,64 @@ device pci 00.3 alias rcec_2 off end device pci 01.0 on end # Dummy device function, do not disable - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 01.1 alias gpp_bridge_2_0_a off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 01.2 alias gpp_bridge_2_1_a off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 01.3 alias gpp_bridge_2_2_a off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 01.4 alias gpp_bridge_2_3_a off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 01.5 alias gpp_bridge_2_4_a off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 01.6 alias gpp_bridge_2_5_a off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 01.7 alias gpp_bridge_2_6_a off end end device pci 02.0 on end # Dummy device function, do not disable - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 02.1 alias gpp_bridge_2_7_a off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 02.2 alias gpp_bridge_2_8_a off end end device pci 03.0 on end # Dummy device function, do not disable - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 03.1 alias gpp_bridge_2_0_b off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 03.2 alias gpp_bridge_2_1_b off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 03.3 alias gpp_bridge_2_2_b off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 03.4 alias gpp_bridge_2_3_b off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 03.5 alias gpp_bridge_2_4_b off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 03.6 alias gpp_bridge_2_5_b off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 03.7 alias gpp_bridge_2_6_b off end end device pci 04.0 on end # Dummy device function, do not disable - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 04.1 alias gpp_bridge_2_7_b off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 04.2 alias gpp_bridge_2_8_b off end end @@ -286,78 +286,78 @@ device pci 00.3 alias rcec_3 off end device pci 01.0 on end # Dummy device function, do not disable - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 01.1 alias gpp_bridge_3_0_a off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 01.2 alias gpp_bridge_3_1_a off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 01.3 alias gpp_bridge_3_2_a off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 01.4 alias gpp_bridge_3_3_a off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 01.5 alias gpp_bridge_3_4_a off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 01.6 alias gpp_bridge_3_5_a off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 01.7 alias gpp_bridge_3_6_a off end end device pci 02.0 on end # Dummy device function, do not disable - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 02.1 alias gpp_bridge_3_7_a off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 02.2 alias gpp_bridge_3_8_a off end end device pci 03.0 on end # Dummy device function, do not disable - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 03.1 alias gpp_bridge_3_0_b off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 03.2 alias gpp_bridge_3_1_b off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 03.3 alias gpp_bridge_3_2_b off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 03.4 alias gpp_bridge_3_3_b off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 03.5 alias gpp_bridge_3_4_b off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 03.6 alias gpp_bridge_3_5_b off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 03.7 alias gpp_bridge_3_6_b off end end device pci 04.0 on end # Dummy device function, do not disable - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 04.1 alias gpp_bridge_3_7_b off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 04.2 alias gpp_bridge_3_8_b off end end device pci 05.0 on end # Dummy device function, do not disable - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 05.1 alias gpp_bridge_3_0_c off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 05.2 alias gpp_bridge_3_1_c off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 05.3 alias gpp_bridge_3_2_c off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 05.4 alias gpp_bridge_3_3_c off end end diff --git a/src/soc/amd/phoenix/chipset_opensil.cb b/src/soc/amd/phoenix/chipset_opensil.cb index 0c5cfbc..42f36bc 100644 --- a/src/soc/amd/phoenix/chipset_opensil.cb +++ b/src/soc/amd/phoenix/chipset_opensil.cb @@ -9,37 +9,37 @@ device pci 01.0 on end # Dummy device function, do not disable # The PCIe GPP aliases in this SoC match the device and function numbers - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 01.1 alias gpp_bridge_1_1 hidden ops amd_external_pcie_gpp_ops end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 01.2 alias gpp_bridge_1_2 hidden ops amd_external_pcie_gpp_ops end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 01.3 alias gpp_bridge_1_3 hidden ops amd_external_pcie_gpp_ops end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 01.4 alias gpp_bridge_1_4 hidden ops amd_external_pcie_gpp_ops end end device pci 02.0 on end # Dummy device function, do not disable # The PCIe GPP aliases in this SoC match the device and function numbers - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 02.1 alias gpp_bridge_2_1 hidden ops amd_external_pcie_gpp_ops end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 02.2 alias gpp_bridge_2_2 hidden ops amd_external_pcie_gpp_ops end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 02.3 alias gpp_bridge_2_3 hidden ops amd_external_pcie_gpp_ops end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 02.4 alias gpp_bridge_2_4 hidden ops amd_external_pcie_gpp_ops end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 02.5 alias gpp_bridge_2_5 hidden ops amd_external_pcie_gpp_ops end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 02.6 alias gpp_bridge_2_6 hidden ops amd_external_pcie_gpp_ops end end diff --git a/src/vendorcode/amd/opensil/genoa_poc/mpio/chip.c b/src/vendorcode/amd/opensil/genoa_poc/mpio/chip.c index d20d1532..d70f47f 100644 --- a/src/vendorcode/amd/opensil/genoa_poc/mpio/chip.c +++ b/src/vendorcode/amd/opensil/genoa_poc/mpio/chip.c @@ -11,10 +11,6 @@ #include "chip.h" -struct chip_operations vendorcode_amd_opensil_chip_mpio_ops = { - .name = "AMD GENOA MPIO", -}; - static void mpio_params_config(void) { MPIOCLASS_INPUT_BLK *mpio_data = SilFindStructure(SilId_MpioClass, 0); @@ -127,7 +123,7 @@ mpio_data->EarlyBmcLinkDie = 0; } -static void opensil_mpio_per_device_config(struct device *dev) +void opensil_mpio_per_device_config(struct device *dev) { /* Cache *mpio_data from SilFindStructure */ static MPIOCLASS_INPUT_BLK *mpio_data = NULL; @@ -138,7 +134,7 @@ static uint32_t slot_num; const uint32_t domain = dev_get_domain_id(dev); const uint32_t devfn = dev->path.pci.devfn; - const struct vendorcode_amd_opensil_mpio_config *const config = dev->chip_info; + const struct drivers_amd_opensil_mpio_config *const config = dev->chip_info; printk(BIOS_DEBUG, "Setting MPIO port for domain 0x%x, PCI %d:%d\n", domain, PCI_SLOT(devfn), PCI_FUNC(devfn)); @@ -199,14 +195,8 @@ mpio_port++; } -void opensil_mpio_config(void) +void opensil_mpio_common_config(void) { mpio_params_config(); nbio_params_config(); - - /* Find all devices with this chip that are directly below the chip */ - for (struct device *dev = &dev_root; dev; dev = dev->next) - if (dev->chip_ops == &vendorcode_amd_opensil_chip_mpio_ops && - dev->chip_info != dev->upstream->dev->chip_info) - opensil_mpio_per_device_config(dev); } diff --git a/src/vendorcode/amd/opensil/genoa_poc/mpio/chip.h b/src/vendorcode/amd/opensil/genoa_poc/mpio/chip.h index 9b4d226..1937981 100644 --- a/src/vendorcode/amd/opensil/genoa_poc/mpio/chip.h +++ b/src/vendorcode/amd/opensil/genoa_poc/mpio/chip.h @@ -54,7 +54,7 @@ L0sL1, }; -struct vendorcode_amd_opensil_chip_mpio_config { +struct drivers_amd_opensil_mpio_config { enum mpio_type type; uint8_t start_lane; uint8_t end_lane; diff --git a/src/vendorcode/amd/opensil/opensil.h b/src/vendorcode/amd/opensil/opensil.h index 42eb221..935d1ca 100644 --- a/src/vendorcode/amd/opensil/opensil.h +++ b/src/vendorcode/amd/opensil/opensil.h @@ -17,6 +17,7 @@ void opensil_xSIM_timepoint_2(void); void opensil_xSIM_timepoint_3(void); -void opensil_mpio_config(void); +void opensil_mpio_common_config(void); +void opensil_mpio_per_device_config(struct device *dev); #endif diff --git a/src/vendorcode/amd/opensil/stub/mpio/chip.c b/src/vendorcode/amd/opensil/stub/mpio/chip.c index 8b0e218..ecd2df5 100644 --- a/src/vendorcode/amd/opensil/stub/mpio/chip.c +++ b/src/vendorcode/amd/opensil/stub/mpio/chip.c @@ -5,11 +5,12 @@ #include "chip.h" -struct chip_operations vendorcode_amd_opensil_chip_mpio_ops = { - .name = "AMD openSIL stub MPIO", -}; +void opensil_mpio_common_config(void) +{ + printk(BIOS_NOTICE, "openSIL stub: %s\n", __func__); +} -void opensil_mpio_config(void) +void opensil_mpio_per_device_config(struct device *dev) { printk(BIOS_NOTICE, "openSIL stub: %s\n", __func__); } diff --git a/src/vendorcode/amd/opensil/stub/mpio/chip.h b/src/vendorcode/amd/opensil/stub/mpio/chip.h index 4564633..58a8b3a 100644 --- a/src/vendorcode/amd/opensil/stub/mpio/chip.h +++ b/src/vendorcode/amd/opensil/stub/mpio/chip.h @@ -60,7 +60,7 @@ SLOT_POWER_LIMIT_DIVISOR_1000 = 3, /* Scale factor 0.001 */ }; -struct vendorcode_amd_opensil_chip_mpio_config { +struct drivers_amd_opensil_mpio_config { enum mpio_engine_type type; uint8_t start_lane; uint8_t end_lane; -- To view, visit https://review.coreboot.org/c/coreboot/+/85746?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9e496ab9df07f2f2ba32314cf5c5fd2861333e67 Gerrit-Change-Number: 85746 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Kochlowski <nickkochlowski(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

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[M] Change in coreboot[main]: drivers/amd/opensil/memmap.c: Factor out common memmap code to driver
by Nick Kochlowski (Code Review) 23 Dec '24

23 Dec '24

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Martin L Roth, Matt DeVillier, Nick Kochlowski, Varshit Pandya. Hello Felix Held, Fred Reitberger, Jason Glenesk, Martin L Roth, Matt DeVillier, Varshit Pandya, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85634?usp=email to look at the new patch set (#10). Change subject: drivers/amd/opensil/memmap.c: Factor out common memmap code to driver ...................................................................... drivers/amd/opensil/memmap.c: Factor out common memmap code to driver Refactor the vendercode openSIL memory map code and move all common calls that do not require any openSIL headers to the driver. Change-Id: I80b9bdd7fd633c7b12d695ced5d4b9b518570d80 Signed-off-by: Nicolas Kochlowski <nickkochlowski(a)gmail.com> --- M src/drivers/amd/opensil/Makefile.mk A src/drivers/amd/opensil/memmap.c M src/drivers/amd/opensil/opensil.h M src/soc/amd/genoa_poc/domain.c M src/soc/amd/phoenix/memmap.c M src/vendorcode/amd/opensil/genoa_poc/memmap.c M src/vendorcode/amd/opensil/opensil.h M src/vendorcode/amd/opensil/stub/ramstage.c 8 files changed, 112 insertions(+), 86 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/85634/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/85634?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I80b9bdd7fd633c7b12d695ced5d4b9b518570d80 Gerrit-Change-Number: 85634 Gerrit-PatchSet: 10 Gerrit-Owner: Nick Kochlowski <nickkochlowski(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Nick Kochlowski <nickkochlowski(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

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[M] Change in coreboot[main]: drivers/amd/opensil/mpio: Factor out common MPIO symbols from vendorcode
by Nick Kochlowski (Code Review) 23 Dec '24

23 Dec '24

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Martin L Roth, Martin Roth, Matt DeVillier, Varshit Pandya. Hello Felix Held, Fred Reitberger, Jason Glenesk, Martin L Roth, Matt DeVillier, Varshit Pandya, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85632?usp=email to look at the new patch set (#8). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: drivers/amd/opensil/mpio: Factor out common MPIO symbols from vendorcode ...................................................................... drivers/amd/opensil/mpio: Factor out common MPIO symbols from vendorcode Refactor vendorcode MPIO configuration functions to be invoked from the openSIL driver. Change-Id: I8b1f92f08565216dd93203a06015e3eec1e7bb69 Signed-off-by: Nicolas Kochlowski <nickkochlowski(a)gmail.com> --- M src/drivers/amd/opensil/Makefile.mk A src/drivers/amd/opensil/mpio/Makefile.mk A src/drivers/amd/opensil/mpio/chip.c R src/drivers/amd/opensil/mpio/chip.h M src/drivers/amd/opensil/opensil.h M src/drivers/amd/opensil/ramstage.c M src/vendorcode/amd/opensil/Kconfig M src/vendorcode/amd/opensil/genoa_poc/mpio/chip.c M src/vendorcode/amd/opensil/genoa_poc/ramstage.c M src/vendorcode/amd/opensil/opensil.h M src/vendorcode/amd/opensil/stub/mpio/chip.c 11 files changed, 72 insertions(+), 35 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/85632/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/85632?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8b1f92f08565216dd93203a06015e3eec1e7bb69 Gerrit-Change-Number: 85632 Gerrit-PatchSet: 8 Gerrit-Owner: Nick Kochlowski <nickkochlowski(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

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[M] Change in coreboot[main]: util/intelp2m: Move remapping reset source to common
by Maxim Polyakov (Code Review) 23 Dec '24

23 Dec '24

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85731?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: util/intelp2m: Move remapping reset source to common ...................................................................... util/intelp2m: Move remapping reset source to common TEST: 'make test' = PASS Change-Id: I315541b12f5f1fdf7c97c2ff8ddd305e30a447cc Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M util/intelp2m/platforms/adl/macro.go M util/intelp2m/platforms/apl/macro.go M util/intelp2m/platforms/cnl/macro.go M util/intelp2m/platforms/common/common.go M util/intelp2m/platforms/common/macro.go M util/intelp2m/platforms/ebg/macro.go M util/intelp2m/platforms/jsl/macro.go M util/intelp2m/platforms/lbg/macro.go M util/intelp2m/platforms/mtl/macro.go M util/intelp2m/platforms/snr/macro.go M util/intelp2m/platforms/tgl/macro.go 11 files changed, 101 insertions(+), 141 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/85731/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/85731?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I315541b12f5f1fdf7c97c2ff8ddd305e30a447cc Gerrit-Change-Number: 85731 Gerrit-PatchSet: 3 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[L] Change in coreboot[main]: soc/mediatek/mt8196: Add GPUEB support
by Yu-Ping Wu (Code Review) 23 Dec '24

23 Dec '24

Attention is currently required from: Andy Hsu, Hung-Te Lin, Jarried Lin. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85654?usp=email ) Change subject: soc/mediatek/mt8196: Add GPUEB support ...................................................................... Patch Set 3: (1 comment) File src/soc/mediatek/mt8196/gpueb.c: https://review.coreboot.org/c/coreboot/+/85654/comment/8c2211d8_20999aed?us… : PS2, Line 358: die > The gpueb init flow is critical for boot up. […] Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/85654?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0f10dfc753f73df97ea08a4c23e97de416832be2 Gerrit-Change-Number: 85654 Gerrit-PatchSet: 3 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Andy Hsu <andy.hsu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Andy Hsu <andy.hsu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Mon, 23 Dec 2024 15:19:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Andy Hsu <andy.hsu(a)mediatek.corp-partner.google.com> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com>

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[M] Change in coreboot[main]: drivers/mipi: Add support for KD_KD110N11_51IE panel
by Yu-Ping Wu (Code Review) 23 Dec '24

23 Dec '24

Attention is currently required from: Yang Wu, Yidi Lin. Yu-Ping Wu has posted comments on this change by Yang Wu. ( https://review.coreboot.org/c/coreboot/+/85741?usp=email ) Change subject: drivers/mipi: Add support for KD_KD110N11_51IE panel ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85741?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iecf7957185afd1c62f768d163bba69ed373b7f92 Gerrit-Change-Number: 85741 Gerrit-PatchSet: 1 Gerrit-Owner: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Xinxiong Xu <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Mon, 23 Dec 2024 15:09:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: soc/intel/alderlake: Change the maximum C state to C8
by Subrata Banik (Code Review) 23 Dec '24

23 Dec '24

Attention is currently required from: Dinesh Gehlot, Jayvik Desai, Michał Żygowski, Nick Vaccaro, Sean Rhodes. Subrata Banik has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/84622?usp=email ) Change subject: soc/intel/alderlake: Change the maximum C state to C8 ...................................................................... Patch Set 5: (1 comment) Patchset: PS5: ideally this should be reviewed by Intel team because this information is coming from some Intel document -- To view, visit https://review.coreboot.org/c/coreboot/+/84622?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idb3e4d34361c8ac25ef144c0d1cda9f801ed0c54 Gerrit-Change-Number: 84622 Gerrit-PatchSet: 5 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Mon, 23 Dec 2024 14:59:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: soc/intel/alderlake: Remove superflous compiler argument
by Kapil Porwal (Code Review) 23 Dec '24

23 Dec '24

Attention is currently required from: Dinesh Gehlot, Nick Vaccaro, Sean Rhodes, Subrata Banik. Kapil Porwal has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/84621?usp=email ) Change subject: soc/intel/alderlake: Remove superflous compiler argument ...................................................................... Patch Set 5: Code-Review+2 (1 comment) Patchset: PS5: You need to rebase it. -- To view, visit https://review.coreboot.org/c/coreboot/+/84621?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I92f6d1b0a7fed4730f11e572b076f5dfdb91d96f Gerrit-Change-Number: 84621 Gerrit-PatchSet: 5 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Mon, 23 Dec 2024 14:51:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: mb/google/nissa/var/telith: Disable stylus function
by Kapil Porwal (Code Review) 23 Dec '24

23 Dec '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kun Liu, Nick Vaccaro, Subrata Banik. Kapil Porwal has posted comments on this change by Kun Liu. ( https://review.coreboot.org/c/coreboot/+/85738?usp=email ) Change subject: mb/google/nissa/var/telith: Disable stylus function ...................................................................... Patch Set 2: (1 comment) File src/mainboard/google/brya/variants/telith/gpio.c: https://review.coreboot.org/c/coreboot/+/85738/comment/3c7c88f8_2ab2d868?us… : PS2, Line 46: PAD_CFG_GPO > Because the external environment is floating, EE requires setting GPIO output to be pulled high or l […] Please mention it in the commit message. -- To view, visit https://review.coreboot.org/c/coreboot/+/85738?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7b72284ab173633405d5de9541f0ea7520d09658 Gerrit-Change-Number: 85738 Gerrit-PatchSet: 2 Gerrit-Owner: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Mon, 23 Dec 2024 14:33:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kapil Porwal <kapilporwal(a)google.com> Comment-In-Reply-To: Kun Liu <liukun11(a)huaqin.corp-partner.google.com>

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[XS] Change in coreboot[main]: soc/intel/common/block/power_limit: Disable RAPL via MSR completely
by Mario Scheithauer (Code Review) 23 Dec '24

23 Dec '24

Attention is currently required from: Johannes Hahn, Uwe Poeche, Werner Zeh. Mario Scheithauer has posted comments on this change by Johannes Hahn. ( https://review.coreboot.org/c/coreboot/+/85606?usp=email ) Change subject: soc/intel/common/block/power_limit: Disable RAPL via MSR completely ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85606?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8272339a991667d5ba177f4755ec40e1961d729e Gerrit-Change-Number: 85606 Gerrit-PatchSet: 5 Gerrit-Owner: Johannes Hahn <johannes-hahn(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: siemens-bot Gerrit-Attention: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Attention: Johannes Hahn <johannes-hahn(a)siemens.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Mon, 23 Dec 2024 13:48:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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coreboot-gerrit December 2024